ICM7217 RENESAS | Alldatasheet
Document overview
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Technical content
Features
- Four Decade, Presettable Up-Down Counter with Parallel Zero Detect
- Settable Register with Contents Continuously Compared to Counter
- Directly Drives Multiplexed 7 Segment Common Anode or Common Cathode LED Displays
- On-Board Multiplex Scan Oscillator
- Schmitt Trigger On Count Input
- TTL Compatible BCD I/O Port, Carry/Borrow, Equal, and Zero Outputs
- Display Blank Control for Lower Power Operation; Quiescent Power Dissipation <5mW
- All Terminals Fully Protected Against Static Discharge
- Single 5V Supply Operation
Description
The ICM7217 is a four digit, presettable up/down counter with an onboard presettable register continuously compared to the counter. The ICM7217 is intended for use in hard-wired applications where thumbwheel switches are used for loading data, and simple SPDT switches are used for chip control. This circuit provides multiplexed 7 segment LED display outputs, with common anode or common cathode configurations available. Di git and segment drivers are provided to directly drive displays of up to 0.8 inch character height (common anode) at a 25% duty cycle. The frequency of the onboard multiplex oscillator may be controlled with a single capacitor , or the oscillator may be allowed to free run. Leading zeros can be blanked. The data appearing at the 7 segment and BCD outputs is latched; the content of the counter is transferred into the latches under external control by means of the Store pin. The ICM7217 (common anode) and ICM7217A (common cathode) versions are dec ade counters, providing a maximum count of 9999, while the ICM7217B (common anode) and ICM7217C (common cathode) are intended for timing purposes, providing a maximum count of 5959. This circuit provides 3 ma in outputs; a CARRY/BORROW output, which allows for direct cascading of counters, a ZERO output, which indicates when the count is zero, and an EQUAL output, which indicates when the count is equal to the value contained in the register. Data is multiplexed to and from the device by means of a three-state BCD I/O port. The CARRY/BORROW, EQUAL , ZERO outputs, and the BCD port will each drive one standard TTL load. To permit operation in noisy environments and to prevent multiple triggering with slo wly changing inputs, the count input is provided with a Schmitt trigger. Input frequency is guaranteed to 2MHz, although the device will typically run with fIN as high as 5MHz. Counting and comparing (EQUAL output) will typically run 750kHz maximum. Part Number Information PART NUMBER TEMP. RANGE (oC) PACKAGE DISPLAY DRIVER TYPE COUNT OPTION/ MAX COUNT PKG. NO. ICM7217AIPI -25 to 85 28 Ld PDIP Common Cathode Decade/9999 E28.6 ICM7217CIPl -25 to 85 28 Ld PDIP Common Cathode Timing/5959 E28.6 ICM7217IJI -25 to 85 28 Ld CERDIP Common Anode Decade/9999 F28.6 lCM7217BlJl -25 to 85 28 Ld CERDIP Common Anode Timing/5959 F28.6 FOR A POSSIBLE SUBSTITUTE PRODUCT call Central Applications 1-888-INTERSIL or email: centapp@intersil.com OBSOLETE PRODUCT
FN3167 Rev 3.00 Page 2 of 19 July 2001 Pinouts Functional Block Diagram ICM7217 (CERDIP) COMMON ANODE TOP VIEW ICM7217 (PDIP) COMMON CATHODE TOP VIEW CARRY/BORROW ZERO EQUAL BCD I/O 8s BCD I/O 4s BCD I/O 2s BCD I/O 1s COUNT INPUT STORE UP/DOWN LOAD REGISTER/OFF LOAD COUNTER/I/O OFF SCAN RESET VDD DISPLAY CONT. SEG b SEG e SEG f SEG d SEG a SEG c SEG g VSS ICM7217 ICM7217B CARRY/BORROW ZERO EQUAL BCD I/O 8s BCD I/O 4s BCD I/O 2s BCD I/O 1s COUNT INPUT STORE UP/DOWN LOAD REGISTER/OFF LOAD COUNTER/I/O OFF SCAN RESET SEG d SEG f SEG c VDD SEG a SEG g VSS SEG b SEG e DISPLAY CONT. ICM7217A ICM7217C T.G. RS ZERO U/D CL CARRY T.G. LATCH MUX T.G. RS ZERO U/D CL CARRY T.G. LATCH MUX T.G. RS ZERO U/D CL CARRY T.G. LATCH MUX T.G. RS ZERO U/D CL CARRY T.G. LATCH MUX 1234 T.G. COMP. REG. 1234 123 4 123 4 T.G. COMP. REG. T.G. COMP. REG. T.G. COMP. REG. BDC I/O ZERO UP/DN COUNT VDD VSS SEGMENT DECODER SEGMENT DRIVERS (7) DIGIT DRIVERS (4) A D4 D3 D2 D1 DISPLAY BLANK + OFF GB C D E F MUX. OSCILLATOR MUX. I/O AND DISPLAY CONTROL LOGIC 4 4DIGIT MUX SCAN DISPLAY LOAD LOAD RESET STORE EQUALCARRY/BARROW CONTROL REGISTER COUNTER L.R. L.C. RESET BCD I/O INPUTS COM. ANODE: PULL DOWN COM. CATHODE: PULL UP VDD VDD VDD VSS VDD VSS VDD VSS
FN3167 Rev 3.00 Page 3 of 19 July 2001 Absolute Maximum Ratings Thermal Information (Note 1) Operating Conditions Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) Maximum Junction Temperature CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than VDD or less than VSS may cause destructive device latchup. For this reason it is recommended that the power supply to the device be established before any inputs are applied and that in multiple systems the supply to the ICM7217 be turned on first. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = 5V, VSS = 0V, TA = 25oC, Display Diode Drop 1 .7V, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Current (Lowest Power Mode), IDD (7217) Display Off, LC, DC, UP/DN, ST, RS, BCD I/O Floating or at VDD (Note 1) - 350 500 A Supply Current, OPERATING, IOP Common Anode, Display On, all “8’s” 140 200 - mA Supply Current, OPERATING, IOP Common Cathode, Display On, all “8’s” 50 100 - mA VSUPPLY, VDD 4 . 555 . 5V Digit Driver Output Current, IDIG Common Anode, VOUT = VDD - 2.0V 140 200 - mA PEAK SEGment Driver Output Current, ISEG Common Anode, VOUT = +1.5V 20 35 - mA PEAK Digit Driver, Output Current, IDIG Common Cathode, VOUT = +1.0V -50 -75 - mA PEAK SEGment Driver Output Current, ISEG Common Cathode VOUT = VDD - 2V -9 -12.5 - mA PEAK ST, RS, UP/DN Input Pullup Current, IP VIN = VDD - 2V (Note 1) 5 25 - A
3 Level Input Impendance, ZIN 40 - 350 k
BCD I/O Input, High Voltage VBIH ICM7217 Common Anode (Note 2) 1.5 - - V ICM7217 Common Cathode (Note 2) 4.40 - - V BCD I/O Input, Low Voltage VBIL ICM7217 Common Anode (Note 2) - - 0.60 V ICM7217 Common Cathode (Note 2) - - 3.2V V BCD I/O Input, Pullup Current IBPU ICM7217 Common Cathode VIN = VDD - 2V (Note 2) 52 5- A BCD I/O Input Pulldown Current, IBPD ICM7217 Common Anode VIN = +2V (Note 2) 5 25 - A BCD I/O, ZERO, EQUAL Outputs Output High Voltage, VOH BCD I/O, CARRY/BORROW ZERO, EQUAL Outputs Output Low Voltage, VOL IOL = 1.6mA - - 0.4 V Count Input Frequency, fIN -20oC to 70oC- 5 - M H z Guaranteed 0 - 2 MHz Count Input Threshold, VTH (Note 3) - 2 - V Count Input Hysteresis, VHYS (Note 3) - 0.5 - V Count Input LO, VCIL - - 0.40 V Count Input HI, VCIH 3.5 - - V
FN3167 Rev 3.00 Page 4 of 19 July 2001 Display Scan Oscillator Frequency, fDS Free-running (SCAN Terminal Open Circuit) - 2.5 10 kHz Switching Specifications VDD = 5V, VSS = 0V, TA = 25oC PARAMETER MIN TYP MAX UNIT UP/DOWN Setup Time, tUCS 300 - - ns UP/DOWN Hold Time, tUCH 1500 750 - ns COUNT Pulse Width High, tCWH 250 100 - ns COUNT Pulse Width Low, tCWI 250 100 - ns COUNT to CARRY/BORROW Delay, tCB - 750 - ns CARRY/BORROW Pulse Width tBW - 100 - ns COUNT to EQUAL Delay, tCE - 500 - ns COUNT to ZERO Delay, tCZ - 300 - ns RESET Pulse Width, tRST 1000 500 - ns NOTES: 1. In the ICM7217 the UP/DOWN, STORE, RESET and the BCD I/O as inputs have pullup or pulldown devices which consume power when connected to the opposite supply. Under these conditions, with the display off, the device will consume typically 750A. 2. These voltages are adjusted to allow the use of thumbwheel switc hes for the ICM7217. Note that a high level is taken as an input logic zero for ICM7217 common-cathode versions. 3. Parameters not tested (Guaranteed by Design). Electrical Specifications VDD = 5V, VSS = 0V, TA = 25oC, Display Diode Drop 1 .7V, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FN3167 Rev 3.00 Page 9 of 19 July 2001 the COUNT INPUT provides hysteresis to prevent double trig- gering on slow rising edges and permits operation in noisy environments. The COUNT INPUT is inhibited during reset and load counter operations. The STORE pin controls the internal latches and consequently the signals appearing at th e 7-Segment and BCD outputs. Bringing the STORE pin low transfers the contents of the counter into the latches. The counter is asynchronously reset to 0000 by bringing the RESET pin low. The circuit performs the reset operation by forcing the BCD input lines to zero, and “presetting” all four decades of counter in parallel. Th is affects register loading; if LOAD REGISTER is ac tivated when the RESET input is low, the register will also be set to zero. The STORE , RESET and UP/DOWN pins are provided with pullup resistors of approxi- mately 75k. BCD I/O Pins The BCD I/O port provides a means of transferring data to and from the device. The ICM7217 versions can multiplex data into the counter or register via thumbwheel switches, depending on inputs to the LOAD COUNTER or LOAD REGISTER pins; (see below). When functioning as outputs, the BCD I/O pins will drive one standard TTL load. Common anode versions have internal pull down resistors and common cathode versions have internal pull up resistors on the four BCD I/O lines when used as inputs. LOADing the COUNTER and REGISTER The BCD I/O pins, the LOAD COUNTER (LC), and LOAD REGISTER (LR) pins combine to provide presetting and com- pare functions. LC and LR are 3-level inputs, being self-biased at approximately 1/2VDD for normal operation. With both LC and LR open, the BCD I/O pins provide a multiplexed BCD out- put of the latch contents, scanned from MSD to LSD by the dis- play multiplex. When either the LOAD COUNTER (Pin 12) or LOAD REGISTER (Pin 11) is taken low, the drivers are turned off and the BCD pins become high-impedance inputs. When LC is connected to V DD, the count input is inhibited and the levels at the BCD pins are multiplexed into the counter. When LR is connected to VDD, the levels at the BCD pins are multiplexed into the register without disturbing the counter. When both are connected to VDD, the count is inhibited and both register and counter will be loaded. The LOAD COUNTER and LOAD REGISTER inputs are edge- triggered, and pulsing them hi gh for 500ns at room tempera- ture will initiate a full sequence of data entry cycle operations (see Figure 3). When the circuit recognizes that either or both of the LC or LR pins input is high, the multiplex oscillator and counter are reset (to D4). The internal oscillator is then discon- nected from the SCAN pin and the preset circuitry is enabled. The oscillator starts and runs with a frequency determined by its internal capacitor, (which may vary from chip to chip). When the chip finishes a full 4-digit multiplex cycle (loading each digit from D4 to D3 to D2 to D1 in turn), it again samples the LOAD REGISTER and LOAD COUNTER i nputs. If either or both is still high, it repeats the load cycle, if both are floating or low, the oscillator is reconnected to the SCAN pin and the chip returns to normal operation. Tota l load time is digit “on” time multiplied by 4. lf the Digit ou tputs are used to strobe the BCD data into the BCD I/O inputs, the input must be synchronized to the appropriate digit (Figure 3). Input data must be valid at the trailing edge of the digit output. When LR is connected to GROUND, the oscillator is inhibited, the BCD I/O pins go to the high impedance state, and the seg- ment and digit drivers are turned off. This allows the display to be used for other purposes and minimizes power consumption. In this display off condition, the circuit will continue to count, and the CARRY/BORROW, EQUAL , ZERO , UP/DOWN , RESET and STORE functions operate as normal. When LC is connected to ground, the BCD I/O pins are forced to the high impedance state without disturbing the counter or register. See “Control Input Definitions” (Table 2) for a list of the pins that function as three-state self-bia sed inputs and their respective operations. Note that the ICM7217 and ICM7217B have been designed to drive common anode displays. The BCD inputs are high true, as are the BCD outputs. INPUT OUTPUT INPUT OUTPUT High High High Disconnected Low Disconnected Low High FIGURE 11A. CMOS INVERTER FIGURE 11B. CMOS INVERTER INPUT B INPUT A OUTPUT INPUT B INPUT A OUTPUT High High Low High High Disconnected INPUT CD4069 1N4148 OUTPUT INPUT CD4069 OUTPUT 1N4148 INPUT A CD74HC03 OUTPUT INPUT B INPUT A CD4502B OUTPUT INPUT B
device. See Figure 14 and Figure 17. mon anode and common cathode) ar e TRUE BCD coded; i.e. 1.6ms typical (5ms maximum) after LC or LR are released. transitioning from 5 to 6 or 6 to 5. input is shown on Figure 15. FIGURE 14. LCD DISPLAY INTERFACE (WITH THUMBWHEEL SWITCHES)
28 SEGMENTS
FN3167 Rev 3.00 Page 13 of 19 July 2001
Applications
ICM7217 has three inputs with 3-level logic states; High, Low and Disconnected. These inputs are: LOAD REGISTER/OFF , LOAD COUNTER/I/O OFF and DISPLAY CONT. The circuits illustrated on Figure 11 can be used to drive these inputs in different applications. Fixed Decimal Point In the common anode versions, a fixed decimal point may be acti- vated by connecting the DP segment lead from the appropriate digit (with separate digit displays) through a 39 series resistor to Ground. With common cathode devices, the DP segment lead should be connected through a 75 series resistor to VDD. To force the device to display leading zeroes after a fixed deci- mal point, use a bipolar transistor and base resistor in a config- uration like that shown in Figure 12 with the resistor connected to the digit output driving the DP for left hand DP displays, and to the next least significant digit output for right hand DP dis- play. Driving Larger Displays For displays requiring more current than the ICM7217 can pro- vide, the circuits of Figure 13 can be used. LCD Display Interface The low-power operation of the ICM7217 makes an LCD inter- face desirable. The Intersil ICM7211 4-digit, BCD-to-LCD dis- play driver easily interfaces to the ICM7217 as shown in Figure 14. Total system power consumption is less than 5mW. System timing margins can be improved by using capacitance to ground to slow down the BCD lines. The 10k - 20k resistors on the switch BCD lines serve to isolate the switches during BCD output. Unit Counter with BCD Output The simplest application of the ICM7217 is a 4-digit unit counter (Figure 18). All that is required is an ICM7217, a power supply and a 4 digit display. Add a momentary switch for reset, an SPDT center-off switch to blank the display or view leading zeroes, and one more SPDT switch for up/ down control. Using an ICM7217A with a common-cathode calculator-type display results in the least expensive digital counter/display system available. Inexpensive Frequency Counter/ Tachometer This circuit uses the low power ICM7555 (CMOS 555) to gen- erate the gating, STORE and RESET signals as shown in Fig- ure 19. To provide the gating signal, the timer is con- figured as an a stable multivibrator, using R A, R B and C to provide an output that is positive for approximately one second and nega- tive for approximately 300 s - 500 s. The positive waveform time is given by t WP = 0.693 (R A + R B)C while the negative waveform is given by two = 0.693 R BC. The system is cali- brated by using a 5M potentiometer for RA as a “coarse” con- trol and a 1k potentiometer for R B as a “fine” control. CD40106Bs are used as a monostable multivibrator and reset time delay. Tape Recorder Position Indicator/controller The circuit in Figure 20 shows an application which uses the up/down counting feature of the ICM7217 to keep track of tape position. This circuit is representative of the many applications of up/down counting in monitoring dimensional position. In the tape recorder applicat ion, the LOAD REGISTER, EQUAL and ZERO outputs are used to control the recorder. To make the recorder stop at a particular point on the tape, the register can be set with the stop point and the EQUAL output used to stop the recorder either on fast forward, play or rewind. To make the recorder stop before the tape comes free of the reel on rewind, a leader should be used. Resetting the counter at the starting point of the tape, a few feet from the end of the leader, allows the ZERO output to be used to stop the recorder on rewind, leaving the leader on the reel. The 1M resistor and 0.0047 F capacitor on the COUNT INPUT provide a time constant of about 5ms to debounce the reel switch. The Schmitt trigger on the COUNT INPUT of the ICM7217 squares up the signal before applying it to the counter. This technique may be used to debounce switch-closure inputs in other applications. Precision Elapsed Time/Countdown Timer The circuit in Figure 21 uses an ICM7213 precision one minute/one second timebase generator using a 4.1943MHz crystal for generating pulses counted by an ICM7217B. The thumbwheel switches allow a starting time to be entered into the counter for a preset-countdo wn type timer, and allow the register to be set for compare functions. For instance, to make a 24-hour clock with BCD output the register can be preset with 2400 and the EQUAL output used to reset the counter. Note the 10K resistor connected between the LOAD COUNTER terminal and Ground. This resistor pulls the LOAD COUNTER input low when not loading, thereby inhibiting the BCD output drivers. This resist or should be eliminated and SW4 replaced with an SPDT center-off switch if the BCD outputs are to be used. This technique may be used on any 3-level input. The 100k pullup resistor on the count input is used to ensure proper logic voltage swing from the ICM7213. For a less expensive (and less accurate) timebase, an ICM7555 timer may be used in a configuration like that shown in Figure 19 to generate a 1Hz reference. 8-Digit Up/Down Counter This circuit (Figure 22) shows how to cascade counters and retain correct leading zero blanking. The NAND gate detects whether a digit is active since one of the two segments a or b is active on any unblanked number. The flip flop is clocked by the least significant digit of the high order counter, and if this digit is not blanked, the Q output of the flip flop goes high and turns on the NPN transistor, thereby inhibiting leading zero blanking on the low order counter. It is possible to use separate thumbwheel switches for presetting, but since the devices load data with the oscillator
DD, and a 0.1s gating with Pin 11 open. and multiply the rotational frequency by 600. conversion, an automatic fare subtraction occurs in the result. TABLE 2. CONTROL INPUT DEFINITIONS ICM7217
10 V DD (or floating)
14 V DD (or floating)
12 Unconnected
11 Unconnected
20 Common Cathode
FIGURE 17. THUMBWHEEL SWITCH/DIODE CONNECTIONS FIGURE 18. UNIT COUNTER
7 SEGMENTS
FIGURE 19. INEXPENSIVE FREQUENCY COUNTER FIGURE 20. TAPE RECORDER POSITION INDICATOR
7 VDD
4 DIGITS
99994 DIGIT
FIGURE 21. PRECISION TIMER
otherwise under any patent or patent rights of Intersil or its subsidiaries. © Copyright Intersil Americas LLC 2001. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. FIGURE 22. 8-DIGIT UP/DOWN COUNTER
4 DIGITS 7 SEGMENTS
FIGURE 23. PRECISION FREQUENCY COUNTER (MHz MAXIMUM) FIGURE 24. AUTO-TARE SYSTEM FOR A/D CONVERTER