ICL8052 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 16-Bit/14-Bit Binary Three-State Latched Outputs Plus Polarity and Overrange
  • Ideally Suited for Interface to UARTs and Microprocessors
  • Conversion on Demand or Continuously
  • Guaranteed Zero Reading for 0V Input
  • True Polarity at Zero Count for Precise Null Detection
  • Single Reference Voltage for True Ratiometric Operation
  • Onboard Clock and Reference
  • Auto-Zero, Auto-Polarity
  • Accuracy Guaranteed to 1 Count
  • All Outputs TTL Compatible
  • ±4V Analog Input Range
  • Status Signal Available for External Sync, A/Z in Preamp, Etc.

Description

The ICL7104, combined with the ICL8052 or ICL8068, forms a member of Intersil’ high performance A/D converter family. The ICL7104-16, performs the analog switching and digital function for a 16-bit binary A/D converter, with full three-state output, UART handshake capability, and other outputs for easy interfacing. The ICL7014-14 is a 14-bit version. The analog section, as with all Intersil’ integrating converters, provides fully precise Auto-Zero, Auto-Polarity (including±0 null indication), single reference operation, very high input impedance, true input integration over a constant period for maximum EMI rejection, fully rationmetric operation, over-range indication, and a medium quality built-in reference. The chip pair also offers optional input buffer gain for high sensitivity applications, a built-in clock oscillator, and output signals for providing an external Auto-Zero capability in preconditioning circuitry, synchronizing external multiplexers, etc.

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. ICL8052CPD 0 to 70 14 Ld PDIP E14.3 lCL8052CDD 0 to 70 14 Ld CERDIP F14.3 lCL8052ACPD 0 to 70 14 Ld PDIP E14.3 ICL8052ACDD 0 to 70 14 Ld CERDIP F14.3 ICL8068CDD 0 to 70 14 Ld CERDIP F14.3 ICL8068ACDD 0 to 70 14 Ld CERDIP F14.3 lCL8068ACJD 0 to 70 14 Ld CERDIP F14.3 ICL7104-14CPL 0 to 70 40 Ld PDIP E40.6 lCL7104-16CPL 0 to 70 40 Ld PDIP E40.6 August 1997 ICL8052/ICL7104, ICL8068/ICL7104 14-Bit/16-Bit, Microprocessor- Compatible, 2-Chip, A/D Converter File Number 3091.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

FIGURE 1. ICL8052A (8068A)/ICL7104 16-BIT/14-BIT A/D CONVERTER FUNCTIONAL DIAGRAM

24 HBEN

23 MBEN

22 LBEN

30 CE/LD

PIN NO. SYMBOL OPTION DESCRIPTION 1 V++ Positive Supply Voltage: Nominally +15V. 2 GND Digital Ground: 0V, ground return. 3 STTS Status Output: HI during integrate and deintegrate until data is latched. LO when analog section is in auto-zero configuration. 4 POL Polarity: Three-state output. HI for positive input. 5 OR Over Range: Three-state output.

6 BIT 16

-16 -14 Most Significant Bit (MSB).

7 BIT 15

-16 -14 DATA Bits: Three-state outputs. See Table 3 for format of ENABLES and bytes. HIGH = true.

8 BIT 14

-16 -14

9 BIT 13

-16 -14

10 BIT 12

-16 -14

11 BIT 11

-16 -14

12 BIT 10

-16 -14

13 BIT 9

-16 -14

14 BIT 8

15 BIT 7

16 BIT 6

17 BIT 5

18 BIT 4

19 BIT 3

20 BIT 2

21 BIT 1 Least Significant Bit (LSB). LBEN LO W BYTE ENABLE: If not in handshake mode (see pin 27) when LO (withCE/LD, pin 30) activates low-order byte outputs, BITS 1-8. When in handshake mode (see pin 27), serves as a low byte flag output. See Figures 11, 12, 13. MBEN -16 MID BYTE ENABLE: Activates Bits 9-16, seeLBEN (pin 22) HBEN -14 HIGH BYTE ENABLE: Activates Bits 9-14, POL, OR, seeLBEN (pin 22) 24 HBEN -16 HIGH BYTE ENABLE: Activates POL, OR, seeLBEN (pin 22). CLOCK3 -14 RC oscillator pin: Can be used as clock output. ICL8052/ICL7104, ICL8068/ICL7104

25 CLOCK 1 Clock Input: External clock or ocsillator. 26 CLOCK 2 Clock Output: Crystal or RC oscillator.

27 MODE INPUT LO: Direct output mode where

CE/LD, HBEN, MBEN and LBEN act as inputs directly controlling byte outputs. If pulsed HI causes immediate entry into handshake mode (see Figure 13). If HI, enables CE/LD,HBEN, MBEN and LBEN as outputs. Handshake mode will be entered and data output as in Figures 11 and 12 at conversion completion.

28 R/ H RUN/ HOLD: Input HI conversions continuously performed every 217(-16) or 215(-14) clock

pulses. Input LO conversion in progress completed, converter will stop in Auto-Zero 7 counts before input integrate. 29 SEN SEND ENABLE: Input controls timing of byte transmission in handshake mode. HI indicates ‘send’. CE/LD CHIP ENABLE/ LO AD: WITH MODE (PIN 27) LO, CE/LD serves as a master output enable; when HI, the bit outputs and POL, OR are disabled. With MODE HI, pin serves as aLO AD strobe (-ve going) used in handshake mode. See Figures 11 and 12. 31 V+ Positive Logic Supply Voltage: Nominally +5V. 32 AN I/P Analog Input: High Side. 33 BUF IN Buffer Input: Buffer Analog to analog chip (ICL8052 or ICL8086). 34 REFCAP2 Reference Capacitor: Negative Side. 35 AN. GND Analog Ground: Input low side and reference low side. 36 A-Z Auto-Zero node. 37 V REF Voltage Reference: Input (positive side). 38 REFCAP1 Reference Capacitor: Positive side. 39 COMP-IN Comparator Input: From 8052/8068. 40 V- Negative Supply Voltage: Nominally -15V. Pin Descriptions (Continued) PIN NO. SYMBOL OPTION DESCRIPTION ICL8052/ICL7104, ICL8068/ICL7104

Absolute Maximum Ratings Thermal Information ICL8052, ICL8068 Differential Input Voltage ICL7104 Digital Input Voltage Operating Conditions Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. For supply voltages less than±15V, the absolute maximum input voltage is equal to the supply voltage. 3. Short circuit may be to ground or either supply. Rating applies to 70oC ambient temperature. 4. Input voltages may exceed the supply voltages provided the input current is limited to±100µA. 5. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. For this reason it is recommended that the power supply to the ICL7104 be established before any inputs from sources not on that supply are applied. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Clock Input, CLK 1 I IN VIN = +5V to 0V ±2 ±7 ±30 µA Comparator I/P, COMP IN (Note 6) I IN VIN = 0V to +5V -10 ±0.001 10 µA Inputs with Pulldown, MODE I IH VIN = +5V 1 5 30 µA IIL VIN = 0V -10 ±0.01 10 µA Inputs with Pullups SEN, R/H LBEN, MBEN, HBEN, CE/LD (Note 7) IIH VIN = +5V -10 ±0.01 10 µA IIL VIN = 0V -30 -5 -1 µA Input High Voltage, All Digital Inputs V IH 2.5 2.0 - V Input Low Voltage, All Digital Inputs V IL - 1.5 1.0 V Digital Outputs Three-Stated On, LBEN, MBEN (16 Only),HBEN, CE/LD BIT n, POL, OR (Note 8) VOL IOL = 1.6mA - 0.27 0.4 V VOH IOH = -10µA - 4.5 - V VOH IOH = -240µA 2.4 3.5 - V Digital Outputs Three-Stated Off Bit n, POL, OR IOL 0 ≤ VOUT ≤ V+ -10 ±0.001 +10 µA Non Three-State Digital Output STTS V OL IOL = 3.2mA - 0.3 0.4 V VOH IOH = -400µA 2.4 3.3 - V Clock 2 V OL IOL = 320µA - 0.5 - V VOH IOH = -320µA - 4.5 - V Clock 3 (-14 Only) V OL IOL = 1.6mA - 0.27 0.4 V VOH IOH = -320µA 2.4 3.5 - V ICL8052/ICL7104, ICL8068/ICL7104

Switch 1 r DS(ON) - 25k - Ω Switches 2, 3 r DS(ON) - 4k 20k Ω Switches 4, 5, 6, 7, 8, 9 r DS(ON) - 2k 10k Ω Switch Leakage I D(OFF) -1 5- p A Clock Frequency (Note 9) f CLOCK DC 200 400 kHz Supply Currents +5V Supply Current All outputs high impedance I+ Frequency = 200kHz - 200 600 µA +5V Supply Current I++ Frequency = 200kHz - 0.3 1.0 mA -5V Supply Current I- Frequency = 200kHz - 25 200 µA Supply Voltage Range Logic Supply V+ Note 10 4 - 11 V Positive Supply V++ 10 - 16 V Negative Supply V- -16 - -10 V NOTES: 6. This specification applies when not in Auto-Zero phase. 7. Apply only when these pins are inputs, i.e., the mode pin is low, and the 7104 is not in handshake mode. 8. Apply only when these pins are outputs, i.e., the mode pin is high, or the 7104 is in handshake mode. 9. Clock circuit shown in Figures 14 and 15. 10. V+ must not be more positive than V++. PARAMETER SYMBOL TEST CONDITIONS ICL8068 ICL8068A UNITSMIN TYP MAX MIN TYP MAX EACH OPERATIONAL AMPLIFIER Input Offset Voltage V OS VCM = 0V - 20 65 - 20 65 mV Input Current (Either Input) (Note 11) IIN VCM = 0V - 175 250 - 80 150 pA Common-Mode Rejection Ratio CMRR V CM =±10V 70 90 - 70 90 - dB Non-Linear Component of Common- Mode Rejection Ratio (Note 12) VCM =±2V - 110 - - 110 - dB Large Signal Voltage Gain A V R L = 50kΩ 20,000 - - 20,000 - - V/V Slew Rate SR - 6 - - 6 - V/ µs Unity Gain Bandwidth GBW - 2 - - 2 - MHz Output Short-Circuit Current I SC -5 --5 - m A COMPARATOR AMPLIFIER Small-Signal Voltage Gain A VOL R L = 30kΩ - 4000 - - - - V/V Positive Output Voltage Swing +V O 12 13 - 12 13 - V Negative Output Voltage Swing -V O -2.0 -2.6 - -2.0 -2.6 - V VOLTAGE REFERENCE Output Voltage V Output Resistance R O -5 --5 - Ω PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ICL8052/ICL7104, ICL8068/ICL7104

Temperature Coefficient TC - 50 - - 40 - ppm/ oC Supply Voltage Range V SUPPL Y ±10 - ±16 ±10 - ±16 V Supply Current Total I SUPPL Y - - 14 - 8 14 mA PARAMETER SYMBOL TEST CONDITIONS ICL8052 ICL8052A UNITSMIN TYP MAX MIN TYP MAX EACH OPERATIONAL AMPLIFIER Input Offset Voltage V OS VCM = 0V - 20 75 - 20 75 mV Input Current (Either Input) (Note 11) IIN VCM = 0V - 5 50 - 2 10 pA Common-Mode Rejection Ratio CMRR V CM =±10V 70 90 - 70 90 - dB Non-Linear Component of Common- Mode Rejection Ratio (Note 12) VCM =±2V - 110 - - 110 - dB Large Signal Voltage Gain A V R L = 50kΩ 20,000 - - 20,000 - - V/V Slew Rate SR - 6 - - 6 - V/ µs Unity Gain Bandwidth GBW - 1 - - 1 - MHz Output Short-Circuit Current I SC -2 0 - -2 0 - m A COMPARATOR AMPLIFIER Small-Signal Voltage Gain A VOL R L = 30kΩ - 4000 - - - - V/V Positive Output Voltage Swing +V O 12 13 - 12 13 - V Negative Output Voltage Swing -V O -2.0 -2.6 - -2.0 -2.6 - V VOLTAGE REFERENCE Output Voltage V Output Resistance R O -5 --5 - Ω Temperature Coefficient TC - 50 - - 40 - ppm/ oC Supply Voltage Range V SUPPL Y ±10 - ±16 ±10 - ±16 V Supply Current Total I SUPPL Y - 6 12 - 6 12 mA NOTES: 11. The input bias currents are junction leakage currents which approximately double for every 10oC increase in the junction temperature, TJ. Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD . TJ = TA + RθJAPD where R θJA is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise. 12. This is the only component that causes error in dual-slope converter. PARAMETER SYMBOL TEST CONDITIONS ICL8068 ICL8068A UNITSMIN TYP MAX MIN TYP MAX ICL8052/ICL7104, ICL8068/ICL7104

System Electrical Specifications: ICL8068/ICL7104V++ = +15V, V+ = +5V, V- = -15V, fCLOCK = 200kHz (Note 16) PARAMETER TEST CONDITIONS ICL8068A/ICL7104-14 ICL8068A/ICL7104-16 UNITSMIN TYP MAX MIN TYP MAX Zero Input Reading V IN = 0V, VREF = 2V -00000 ±00000 +00000 -00000 ±00000 +00000 Counts Ratiometric Error (Note 13) V IN = VREF = 2V -1 0 1 -1 0 1 LSB Linearity Over± Full Scale (Error of Reading from Best Straight Line) -4V ≤ VIN ≤ +4V - 0.5 1 - 0.5 1 LSB Differential Linearity (Difference between Worst Case Step of Adjacent Counts and Ideal Step) -4V ≤ V Rollover Error (Difference in Reading for Equal Positive & Negative Voltage Near Full Scale) IN = +VIN ≅ 4V - 0.5 1 - 0.5 1 LSB Noise (P-P Value Not Exceeded 95% of Time) VIN = 0V, Full Scale = 4V -2--2- µV Leakage Current at Input (Note 14) VIN = 0V - 100 165 - 100 165 pA Zero Reading Drift V IN = 0V, 0oC to 70oC Scale Factor Temperature Coefficient (Note 15) VIN = 4V, 0oC to 50oC ext. ref. 0ppm/oC - 2 5 - 2 5 ppm/ oC System Electrical Specifications: ICL8052/ICL7104V++ = +15V, V+ = +5V, V- = -15V, fCLOCK = 200kHz (Note 16) PARAMETER TEST CONDITIONS ICL8052A/ICL7104-14 ICL8052A/ICL7104-16 UNITSMIN TYP MAX MIN TYP MAX Zero Input Reading V IN = 0V, VREF = 2V -00000 ±00000 +00000 -00000 ±00000 +00000 Counts Ratiometric Error (Note 15) V IN = VREF = 2V -1 0 1 -1 0 1 LSB Linearity Over± Full Scale (Error of Reading from Best Straight Line) -4V ≤ VIN ≤ +4V - 0.5 1 - 0.5 1 LSB Differential Linearity (Difference between Worst Case Step of Adjacent Counts and Ideal Step) -4V ≤ V Rollover Error (Difference in Reading for Equal Positive and Negative Voltage Near Full Scale) IN = +VIN ≈ 4V - 0.5 1 - 0.5 1 LSB Noise (Peak-to-Peak Value Not Exceeded 95% of Time) VIN = 0V, Full Scale = 4V -3 0- -3 0- µV Leakage Current at Input (Note 14) VIN = 0V - 20 30 - 20 30 pA Zero Reading Drift V IN = 0V, 0oC to 70oC Scale Factor Temperature Coefficient VIN = 4V, 0oC to 50oC ext. ref. 0ppm/oC - 2 - - 2 - ppm/ oC NOTES: 13. Tested with low dielectric absorption integrating capacitor. 14. The input bias currents are junction leakage currents which approximately double for every 10 oC increase in the junction temperature, TJ. Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal oper- ation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD . TJ = TA + RθJAPD where RθJA is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise. 15. The temperature range can be extended to 70oC and beyond if the Auto-Zero and Reference capacitors are increased to absorb the high temperature leakage of the 8068. See note 14 above. 16. System Electrical Specifications are not tested; for reference only. ICL8052/ICL7104, ICL8068/ICL7104

TABLE 1. DIRECT MODE TIMING REQUIREMENTS (Note: Not tested in production) TABLE 2. HANDSHAKE TIMING REQUIREMENTS (Note: Not tested in production)

discussion, see Application Note AN030. level conditions, will give better performance. TABLE 3. THREE-STATE BYTE FORMATS AND ENABLE PINS TABLE 4. TYPICAL COMPONENT VALUES (V++ = +15V, V+ = 5V, V- = 5V, V- = -15V, fCLOCK = 200kHz) FIGURE 7. ADDING BUFFER GAIN TO ICL8068

use the capacitor with the input tied to the reference. and any deviation is probably due to dielectric absorption. also be used in less critical applications. the noise of the system, a large capacitor giving less noise. stray capacitance to ground from its nodes is negligible. capacitor should be substantially larger than the auto-zero capacitor. not required for the first few seconds of recovery. the ICL7104 at 16 bits is one part in 65536, or 15.26ppm. FIGURE 8. CONVERSION TIMING

the Block Diagram Figure 9 (16-bit version shown). pullup resistors added for maximum noise immunity. shake Mode” for further details). rupts, or for monitoring the status of the converter. TABLE 5. THREE-STATE BYTE FORMATS AND ENABLE PINS FIGURE 9. DIGITAL SECTION

7104-14 clock periods, regardless of the resulting value. immediately terminate Deintegrate and jump to Auto-Zero. Hold. See Figure 10 for details. CHIP ENABLE terminals as inputs. cycle by monitoring the STATUS output will prevent this. potential bus conflict described under “Initial Clear Circuitry”. number of lines to the central controlling processor. FIGURE 10. RUN/HOLD OPERATION

7 COUNTS

silicon rectifier is adequate. ground lines is shown in Figure 16. FIGURE 16. GROUNDING SEQUENCE

8068 PIN 2

ICL7104 with ICL8052/8068 Integrating A/D Converter Equations

  • Oscillator CRYSTAL or RC (RC on -14 Part Only) fOSC (Typ) 200kHz fOSC = 0.45/RC (ICL7104-14 Only) C OSC > 50pF and ROSC > 50K
  • Oscillator Period tOSC = 1/fOSC
  • Integration Clock Frequency fCLOCK = fOSC
  • Integration Period tINT = 8192 x tOSC (7104-14) tINT = 32768 x tOSC (7104-16)
  • 60/50Hz Rejection Criterion tINT/t60Hz or tINT/t50Hz = Integer
  • Optimum Integration Current IINT = 20µA
  • Full Scale Analog Input Voltage VINFS (Typ) = 200mV to 2V = 2VREF
  • Integrate Resistor
  • Integrate Capacitor
  • Integrator Output Voltage VINT (Typ) = 9V
  • Output Count
  • Output Type: Binary Amplitude with Polarity and Overrange Bits.
  • Power Supply:±15V, +5V V++ = +15V V- = -15V V+ = +5V V REF ≅ 1.75V If VREF not used, float output pin.
  • Auto Zero Capacitor Values 0.01µF < CAZ < 1µF
  • Reference Capacitor Value C REF = (Buffer Gain) x CAZ R INT BufferGain() V INFS× IINT C INT tINT() IINT() V INT V INT tINT() IINT() C INT Count 8192 V IN V REF Count 32768 V IN V REF FIGURE 17. AUTOZERO (COUNT) 24,576 - 8,193 98,304 - 32,769 INTEGRATE (FIXED COUNT) 8192 32768 DEINTEGRATE (COUNT) 0 - 16383 0 - 65535 ICL7104 - 14 ICL7104 - 16 CONVERSION TIME (IN CONTINUOUS MODE): 32,768† tOSC (7104 - 14) 131,072† tOSC (7104 - 16) ICL8052/ICL7104, ICL8068/ICL7104 All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com