LCDA05_06 SEMTECH | Alldatasheet
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1 www.semtech.com PROTECTION PRODUCTS LCDA05 through LCDA24 Low Capacitance TVS Diode Array For High-Speed Data Interfaces Transient protection for high-speed data lines to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (lightning) (8/20µs)* Protects two I/O lines Low capacitance for high-speed data lines Working voltages: 5V, 12V, 15V and 24V Low leakage current Low operating and clamping voltages Solid-state silicon avalanche technology Description Features Circuit Diagram (Each Line Pair) Schematic & PIN Configuration Revision 08/15/2006
Applications
Mechanical Characteristics SO-8 (Top View) The LCDA series of TVS arrays are designed to protect sensitive electronics from damage or latch-up due to ESD and other voltage-induced transient events. Each device will protect two high-speed lines. They are available with operating voltages of 5V, 12V, 15V and 24V. They are bidirectional devices and may be used on lines where the signal polarities are above and below ground. TVS diodes are solid-state devices designed specifically for transient suppression. They offer desirable charac- teristics for board level protection including fast re- sponse time, low operating and clamping voltage and no device degradation. The LCDA series devices feature low capacitance compensation diodes in series with standard TVS diodes to provide an integrated, low capacitance solution for use on high-speed interfaces. The LCDA series devices may be used to meet the immunity requirements of IEC 61000-4-2, level 4. JEDEC SO-8 package Molding compound flammability rating: UL 94V-0 Marking : Part Number, Date Code Packaging : Tape and Reel per EIA 481 High-Speed Data Lines Microprocessor Based Equipment Universal Serial Bus (USB) Port Protection Notebooks, Desktops, and Servers Instrumentation LAN/WAN Equipment Peripherals 8Pin 1 and 2 Pin 7 and 8 *See Electrical Characteristics Tables for Ipp
2 2005 Semtech Corp. www.semtech.com PROTECTION PRODUCTSPROTECTION PRODUCTS LCDA05 through LCDA24 Absolute Maximum Rating
Electrical Characteristics
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3 2005 Semtech Corp. www.semtech.com PROTECTION PRODUCTS LCDA05 through LCDA24 51ADCL retemaraPl obmySs noitidnoCm uminiMl acipyTm umixaMs tinU egatloVffO-dnatSesreveRV MWR 51V egatloVnwodkaerBesreveRV RB It Am1=7 .61V tnerruCegakaeLesreveRI R V MWR C°52=T,V51=1 A µ egatloVgnipmalCV C I PP t,A1= p sµ02/8=4 2V egatloVgnipmalCV C I PP t,A5= p sµ02/8=0 3V tnerruCesluPkaePmumixaMI PP tp sµ02/8=0 1A ecnaticapaCnoitcnuJC j dnasniPO/IneewteB dnuorG VR zHM1=f,V0= 5F p 42ADCL retemaraPl obmySs noitidnoCm uminiMl acipyTm umixaMs tinU egatloVffO-dnatSesreveRV MWR 42V egatloVnwodkaerBesreveRV RB It Am1=7 .62V tnerruCegakaeLesreveRI R V MWR C°52=T,V42=1 A µ egatloVgnipmalCV C I PP t,A1= p sµ02/8=3 4V egatloVgnipmalCV C I PP t,A5= p sµ02/8=5 5V tnerruCesluPkaePmumixaMI PP tp sµ02/8=5 A ecnaticapaCnoitcnuJC j dnasniPO/IneewteB dnuorG VR zHM1=f,V0= 5F p Electrical Characteristics (continued)
4 2005 Semtech Corp. www.semtech.com PROTECTION PRODUCTSPROTECTION PRODUCTS LCDA05 through LCDA24 Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve 100 110 0 5 10 15 20 25 30 Time (µs) Percent of IPP e td = IPP/2 Waveform Parameters: tr = 8µs td = 20µs Pulse Waveform ESD Pulse Waveform (Per IEC 61000-4-2) 0.01 0.1 0.1 1 10 100 1000 Pulse Duration - tp (µs) Peak Pulse Power - Ppk (kW) 100 110 0 25 50 75 100 125 150 Ambient Temperature - T A (oC) % of Rated Power or IPP leveLt sriF kaeP tnerruC )A( kaeP tnerruC sn03ta )A( kaeP tnerruC sn06ta )A( tseT egatloV tcatnoC( )egrahcsiD )Vk( tseT egatloV riA( )egrahcsiD )Vk( 15 .74 8 2 2 25 18 4 4 4 35 .222 16 6 8 40 36 18 8 5 1 ESD Discharge Parameters Per IEC 61000-4-2
5 2005 Semtech Corp. www.semtech.com PROTECTION PRODUCTS LCDA05 through LCDA24 Applications Information Device Connection for Protection of Two High-Speed Data Lines The LCDAxx is designed to protect up to two high-speed data lines. The LCDAxx utilizes a low capacitance compensation diode in series with, but in opposite polarity to a TVS diode in each line. The resulting capacitance is less than 5pF per line. Each line will only suppress transient events in one polarity. There- fore, to achieve protection in both positive and nega- tive polarity, a second TVS/rectifier pair is connected in anti-parallel to the first. Pins 1, 2, 7, and 8 are used to protect one data line. Pins 3, 4, 5, and 6 are used to protect the second data line. The device is connected as follows: z Pins 1 and 2 are tied together and pins 7 and 8 are tied together providing the protection circuit for one I/O line. Pins 3 and 4 are tied together and pins 5 and 6 are tied together providing the protec- tion circuit for the second I/O line. Since the device is electrically symmetrical, either side of the connected pairs may be used to protect the lines. The other side of the pair is used to make the ground connection. The ground connections should be made directly to the ground plane for best results. The path length is kept as short as pos- sible to reduce the effects of parasitic inductance in the board traces. Circuit Board Layout Recommendations for Suppres- sion of ESD. Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: z Place the TVS near the input terminals or connec- tors to restrict transient coupling. z Minimize the path length between the TVS and the protected line. z Minimize all conductive loops including power and ground loops. z The ESD transient return path to ground should be kept as short as possible. z Never run critical signals near board edges. z Use ground planes whenever possible. Line 1 In/Out Line 1 Ground Line 2 In/Out Line 2 Ground From Connector To Protected Device 8Line 1 In/Out Ground Line 2 In/Out From Connector To Protected Device Connection Options I/O Line Protection LCDA Connection Diagram I/O 1 I/O 2 I/O 1 I/O 2
6 2005 Semtech Corp. www.semtech.com PROTECTION PRODUCTSPROTECTION PRODUCTS LCDA05 through LCDA24 Matte Tin Lead Finish Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads is small com- pared to the solder paste volume that is placed on the land pattern of the PCB, the reflow profile will be determined by the requirements of the solder paste. Therefore, these devices are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other lead-free compositions, matte tin does not have any added alloys that can cause degradation of the solder joint. Applications Information (continued)
7 2005 Semtech Corp. www.semtech.com PROTECTION PRODUCTS LCDA05 through LCDA24 Land Pattern - SO-8 Outline Drawing - SO-8 bxN 2X N/2 TIPS SEATING aaa C E/22X N A D bbb C A-B D ccc C e/2 SEE DETAIL A SIDE VIEW A B C De DETAIL A c L (L1) 01 0.25 GAGE PLANE h h H PLANE 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. -B- CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS AND TO BE DETERMINED AT DATUM PLANE NOTES: 2. -A- -H- REFERENCE JEDEC STD MS-012, VARIATION AA.4. .050 BSC .236 BSC .010 .150 .189 .154 .193 .012 - 0.25
1.27 BSC
6.00 BSC
3.90 4.90 .157 .197 3.80 4.80 .020 0.31 4.00 5.00 0.51 (.041) .004 .008 .028 .016 .007 .049 .004 .053 8° 0° 0.20 0.10 - 8° 0.40 0.17 1.25 0.10 .041 .010 .069 .065 .010 1.35 (1.04) 0.72 1.04 0.25 - 1.75 1.65 0.25 N bbb aaa ccc A b D E L h e c DIM MIN MILLIMETERS NOM DIMENSIONS INCHES MIN MAX MAX NOM E (.205) (5.20) ZG Y P (C) 3.00.118 1.27.050 0.60.024 2.20.087 7.40.291 X INCHES DIMENSIONS Z P Y X DIM C G MILLIMETERS THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. NOTES: REFERENCE IPC-SM-782A, RLP NO. 300A.2.
8 2005 Semtech Corp. www.semtech.com PROTECTION PRODUCTSPROTECTION PRODUCTS LCDA05 through LCDA24 Contact Information Semtech Corporation Protection Products Division
200 Flynn Road, Camarillo, CA 93012
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