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Technical content

Features

Flash ROM

  • 128K × 8bit (Table data reside in the same space.) RAM
  • 4240 × 8bit
  • For data 4096 × 8bit
  • For display 72 × 16bit LCD Display
  • 64 segment × 16 common/72 segment × 8 common (1/4 bias) CMOS IC FROM 128K byte, RAM 4096K byte on-chip 16-bit 1-chip Microcontroller * This product is licensed from Silicon Storage Technology, Inc. (USA).

No.A1228-2/25 Instruction Execution Time (min)

  • 31.0μs : 32.768kHz crystal used
  • 15.6μs (typ) : Low speed RC oscillation (typ: 64kHz)
  • 0.25μs : 4.0MHz ceramic filter oscillation
  • 1.00μs (typ) : High speed RC oscillation (typ: 1MHz) Power Supply Voltage
  • 2.3V to 5.5V (Ta =-20 to 75°C) : 32.768kHz crystal used
  • 2.3V to 5.5V (Ta =0 to 60°C) : Low speed RC oscillation (typ: 64kHz)
  • 2.4V to 5.5V (Ta =-20 to 75°C) : 4.0MHz ceramic filter oscillation
  • 2.3V to 5.5V (Ta =0 to 60°C) : High-speed RC oscillation (typ: 1MHz)
  • 2.4V to 5.5V (Ta =-20 to 75°C) : When LCD ON Consumption Current (3.0V):
  • 10.5μA (typ) (Ta=25°C, crystal oscillation 32.768kHz, 1/1 dividing frequency, HALT, LCD: ON)
  • 300μA (typ) (Ta=25°C, crystal oscillation 32.768kHz, CF 4MHz, 1/2 dividing frequency, HALT, LCD: ON)
  • 2200μA (typ) (Ta=25°C, crystal oscillation 32.768kHz, CF 4MHz, 1/2 dividing frequency, continuous operation, LCD: ON) Ports
  • Normal withstand voltage I/O ports 20 (P0n, P1n, P20 to P23)
  • LCD (COM8/SEG0 to COM15/SEG7 pins are multiplexed with COMMON and SEGMENT) LCD drive bias power supply port 4 (V LCD1 to VLCD4) Step-up capacitor port 2 (CUP00, CUP01) 16 common mode Segment output 64 (SEG8 to SEG71) Common output 16 (COM0 to COM15) 8 common mode Segment output 72 (SEG0 to SEG71) Common output 8 (COM0 to COM7)
  • Oscillation pins 4 (XT1, XT2, CF1, CF2)
  • Reset pin 1 (RESB)
  • Test pin 1 (TST)
  • LCD port power pins 2 (LCDV SS0, LCDVSS1)
  • Power pins 2 (V DD, V SS) LCD
  • LCD power supply : Capacitor step-up type
  • Number of dots : 1024 (64 segments × 16 commons) / 576 (72 segments × 8 commons)
  • Contrast : Adjustable in 16 steps
  • LCD frame frequency : Selectable from 4 types

No.A1228-3/25 Timers

  • Timer 0: 16-bit timer that supports PWM/toggle outputs 1) With 5-bit prescaler 2) 8-bit PWM × 2/8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
  • Timer 1: 16-bit timer with capture registers 1) With 5-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
  • Timer 3: 16-bit timer that supports PWM/toggle outputs 1) With 8-bit prescaler 2) 8-bit timer × 2ch/8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
  • Timer 4: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0
  • Timer 5: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0
  • Base timer 1) Clock may be selected from OSC0 (32.768kHz crystal oscillator) and frequency-divided output of system clock. 2) Interrupts can be generated in 7 timing schemes. Watchdog Timer 1) Driven by the base timer + internal watchdog timer dedicated counter. 2) Interrupt or reset mode selectable SIO0: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) It is possible to communicate with 8 bits or less. (1 to 8 bits specifiable in 1-bit units) 3) Built-in 8-bit baudrate generator (transfer clock cycle 4 tCYC to 512 tCYC) 4) Automatic continuous data transmission (9 to 32768 bits specifiable in 1-bit units) 5) Interval function (interval time: 0 to 64 SIOCLKs specifiable in 1 SIOCLK units) 6) Wakeup function UART2: Asynchronous SIO 1) Full duplex transmission 2) Start bit 1, data bit 8 (LSB first), stop bit 1 3) Parity bit: None/even parity/odd parity 4) Transfer rate: 8 to 4096 tCYC 5) Baudrate source clock: systemclock/OSC0/OSC1 6) Wakeup function AD converter: 12bit × 4 channels 1) 12-/8-bit resolution selectable 2) Analog input: 4 channels 3) Comparator mode 4) Automatic reference voltage generation

No.A1228-4/25 Interrupts

  • 12 sources, 11 vector addresses 1) Provides three levels of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Interrupt Source 1 08000H WATCHDOGTIMER 2 08004H BASETIMER 3 08008H TIMER0 4 08018H SIO0 5 0801CH TIMER1 6 08020H UART2 7 08024H TIMER3 8 08028H TIMER4 9 0802CH TIMER5 10 08030H ADC 11 0803CH P00 to P05 SEG71 to SEG64
  • The priority level can be specified by three levels.
  • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels
  • Max- whole RAM area (Stack is set in RAM) Oscillation Circuits
  • OSC1: For system clock ceramic oscillation with external CGC, CDC or RC oscillation (external RCR1)
  • OSC0: For low-speed system clock, base timer count, for LCD display 32kHz crystal oscillation with external CGX, CDX or RC oscillation (external RCR0)
  • Internal oscillation circuit: Internal RC * Depends on control resister for each oscillator operation and stop. Initial setting - External oscillation stop, internal RC oscillation operation

No.A1228-5/25 Standby Function

  • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Released by a system reset or occurrence of an interrupt.
  • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) OSC1, internal RC and X’tal oscillators automatically stop operation. 2) There are the following methods of resetting the HOLD. (1) Setting the reset pin to the low level (2) Having an interrupt source established in the SIO0 (3) Having an interrupt source established in the UART2 (4) Having an interrupt source established in the P00 to P05 (5) Having an interrupt source established in the SEG71 to SEG64
  • X’tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except using OSC0. 1) The OSC1 and internal RC oscillators automatically stop operation. 2) The state of OSC0 oscillation established when the X'tal HOLD mode is entered is retained. 3) There are the following methods of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Having an interrupt source established in the base timer circuit (3) Having an interrupt source established in the timers 0, 1, 3, 4, 5 (4) Having an interrupt source established in the SIO0 (5) Having an interrupt source established in the UART2 (6) Having an interrupt source established in the P00 to P05 (7) Having an interrupt source established in the SEG71 to SEG64 On-chip debugger
  • Supports software debugging with the IC mounted on the target board.
  • Supports tracing, realtime monitoring, and breakpoint setting.
  • Single-wire communication Package Form
  • TQFP120(14×14): Lead-free type Development Tools
  • On-chip debugger : EOCUIF1 + LC88F83B0A
  • Programming boards : Package Dimensions unit : mm (typ) 3257A SANYO : TQFP120(14X14) 0.125 120 0.150.4 (1.2) 14.0 16.0 14.0 16.0 1.2MAX 0.1 (1.0) 0.5

No.A1228-6/25 Pad Assignment

  • Chip size (X × Y) : 3.40mm × 3.19mm
  • Pad size : 59 μm
  • Pad pitch : 80 μm
  • Chip thickness : 280 μm ± 20μm Note: Pin numbers assigned to a package differ from pad numbers assigned to a chip. Numbers in the above figure show the pad numbers of the chip.  61  60  59  58  57  56  55  54  53  52  51  50  49  48  47  46  45  44  43  42  41  40  39  38  37  36  35  34  33  32  31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  15  14  13  12  11  10  9  8  7  6  5  4  3  2  1 62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100  101  102  103  104  105  106  107  108  109  110  111  112  113  114  115  116  117  118  119  120  121  122  123  124  125  126  Y X (0, 0)

No.A1228-7/25 Pad Coordinates Table Pad No. Pin Name Coordinates Pad No. Pin Name Coordinates X μm Y μm X μm Y μm 1 P20 1567.4 -1308 48 SEG29 -192 1462.4 2 P21 1567.4 -1228 49 SEG28 -272 1462.4 3 P22 1567.4 -1147 50 SEG27 -352 1462.4 4 P23 1567.4 -1067 51 SEG26 -432 1462.4 5 SEG71 1606.99 -951.8 52 SEG25 -512 1462.4 6 SEG70 1606.99 -863.6 53 SEG24 -592 1462.4 7 SEG69 1606.99 -775.4 54 SEG23 -672 1462.4 8 SEG68 1606.99 -606.8 55 SEG22 -752 1462.4 9 SEG67 1606.99 -518.6 56 SEG21 -832 1462.4 10 SEG66 1606.99 -430.4 57 SEG20 -912 1462.4 11 SEG65 1606.99 -342.2 58 SEG19 -992 1462.4 12 SEG64 1606.99 -254 59 SEG18 -1072 1462.4 13 SEG63 1606.99 -165.8 60 SEG17 -1152 1462.4 14 SEG62 1606.99 -77.6 61 SEG16 -1232 1462.4 15 SEG61 1606.99 10.6 62 SEG15 -1567.4 1335 16 SEG60 1606.99 98.8 63 SEG14 -1567.4 1255 17 SEG59 1606.99 187 64 SEG13 -1567.4 1175 18 SEG58 1606.99 275.2 65 SEG12 -1567.4 1095 19 SEG57 1606.99 363.4 66 SEG11 -1567.4 1015 20 SEG56 1606.99 451.6 67 SEG10 -1567.4 935 21 SEG55 1567.4 573 68 SEG9 -1567.4 855 22 SEG54 1567.4 653 69 SEG8 -1567.4 775 23 SEG53 1567.4 733 70 - - - 24 SEG52 1567.4 813 71 COM15/SEG7 -1567.4 615 25 SEG51 1567.4 893 72 - - - 26 SEG50 1567.4 973 73 COM14/SEG6 -1567.4 455 27 SEG49 1567.4 1053 74 - - - 28 SEG48 1567.4 1133 75 COM13/SEG5 -1567.4 295 29 SEG47 1567.4 1213 76 - - - 30 SEG46 1567.4 1293 77 COM12/SEG4 -1567.4 135 31 LCDV SS1 1190 1462.4 78 - - - 32 SEG45 1088 1462.4 79 COM11/SEG3 -1567.4 -25 33 SEG44 1008 1462.4 80 - - - 34 SEG43 928 1462.4 81 COM10/SEG2 -1567.4 -185 35 SEG42 848 1462.4 82 - - - 36 SEG41 768 1462.4 83 COM9/SEG1 -1567.4 -345 37 SEG40 688 1462.4 84 - - - 38 SEG39 608 1462.4 85 COM8/SEG0 -1567.4 -505 39 SEG38 528 1462.4 86 COM7 -1567.4 -585 40 SEG37 448 1462.4 87 COM6 -1567.4 -665 41 SEG36 368 1462.4 88 COM5 -1567.4 -745 42 SEG35 288 1462.4 89 COM4 -1567.4 -825 43 SEG34 208 1462.4 90 COM3 -1567.4 -905 44 SEG33 128 1462.4 91 COM2 -1567.4 -985 45 SEG32 48 1462.4 92 COM1 -1567.4 -1065 46 SEG31 -32 1462.4 93 COM0 -1567.4 -1145 47 SEG30 -112 1462.4 94 LCDV SS0 -1567.4 -1240 Continued on next page.

No.A1228-8/25 Continued from preceding page. Pad No. Pin Name Coordinates Pad No. Pin Name Coordinates X μm Y μm X μm Y μm 95 CUP00 -1567.4 -1335.8 111 P00 205 -1462.4 96 CUP01 -1567.4 -1415.8 112 P01 285 -1462.4 97 V LCD4 -1295.45 -1462.4 113 P02 365 -1462.4 98 V LCD3 -1215.45 -1462.4 114 P03 445 -1462.4 99 V LCD2 -1130.8 -1462.4 115 P04 525 -1462.4 100 V LCD1 -1050.8 -1462.4 116 P05 605 -1462.4 101 TST -965 -1462.4 117 P06 685 -1462.4 102 XT2 -723 -1462.4 118 P07 765 -1462.4 103 XT1 -643 -1462.4 119 P10 845 -1462.4 104 RESB -563 -1462.4 120 P11 925 -1462.4 105 VDD -383.5 -1462.4 121 P12 1005 -1462.4 106 -272.5 -1462.4 122 P13 1085 -1462.4 107 CF1 -172 -1462.4 123 P14 1165 -1462.4 108 CF2 -92 -1462.4 124 P15 1245 -1462.4 109 VSS 3 -1462.4 125 P16 1325 -1462.4 110 108 -1462.4 126 P17 1405 -1462.4 Note:

  • Pad coordinates shown in above table are referenced at the center of the IC-chip as an origin.
  • There are two pads for each VDD and VSS, and each set of pads needs double-bonding. Pin Assignment TQFP120(14×14) “Lead-free Type” LC88F83B0A VLCD4 VLCD3 VLCD2 VLCD1 TST XT2 XT1 RESB VDD CF1 CF2 VSS P00/P0LI P01/P0LI P02/P0LI P03/P0LI P04/P0HLI P05/P0HLI P06/T0PWML P07/T0PWMH P10/SI0O P11/SI0IO P12/SI0CLK P13/T3OL P14/T3OH P15 P16/U2RX P17/U2TX SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 LCDVSS1 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG8 SEG9 COM15/SEG7 COM14/SEG6 COM13/SEG5 COM12/SEG4 COM11/SEG3 COM10/SEG2 COM9/SEG1 COM8/SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LCDVSS0 CUP00 CUP01 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56/SNO15/SGIN15 SEG57/SNO14/SGIN14 SEG58/SNO13/SGIN13 SEG59/SNO12/SGIN12 SEG60/SNO11/SGIN11 SEG61/SNO10/SGIN10 SEG62/SNO9/SGIN9 SEG63/SNO8/SGIN8 SEG64/SNO7/SGIN7/SGINT7 SEG65/SNO6/SGIN6/SGINT6 SEG66/SNO5/SGIN5/SGINT5 SEG67/SNO4/SGIN4/SGINT4 SEG68/SNO3/SGIN3/SGINT3 SEG69/SNO2/SGIN2/SGINT2 SEG70/SNO1/SGIN1/SGINT1/T3IH SEG71/SNO0/SGIN0/SGINT0/T3IL P23/AN3 P22/AN2 P21/AN1/T5O P20/AN0/T4O 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Top view

No.A1228-9/25 Pin No. Name Pin No. Name Pin No. Name Pin No. Name

1 V LCD4 31 P20/AN0/T4O 61 LCDV SS1 91

2 V LCD3 32 P21/AN1/T5O 62 SEG45 92 SEG16

3 V LCD2 33 P22/AN2 63 SEG44 93 SEG15

4 V LCD1 34 P23/AN3 64 SEG43 94 SEG14

5 TST 35 SEG71/SNO0

/SGIN0/SGINT0 /T3IL

65 SEG42 95 SEG13

/SGIN1/SGINT1 /T3IH

66 SEG41 96 SEG12

7 XT2 37 SEG69/SNO2

/SGIN2/SGINT2

67 SEG40 97 SEG11

8 XT1 38 SEG68/SNO3

/SGIN3/SGINT3

68 SEG39 98 SEG10

9 RESB 39 SEG67/SNO4

/SGIN4/SGINT4

69 SEG38 99 SEG9

10 V DD 40 SEG66/SNO5

/SGIN5/SGINT5

70 SEG37 100 SEG8

11 CF1 41 SEG65/SNO6

/SGIN6/SGINT6

71 SEG36 101 COM15/SEG7

12 CF2 42 SEG64/SNO7

/SGIN7/SGINT7

72 SEG35 102 COM14/SEG6

13 V SS 43 SEG63/SNO8

/SGIN8

73 SEG34 103 COM13/SEG5

14 P00/P0LI 44 SEG62/SNO9

/SGIN9

74 SEG33 104 COM12/SEG4

15 P01/P0LI 45 SEG61/SNO10

/SGIN10

75 SEG32 105 COM11/SEG3

16 P02/P0LI 46 SEG60/SNO11

/SGIN11

76 SEG31 106 COM10/SEG2

17 P03/P0LI 47 SEG59/SNO12

/SGIN12

77 SEG30 107 COM9/SEG1

18 P04/P0HLI 48 SEG58/SNO13

/SGIN13

78 SEG29 108 COM8/SEG0

19 P05/P0HLI 49 SEG57/SNO14

/SGIN14

79 SEG28 109 COM7

20 P06/T0PWML 50 SEG56/SNO15

/SGIN15

80 SEG27 110 COM6

21 P07/T0PWMH 51 SEG55 81 SEG26 111 COM5

22 P10/SI0O 52 SEG54 82 SEG25 112 COM4

23 P11/SI0IO 53 SEG53 83 SEG24 113 COM3

24 P12/SI0CLK 54 SEG52 84 SEG23 114 COM2

25 P13/T3OL 55 SEG51 85 SEG22 115 COM1

26 P14/T3OH 56 SEG50 86 SEG21 116 COM0

27 P15 57 SEG49 87 SEG20 117 LCDV SS0

28 P16/U2RX 58 SEG48 88 SEG19 118 CUP00

29 P17/U2TX 59 SEG47 89 SEG18 119 CUP01

No.A1228-10/25 System Block Diagram P00 to 07 P10 to 17 COM 0 to 15 RESB TST XT1 XT2 CF1 CF2 CUP00, 01 VLCD1 to 4 LCD segment driver 72 terminals Common driver 16 terminals (ADC 4 terminals) (I/O 16 terminals) On-chip debugger SEG 71 to 56 Timer 1 I/O Port Timer 0 R0 to R15 ALU RAM (4K×8bit) Base timer Interrupt control ROM (128K×8bit) PC WD timer IR System control Standby control Internal RC OSC1 CF RC OSC0 X’tal RC Clock Timer 3 PSW LCD display RAM 72×16bit UART2 SIO0 I/O Port LCD power supply Timer 4 Timer 5 P20 to 23 I/O Port SEG 0 to 71

No.A1228-11/25 Pin Description Pin Name I/O Description VDD - + power supply pin VSS - - power supply pin VLCD1 to 4 - LCD bias power port (capacitor connection port) LCDVSS0, LCDVSS1 - LCD power supply pin CUP00, 01 - Switching pin for generating LCD driving voltage Connect capacitor between both ports. OSC0 XT1 I Oscillator circuit for system clock (low speed)

  • 32.768kHz crystal oscillator and capacitor for oscillation connection
  • XT1: Resistor connection for RC oscillation (RC model) XT2 O OSC1 CF1 I Oscillator circuit for system clock (high speed)
  • Ceramic oscillator and capacitor for oscillator connection
  • CF1: Resistance connection for RC oscillator (RC model) CF2 O PORT 0 P00 to P07 I/O • 8-bit I/O port
  • I/O specifiable in 1-bit units
  • Shared pins P00 to P05 : Interrupt function P06: Timer 0 PWML output P07: Timer 0 PWMH output PORT 1 P10 to P17 I/O • 8-bit I/O port
  • I/O specifiable in 1-bit units
  • Shared pins P10: SIO0 data output P11: SIO0 data input/Bus I/O P12: SIO0 Clock I/O P13: Timer 3 PWML output P14: Timer 3 PWMH output P16: UART 2 receive P17: UART 2 send PORT 2 P20 to P23 I/O • 4-bit I/O port
  • I/O specifiable in 1-bit units P20 to P23: AD converter input ports (AN0 to AN3)
  • Shared pins P20: Timer 4 output P21: Timer 5 output COM0 to COM7 O • LCD common output port COM8/SEG0 to COM15/SEG7 O • LCD common output port/segment output port common output/segment output is switched according to the register. SEG8 to SEG55 O • LCD segment output port SEG56 to SEG71 I/O • LCD segment output port
  • SEG71 to SEG56: General purpose Nch OD output/General purpose input SEG71 to SEG56 can switch LCD output, a general-purpose Nch OD output, and a general-purpose input (every 4 bits).
  • SEG71 to SEG64: Interrupt function (every 4 bits) Selecting sampling frequency for chattering removal (every 4 bits) Level/edge selection (every 4 bits) Hi/Low level or rise/fall selection (every 1 bit)
  • SEG71 to SEG70: Timer 3 external input RESB I • Input terminal for system initialization It operates reset by the “LOW” input. with pull-up resistor TST I/O • TEST pin
  • On-chip debugger communication terminal Used with pull-down or VSS *Connect 100kΩ between this pin and VSS when on-chip debugger is used.

No.A1228-12/25 Application circuit X'tal Crystal oscillator CGX Trimmer capacitor CDX Capacitance for X’tal RCR0 Resistor for low-speed oscillation *4: RC oscillation specification CCR0 Capacitor for low-speed oscillation *4: RC oscillation specification (1) (1) 0.1 μF capacitor is recommended when using XT1/XT2 as a system clock. CF Ceramic oscillator CGC Capacitance for CF CDC Capacitance for CF RCR1 Resistor for high-speed oscillation *5: RC oscillation specification CCR1 Capacitor for high-speed oscillation *5: RC oscillation specification C1 to C5 Capacitor CDEN Electrolytic capacitor CRES Capacitance for RESB RTST Resister when on-chip debugger is used LCD panel 64×16/72×8 LC88F83B0A CUP01 CUP00 VLCD4 VLCD3 VLCD2 VLCD1 I/O VDD VSS LCDVSS0 LCDVSS1 TST *1: Crystal oscillation *2: Internal RC oscillation *3: Ceramic oscillation 2.3V to 5.5V CDEN CRES P00 P01 P02 P03 P04 P05 P06 P07 SEG8 SEG71 COM8/SEG0CF2 XT2 XT1 RCR1 RCR0 X'tal CGXCDX CGCCDC RESB CCR1 I/O P10 (SIO0-OUT) P11 (SIO0-IN) P12 (SIO0-CLK) P13 P14 P15 P16 (UART2-RX) P17 (UART2-TX) UART device CCR0 COM0 COM7 COM15/SEG7 I/O P20 P21 P22 P23 Pulse output RTST On-chip debugger CF1 CF

No.A1228-13/25 Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Maximum supply voltage VDD max V DD V DD -0.3 +6.5 V LCD supply voltage VLCD max V LCD2 to VLCD4 V DD -0.3 +6.5 LCD maximum supply voltage LCD max SEG0 to SEG71 COM0 to COM15 VDD, VLCD4 -0.3 +6.5 Input voltage V I(1) RESB, XT1, CF1 -0.3 V DD+0.3 Input/output voltage VIO(1) PORT 0, 1, 2 SEG71 to SEG56 -0.3 V DD+0.3 High level output current Peak output current IOPH(1) PORT0, 2 CMOS output selected Current at each pin mA IOPH(2) PORT1 CMOS output selected Current at each pin -14 Mean output current (Note 1-1) IOMH(1) PORT0, 2 CMOS output selected Current at each pin IOMH(2) PORT1 CMOS output selected Current at each pin Total output current ΣIOAH(1) PORT0, 2 Total of all pins 22.5 ΣIOAH(2) PORT1 Total of all pins 25 ΣIOAH(3) PORT 0, 1, 2 Total of all pins 47.5 Low level output current Peak output current IOPL(1) PORT0, 2 Current at each pin 13 IOPL(2) PORT1 Current at each pin 17 Mean output current (Note 1-1) IOML(1) PORT0, 2 Current at each pin 7.5 IOML(2) PORT1 Current at each pin 10.5 Total output current ΣIOAL(1) PORT0, 2 Total of all pins 35 ΣIOAL(2) PORT1 Total of all pins 60 ΣIOAL(3) PORT 0, 1, 2 Total of all pins 80 Allowable power dissipation Pd max TQFP120(14×14) Ta=-20 to +75 °C 250 mW Operating ambient temperature Topg -20 75 Storage ambient temperature Tstg -65 125 Note 1-1: The mean output current is a mean value measured over 100ms. Note: We assume that the measurements for the allowable operating ranges and electrical characteristics described in this document are performed with the chip mounted in a package. Although this product is shipped in chip form, the characteristic values listed in this document are measured with this IC mounted on a Our designated package at operating ambient temperature range of -20°C to +70°C. The specifications of this product in package form or in chip forms are basically identical, however, the characteristics of the product in chip form may vary depending on the board on which the product is mounted, the bonding pressure, and the type of mold resin used. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Oper ating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No.A1228-14/25 Allowable Operating Conditions at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol Pin /Remarks Conditions Ratings VDD[V] min typ max unit Operating supply voltage (Note2-1) VDD(1) VDD 0.238 μs≤tCYC≤100μs 2.6 5.5 V 0.476μs≤tCYC≤100μs 2.4 5.5 0.909μs≤tCYC≤100μs 2.3 5.5 LCD drive voltage VLCD(1) V LCD2 to VLCD4 5.5 Memory sustaining supply voltage VHD V DD RAM and register contents sustained in HOLD mode. 2.0 5.5 High level input voltage VIH(1) Port 0, 1 Output disabled 0.30VDD +0.70 V DD VIH(2) RESB 0.75V DD V DD Low level input voltage VIL(1) Port 0, 1 Output disabled V SS 0.10VDD +0.40 VIL(2) RESB V SS 0.25V DD Oscillating frequency range (Note2-3) FOSC0 XT1, XT2 Crystal oscillation 2.3 to 5.5 32.768 kHz Low speed RC oscillation (Note2-2) 2.3 to 5.5 30 80 FOSC1 CF1, CF2 Ceramic oscillation 2.4 to 5.5 400 4200 High-speed RC oscillation (Note2-2) 2.4 to 5.5 400 4200 2.3 to 5.5 400 1100 FINTRC Internal RC oscillation 1000 Note2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode. Note2-2: Ta=0°C to 60°C Note2-3: The parts value of oscillation circuit is shown in table 1 and table 2.

No.A1228-15/25 Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit High level input current IIH(1) PORT 0, 1, 2 Output disabled Pull-up resister OFF VIN=VDD (including OFF state leak current of the output Tr.) 2.7 to 5.5 1 μA IIH(2) RESB V IN=VDD 2.7 to 5.5 1 Low level input current IIL(1) PORT 0, 1, 2 Output disabled Pull-up resister OFF VIN=VSS (including OFF state leak current of the output Tr.) 2.7 to 5.5 -1 IIL(2) PORT 0, 1, 2 Output disabled Pull-up resister ON VIN=VSS (including OFF state leak current of the output Tr.) 4.5 to 5.5 -117 -25 IIL(4) RESB 4.5 to 5.5 -10.2 -3.7 High level output current IOH(1) CMOS output mode PORT0, 2 VOH(1)=VDD-1.0V 4.5 to 5.5 -3.7 mA IOH(3) CMOS output mode PORT1 4.5 to 5.5 -10 Low level output current IOL(1) PORT0, 2 VOL(1)=VSS+1.0V 4.5 to 5.5 10 IOL(2) 2.7 to 3.0 4.4 IOL(3) PORT1 4.5 to 5.5 14.5 IOL(4) 2.7 to 3.0 6.5 IOL(5) SEG71 to SEG56 4.5 to 5.5 0.5 IOL(6) 2.7 to 3.0 0.5 Common output current IOH(5) COM0 to COM15 V OH(2)=VLCD4-0.05V 2.7 to 5.5 -25 μA IOL(7) V OL(2)=VSS+0.05V 25 Segment output current IOH(6) SEG0 to SEG71 V OH(2)=VLCD4-0.05V 2.7 to 5.5 -10 IOL(8) V OL(2)=VSS+0.05V 10 Hysterisis voltage VH YS(1) PORT 0, 1, 2 RESB 2.7 to 5.5 0.1V DD V Pin capacitance CP All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.7 to 5.5 10 pF

No.A1228-16/25 LCD Drive Voltage at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Special notes: 0.1μF capacitor must be connected to VLCD1, VLCD2, VLCD3, and VLCD4. (with no panel load) Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit LCD drive voltage VLCD1 V DD VLCD1 Contrast “00” 2.4 to 5.5 Typ ×0.88 1.030 Typ ×1.10 V Contrast “01” 1.045 Contrast “02” 1.060 Contrast “03” 1.075 Contrast “04” 1.090 Contrast “05” 1.105 Contrast “06” 1.120 Contrast “07” 1.135 Contrast “08” 1.150 Contrast “09” 1.165 Contrast “10” 1.180 Contrast “11” 1.195 Contrast “12” 1.210 Contrast “13” 1.225 Contrast “14” 1.240 Contrast “15” 1.255 VLCD2 2×VLCD1 VLCD3 3×VLCD1 VLCD4 4×VLCD1

No.A1228-17/25 Serial I/O Characteristics at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V 1. SIO0 Serial I/O Characteristics (Wake-up function is not in use) (Note 4-1-1) Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(1) SCK0(P12) See Fig. 6. 2.3 to 5.5 tCYC Low level pulse width tSCKL(1) High level pulse width tSCKH(1) tSCKHA(1) Automatic communication mode See Fig. 6. tSCKHBSY(1a) Automatic communication mode See Fig. 6. tSCKHBSY(1b) Excluding Automatic communication mode See Fig. 6. Output clock Frequency tSCK(2) SCK0(P12) CMOS output selected See Fig. 6. 2.3 to 5.5 Low level pulse width tSCKL(2) tSCK High level pulse width tSCKH(2) tSCKHA(2) Automatic communication mode CMOS output selected See Fig. 6. tCYC tSCKHBSY(2a) Automatic communication mode CMOS output selected See Fig. 6. 4 23 tSCKHBSY(2b) Excluding automatic communication mode See Fig. 6. Serial input Data setup time tsDI(1) SI0(P11), SB0(P11) Must be specified with respect to rising edge of SIOCLK. See Fig. 6. 2.3 to 5.5 0.03 μs Data hold time thDI(1) 0.03 Serial output Input clock Output delay time tdD0(1) SO0(P10), SB0(P11) (Note4-1-2) 2.3 to 5.5 1tCYC +0.05 Output clock tdDO(2) (Note4-1-2) 1tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.6.

No.A1228-18/25 2. SIO1 Serial I/O Characteristics (Wake-up function is not in use) (Note 4-2-1) Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(3) SCK0(P12) See Fig. 6. 2.3 to 5.5 tCYC Low level pulse width tSCKL(3) High level pulse width tSCKH(3) tSCKHBSY(3) Serial input Data setup time tsDI(2) SI0(P11), SB0(P11) Must be specified with respect to rising edge of SIOCLK. See Fig. 6. 2.3 to 5.5 0.03 μs Data hold time thDI(2) 0.03 Serial output Input clock Output delay time tdD0(3) SO0(P10), SB0(P11) (Note4-2-2) 2.3 to 5.5 1tCYC +0.05 Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Note 4-2-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.6. UART2 Operating Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Transfer rate UBR2 URX2(P16), UTX2(P17) 2.3 to 5.5 8 4096 tCYC Pulse Input Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit High/low level pulse width tPIL(1) RESB Resetting is enabled. 2.3 to 5.5 50 μs

No.A1228-19/25 AD Converter Characteristics at VSS = LCDVSS0 = LCDVSS1 = 0V <12-bits AD Converter Mode/Ta= -10°C to +75°C> Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Resolution N AN0(SEG71) to AN3(SEG68) 2.9 to 5.5 12 bit Absolute accuracy ET (Note7-1) 2.9 to 5.5 ±16 LSB Conversion time TCAD See Conversion time calculation formulas. (Note7-2) 2.9 to 5.5 90 130 μs Analog input voltage range VAIN 2.9 to 5.5 V SS V DD V Analog ports input current IAINH VAIN=V DD 2.9 to 5.5 1 μA IAINL VAIN=V SS 2.9 to 5.5 -1 <8-bits AD Converter Mode/Ta= -10°C to +75°C > Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Resolution N AN0(SEG71) to AN3(SEG68) 2.9 to 5.5 8 bit Absolute accuracy ET (Note7-1) 2.9 to 5.5 ±1.5 LSB Conversion time TCAD See Conversion time calculation formulas. (Note7-2) 2.9 to 5.5 55 75 μs Analog input voltage range VAIN 2.9 to 5.5 V SS V DD V Analog ports input current IAINH VAIN=V DD 2.9 to 5.5 1 μA IAINL VAIN=V SS 2.9 to 5.5 -1 <Conversion Time Calculation Formulas> 12-bits AD Converter Mode: TCAD (Conversion time) = ((52/(Division ratio))+2) × tCYC 8-bits AD Converter Mode: TCAD (Conversion time) = ((32/(Division ratio))+2) × tCYC <Recommended Operating Conditions> External Oscillator FmCF[MHz] Operating Supply Voltage Range VDD[V] System Division Ratio (SYSDIV) Cycle Time tCYC [ns] AD Division Ratio (ADDIV) AD Conversion Time (TCAD)[μs] 12-bit AD 8-bit AD CF-4 2.9 to 4.0 1/1 250 1/8 104.5 64.5 1/2 500 1/4 105.0 65.0 Note 7-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 7-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when:

  • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
  • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.

No.A1228-20/25 Consumption Current Characteristics at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Consumption current during normal operation (Note 8-1) IDDOP(1) VDD Crystal oscillation mode

  • FOSC0=32.768kHz
  • System clock: FOSC0
  • Internal RC oscillation stopped
  • FOSC1=0Hz (Oscillation stop)
  • 1/1frequency division ratio. [No panel load] LCD Display ON 2.4 to 5.5 70 150 μA IDDOP(2) 2.4 to 3.6 50 80 IDDOP(3) LCD Display OFF 2.3 to 5.5 70 120 IDDOP(4) 2.3 to 3.6 40 70 IDDOP(5) Ceramic oscillation mode
  • FOSC1=4MHz
  • System clock: FOSC1
  • Internal RC oscillation stopped
  • FOSC0=0Hz (Oscillation stop)
  • 1/2 frequency division ratio. 2.4 to5.5 3000 4100 IDDOP(6) 2.4 to 3.6 2200 2900 IDDOP(7) Internal RC oscillation mode
  • System clock: Internal RC
  • Internal RC oscillates
  • FOSC0=0Hz (Oscillation stop)
  • FOSC1=0Hz (Oscillation stop)
  • 1/1 frequency division ratio 2.3 to 5.5 1900 3000 IDDOP(8) 2.3 to3.6 1200 2000 IDDOP(9) High-speed RC oscillation mode *Ta=0 to 60°C
  • FOSC1=1MHz RCR1=470kΩ
  • System clock: FOSC1
  • Internal RC oscillation stopped
  • FOSC0=0Hz (Oscillation stop)
  • 1/1 frequency division ratio. 2.3 to 5.5 1700 2300 IDDOP(10) 2.3 to 3.6 1200 1700 IDDOP(11) Low-speed RC oscillation mode *Ta=0 to 60°C
  • FOSC0=64kHz RCR0=910kΩ
  • System clock: FOSC0
  • Internal RC oscillation stopped
  • FOSC1=0Hz (Oscillation stop)
  • 1/1 frequency division ratio. 2.3 to 5.5 110 170 IDDOP(12) 2.3 to 3.6 70 110 Note 8-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page.

No.A1228-21/25 Continued from preceding page. Parameter Symbol Pin/ Remarks Condition Specification VDD[V] min typ max unit Consumption current during HALT mode (Note 8-1) IDDHALT(1) VDD HALT mode Crystal oscillation mode

  • FOSC0=32.768kHz
  • System clock: FOSC0
  • Internal RC oscillation stopped
  • FOSC1=0Hz (Oscillation stop)
  • 1/1frequency division ratio. [No panel load] LCD Display ON 2.4 to 5.5 32 93 μA IDDHALT(2) 2.4 to 3.6 15 35 IDDHALT(3) LCD Display OFF 2.3 to 5.5 22 59 IDDHALT(4) 2.3 to 3.6 6 21 IDDHALT(5) HALT mode Ceramic oscillation mode
  • FOSC1=4MHz
  • System clock: FOSC1
  • Internal RC oscillation stopped
  • FOSC0=0Hz (Oscillation stop)
  • 1/2 frequency division ratio. 2.4 to 5.5 700 1100 IDDHALT(6) 2.4 to 3.6 300 500 IDDHALT(7) HALT mode Internal RC oscillation mode
  • System clock: Internal RC
  • Internal RC oscillates
  • FOSC0=0Hz (Oscillation stop)
  • FOSC1=0Hz (Oscillation stop)
  • 1/1 frequency division ratio. 2.3 to 5.5 400 700 IDDHALT(8) 2.3 to 3.6 200 300 IDDHALT(9) HALT mode High-speed RC oscillation mode *Ta=0 to 60°C
  • FOSC1=1MHz RCR1=470kΩ
  • System clock: FOSC1
  • Internal RC oscillation stopped
  • FOSC0=0Hz (Oscillation stop)
  • 1/1 frequency division ratio. 2.3 to 5.5 200 400 IDDHALT(10) 2.3 to 3.6 100 200 IDDHALT(11) HALT mode Low-speed RC oscillation mode *Ta=0 to 60°C
  • FOSC0=64kHz RCR0=910kΩ
  • System clock: FOSC0
  • Internal RC oscillation stopped
  • FOSC1=0Hz (Oscillation stop)
  • 1/1 frequency division ratio. 2.3 to 5.5 20 50 IDDHALT(12) 2.3 to 3.6 10 30 Consumption current during HOLD mode IDDHOLD(1) V DD HOLD mode
  • CF1=VDD or OPEN (External clock mode) 2.3 to 5.5 12 IDDHOLD(2) 2.3 to 3.6 5 Consumption current during clock HOLD mode IDDHOLD(3) VDD Clock HOLD mode
  • CF1=VDD or OPEN (External clock mode)
  • FmX’tal=32.768kHz crystal oscillation mode 2.3 to 5.5 16 55 IDDHOLD(4) 2.3 to 3.6 3 16 Note 8-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Onboard programming current IDDFW(1) V DD The consumption current of the microcomputer is excluded. 2.7 to 5.5 5 10 mA Programming time tFW(1) Erasing time: 128 bytes 2.7 to 5.5 20 30 ms tFW(2) Programming time: 2 bytes 2.7 to 5.5 40 60 μs

No.A1228-23/25 Reset Time and Oscillation Stabilization Time HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time Internal RC oscillation CF1, CF2 XT1, XT2 State HOLD reset signal HOLD reset signal absent HOLD reset signal valid tmsCF tmsX’tal HOLD HALT Power supply RESB Internal RC oscillation CF1, CF2 XT1, XT2 Operating mode Reset time tmsCF tmsX’tal Unpredictable Reset Instruction execution VDD Operating VDD lower limit

No.A1228-25/25 Note: The oscillation frequency changes with the board pattern and used parts when OSC1 and OSC0 are used as the RC oscillation. It also greatly depends on the product shape (chip and plastic package) and the board capacitance, and it is recommended to evaluate the resistor value with an actual product. Use the following characteristics as only for a reference. Figure 8 Characteristics of Resistor v.s. Frequency of OSC1 Figure 9 Characteri stics of Resistor v.s. Frequency of OSC0 PS 0.1 200 1000 8000 400 600 1200 Frequency - Resistor Resistor - kΩ Frequency - MHz ILC05650 1.0 Ta=25°C, typ 200 1000 8000 400 600 1200 Frequency - Resistor Resistor - kΩ Frequency - kHz ILC05651 1000 100 Ta=25°C, typ ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s techn ical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC productsfor any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, anddistributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture oft h e part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.