LC88F58B0A

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Technical content

Features

Xstromy16 CPU

• 4G-byte address space
• General-purpose registers: 16 bits × 16 registers Flash ROM
• Capable of onboard programming with a wide range of voltage levels (3.0 to 5.5V).
• Block-erasable in 128 or 1K byte units.
• Data written in 2-byte units.
• 131072 × 8 bits RAM
• 6144 × 8 bits CMOS IC FROM 128K byte, RAM 6K byte on-chip 16-bit 1-chip Microcontroller * This product is licensed from Silicon Storage Technology, Inc. (USA).

No.A1951-2/31 Minimum Instruction Cycle Time (tCYC)

• 83.3 ns (12MHz) V DD = 4.5 to 5.5V
• 100 ns (10MHz) V DD = 3.0 to 5.5V
• 500 ns (2MHz) V DD = 2.2 to 5.5V Ports
• Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units : 52 (P0n, P1n, P2n, P30 to P33, P4n, P6n, P70 to P72, PA0 to PA3, PC2)
• Oscillation/normal withstand voltage I/O ports : 2 (PC0, PC1)
• Oscillation dedicated ports : 2 (CF1, CF2)
• Reset pins : 1 (RESB)
• TEST pins : 1 (TEST)
• Power pins : 6 (V SS1 to 3, VDD1 to 3) Timers
• Timer 0: 16-bit timer that supports PWM/toggle outputs 1) 5-bit prescaler 2) 8-bit PWM × 2, 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
• Timer 1: 16-bit timer with capture registers 1) 5-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
• Timer 2: 16-bit timer with capture registers 1) 4-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and external events
• Timer 3: 16-bit timer that supports PWM/toggle outputs 1) 8-bit prescaler 2) 8-bit timer × 2ch or 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and external events
• Timer 4: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0
• Timer 5: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0
• Base timer 1) Clock may be selected from OSC0 (32.768kHz crystal oscillator) and frequency-divided output of system clock. 2) Interrupts can be generated in 7 timing schemes.

No.A1951-3/31 Serial Interfaces

• SIO0: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) 3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) 4) Continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) Interval function (intervals specifiable in 0 to 64 tSCK units) 6) Wakeup function
• SIO1: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) 3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) 4) Continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) Interval function (intervals specifiable in 0 to 64 tSCK units) 6) Wakeup function
• SMIIC0: Single master I 2C/8-bit synchronous SIO Mode 0: Single-master mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first)
• UART0 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 4/8 cycle 6) Baudrate source clock : P07 input signal used as a 1 cycle signal (T0PWMH can be used as a clock source) 7) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source.
• UART2 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1/2 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 8 to 4096 cycle 6) Baudrate source clock : System clock/OSC0/OSC1 7) Wakeup function 8) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. AD Converter 1) 12/8 bits resolution selectable 2) Analog input: 11 channels 3) Comparator mode 4) Automatic reference voltage generation PWM
• PWM0: Multifrequency 12-bit PWM × 2 channels (PWM0A and PWM0B) 1) 2-channel pairs controlled independently of one another 2) Clock source selectable from system clock or OSC1 3) 8-bit prescaler: TPWMR0=(prescaler value + 1) × clock period 4) 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit 5) Fundamental wave PWM mode Fundamental wave period : 16 TPWMR0 to 256 TPWMR0 High pulse width : 0 to (Fundamental wave period - TPWMR0) 6) Fundamental wave + additional pulse mode Fundamental wave period : 16 TPWMR0 to 256 TPWMR0 Overall period : Fundamental wave period × 16 High pulse width : 0 to (Fundamental wave period - TPWMR0)

No.A1951-4/31 Watchdog Timer 1) Driven by the base timer + internal watchdog timer dedicated counter 2) Interrupt or reset mode selectable Motor Drive Signal Generator Circuit Interrupts (peripheral function)

• 40 sources (24 modules), 16 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Interrupt Module 1 08000H Watchdog timer (1) 2 08004H Base timer (2) 3 08008H Timer 0 (2) 4 0800CH INT0 (1) 5 08010H 6 08014H INT1 (1) 7 08018H INT2 (1)/timer 1 (2)/UART2 (4) 8 0801CH INT3 (1)/timer 2 (4)/SMIIC0 (1) 9 08020H INT4 (1)/timer 3 (2) 10 08024H INT5 (1)/timer 4 (1)/SIO1 (2) 11 08028H USM0 (3) 12 0802CH PWM0 (1) 13 08030H ADC (1)/timer 5 (1) 14 08034H INT6 (1) 15 08038H INT7 (1)/SIO0 (2) 16 0803CH Port 0 (3)
• 3 priority levels selectable.
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• A number enclosed in parentheses denotes the number of sources. Subroutine Stack: 6K-byte RAM area
• Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes
• Subroutine calls that do not automatically save PSW: 4 bytes Multiplication/Division Instructions
• 16 bits × 16 bits (18 tCYC execution time)
• 16 bits ÷ 16 bits (18 to 19 tCYC execution time)
• 32 bits ÷ 16 bits (18 to 19 tCYC execution time) Oscillator Circuits
• RC oscillator circuit (internal): For system clock
• OSC1 (CF oscillator circuit): For system clock, built-in Rf circuit
• OSC0 (crystal oscillator circut): For low-speed system clock
• SLRC oscillator circuit (internal): For system clock (exception processing time) System Clock Divider Function
• Can run on low current.
• 1/1 to 1/128 of the system clock frequency can be set.

No.A1951-5/31 Standby Function

• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not stopped automatically. 2) Released by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) OSC1, RC and OSC0 oscillators automatically stop. 2) There are three ways of releasing the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt established at SIO0 or SIO1 (5) Having an interrupt established at UART2
• HOLDX mode: Suspends instruction execution and the operation of the peripheral circuits except those which run on OSC0. 1) OSC1 and RC oscillations automatically stop. 2) OSC0 maintains the state that is established when the HOLDX mode is entered. 3) There are four ways of releasing the HOLDX mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established at the base timer circuit (5) Having an interrupt established at SIO0 or SIO1 (6) Having an interrupt established at UART2 On-chip Debugger Function
• Supports software debugging with the IC mounted on the target board.
• Supports source line debugging and tracing functions, and breakpoint setting.
• Single-wire communication Package Form
• SQFP64 (10×10): Lead-free and halogen-free type Development Tools
• On-chip debugger: EOCUIF1 + LC88F58B0A Programming Board Package Programming Board SQFP64 (10 × 10) W88F58SQ Flash Programming Manufacturer Model Name Supported Version Device Flash Support Group (Single) AF9708/09/09B/09C Revison : After Rev.03.04 LC88F58B0A Flash Support Group (Gang) AF9723/23B Revison : After Rev.02.29 LC88F58B0A AF9833 Revison : After Rev.01.90 Our company SKK/SKK Type-B Revison : After Rev.01.13 LC88F58B0A

No.A1951-6/31 Package Dimensions unit : mm (typ) 3190A Pin Assignment SQFP64 (10×10) (Lead-free and halogen-free type) 10.0 10.0 12.0 12.0 0.15 0.5 (1.5)0.1 1.7max 0.180.5 (1.25) 11 6 3348 SANYO : SQFP64(10X10) LC88F58B0A Top view P33/INT3 PC2/FILT PA3/USM0O3 PA2/USM0O2 PA1/USM0O1 PA0/USM0O0 P40/INT6 P41/INT7 P42 P43/SO1 P44/SI1/SB1 P45/SCK1 VDD3 VSS3 P46/PWM0A P47/PWM0B P72/AN10 P71/AN9 P70/AN8 P17/U2TX P16/U2RX P15/T3OH P14/T3OL/U0RX P13/U0TX P12/SCK0 P11/SI0/SB0 P10/SO0 P07/T0PWMH/U0BRG P06/T0PWML P05/P05INT P04/P04INT P03/P0INT P32/INT2 P31/INT1 P30/INT0 TEST RESB PC0/XT1 PC1/XT2 VSS1 CF1 CF2 VDD1 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P20/INT4 P21/INT5 P22/SM0CK P23/SM0DA P24/SM0DO VDD2 VSS2 P25/T4O P26/T5O P27 P00/P0INT P01/P0INT P02/P0INT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

No.A1951-7/31 System Block Diagram Clock generator CF RC X’tal Port 0 Port 1 SIO0 SIO1 SMIIC0 Timer 0 Timer 1 Timer 2 Timer 3 Port 2 Port 3 Port 4 Port 6 UART0 Port C Timer 4 PWM0 On-chip debugger Port 7 Xstromy16 CPU RAM FLASH ROM Base timer Watchdog timer AD INT0 to INT7 Motor control signal generator Timer 5 Port A Low speed RC UART2

No.A1951-8/31 Pin Description Pin Name I/O Description VSS1, VSS2, VSS3 - - Power sources VDD1, VDD2, VDD3 - + Power sources Port 0 I/O • 8-bit I/O port

• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• HOLD release input (P00 to P03, P04, P05)
• Port 0 interrupt input (P00 to P03, P04, P05)
• Pin functions P06: Timer 0L output P07: Timer 0L output/UART0 clock input P00 to P07 Port 1 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions P10: SIO0 data output P11: SIO0 data input/pulse input/output P12: SIO0 clock input/output P13: UART0 transmit P14: Timer 3L output/UART0 receive P15: Timer 3H output P16: UART2 receive P17: UART2 transmit P10 to P17 Port 2 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions P20: INT4 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input P21: INT5 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input P22: SMIIC0 clock input/output P23: SMIIC0 bus input/output/data input P24: SMIIC0 data output (used in 3-wire SIO mode) P25: Timer 4 output P26: Timer 5 output Interrupt acknowledge type INT4, INT5: H level, L level, H edge, L edge, both edges P20 to P27 Port 3 I/O • 4-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions P30: INT0 input/HOLD release/timer 2L capture input P31: INT1 input/HOLD release/timer 2H capture input P32: INT2 input/HOLD release/timer 2 event input/timer 2L capture input P33: INT3 input/HOLD release/timer 2 event input/timer 2H capture input Interrupt acknowledge type INT0 to INT3: H level, L level, H edge, L edge, both edges P30 to P33 Continued on next page.

No.A1951-9/31 Continued from preceding page. Pin Name I/O Description Port 4 I/O • 8-bit I/O port

• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions P40: INT6 input/HOLD release input P41: INT7 input/HOLD release input P43: SIO1 data output P44: SIO1 data input/bus input/output P45: SIO1 clock input/output P46: PWM00 output P47: PWM01 output Interrupt acknowledge type INT6, INT7: H level, L level, H edge, L edge, both edges P40 to P47 Port 6 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions AN0 (P60) to AN7 (P67): AD converter input port P60 to P67 Port 7 I/O • 3-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions AN8 (P70) to AN10 (P72): AD converter input port P70 to P72 Port A I/O • 4-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Multiplexed pin functions PA0: USM0 output 0 PA1: USM0 output 1 PA2: USM0 output 2 PA3: USM0 output 3 PA0 to PA3 Port C I/O • 3-bit I/O port (on output: Nch-open drain (PC0 to PC1), CMOS (PC2))
• I/O specifiable in 1-bit units
• Pin functions PC0: 32.768kHz crystal oscillator input PC1: 32.768kHz crystal oscillator output PC2: FILT PC0 to PC2 TEST I/O • TEST pin
• Used to communicate with on-chip debugger.
• Connects an external 100kΩ pull-down resistor. RESB I Reset pin CF1 I Ceramic oscillator input pin CF2 O Ceramic oscillator output pin

No.A1951-10/31 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of Option Type No. Output Type Pull-up Resistor P00 to P07 P10 to P17 P20 to P27 P30 to P33 P40 to P47 P60 to P67 P70 to P72 PA0 to PA3 1 bit 1 CMOS Programmable

2 N-channel open drain

PC0 - - N-channel open drain (32.768kHz crystal oscillator input) None PC1 - - N-channel open drain (32.768kHz crystal oscillator output) None * Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. Be sure to electrically short the VSS1, VSS2 and VSS3 pins. Example 1: When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the backup capacitors. Example 2: When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is unpredictable. Power supply For buckup LSI VSS1V SS2V SS3 VDD3 VDD2 VDD1 1kΩ 2.2μF PC2/FILT VDD3 VDD2 VDD1 LSI VSS1V SS2V SS3 1kΩ 2.2μF PC2/FILT Power supply For buckup

No.A1951-11/31 Parameter Symbol Applicable Pin /Remarks Conditions Specification VDD[V] min typ max unit Maximum supply voltage VDD max V DD1, VDD2, VDD3 V DD1=VDD2=VDD3 -0.3 +6.5 V Input voltage V I(1) CF1, RESB -0.3 VDD +0.3 Input/output voltage VIO(1) Ports 0, 1, 2 Ports 3, 4 Ports 6, 7 Ports A, C -0.3 VDD +0.3 High level output current Peak output current IOPH(1) Ports 0, 1, 2 P70 to P72 P40 to P45 PA0 to PA3 CMOS output selected Per applicable pin -10 mA IOPH(2) P46, P47 Per applicable pin -20 IOPH(3) Port 6 P30 to P33 PC2 Per applicable pin Average output current (Note 1-1) IOMH(1) Ports 0, 1, 2 P70 to P72 P36 to P37 P40 to P45 PA0 to PA3 CMOS output selected Per applicable pin -7.5 IOMH(2) P46, P47 Per applicable pin -10 IOMH(3) Port 6 P30 to P33 PC2 Per applicable pin Total output current ΣIOAH(1) P30 to P33, PC2 Total of currents at applicable pins -15 ΣIOAH(2) Port 6 Total of currents at applicable pins -15 ΣIOAH(3) Port 6 P30 to P33 PC2 Total of currents at applicable pins -20 ΣIOAH(4) Ports 0, 1 P25 to P27 Total of currents at applicable pins -25 ΣIOAH(5) P20 to P24 Total of currents at applicable pins -25 ΣIOAH(6) Ports 0, 1, 2 Total of currents at applicable pins -45 ΣIOAH(7) P40 to P45 PA0 to PA3 Total of currents at applicable pins -25 ΣIOAH(8) P46 to P47 P70 to P72 Total of currents at applicable pins -25 ΣIOAH(9) Port 4 P70 to P72 PA0 to PA3 Total of currents at applicable pins -45 Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Continued on next page.

No.A1951-12/31 Continued from preceding page. Parameter Symbol Applicable Pin /Remarks Conditions Specification VDD[V] min typ max unit Low level output current Peak output current IOPL(1) Ports 0, 1, 4 P70 to P72 PA0 to PA3 P20, P21, P24 to P27 Per applicable pin mA IOPL(2) P22, P23 Per applicable pin 25 IOPL(3) P30 to P33 Port 6 PC0 to PC2 Per applicable pin Average output current (Note 1-1) IOML(1) Ports 0, 1, 4 P70 to P72 PA0 to PA3 P20, P21, P24 to P27 Per applicable pin IOML(2) P22, P23 Per applicable pin 20 IOML(3) P30 to P33 Port 6 PC0 to PC2 Per applicable pin 7.5 Total output current ΣIOAL(1) P30 to P34 PC0 to PC2 Total of currents at applicable pins 15 ΣIOAL(2) Port 6 Total of currents at applicable pins 15 ΣIOAL(3) Port 6 P30 to P33 PC0 to PC2 Total of currents at applicable pins 20 ΣIOAL(4) Ports 0, 1 P25 to P27 Total of currents at applicable pins 45 ΣIOAL(5) P20 to P24 Total of currents at applicable pins 45 ΣIOAL(6) Ports 0, 1, 2 Total of currents at applicable pins 80 ΣIOAL(7) P40 to P45 PA0 to PA3 Total of currents at applicable pins 45 ΣIOAL(8) P46 to P47 P70 to P72 Total of currents at applicable pins 45 ΣIOAL(9) Port 4 P70 to P72 PA0 to PA3 Total of currents at applicable pins 80 Allowable power dissipation Pd max SQFP64 (10 ×10) Ta=-40 to +85 °C 200 mW Operating ambient temperature Topr -40 +85 Storage ambient temperature Tstg -55 +125 Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Oper ating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No.A1951-13/31 Allowable Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Applicable Pin /Remarks Conditions Specification VDD[V] min typ max unit Operating supply voltage (Note 2-1) VDD(1) V DD1=VDD2=VDD3 0.081 μs≤tCYC≤66μs 4.5 5.5 V 0.098μs≤tCYC≤66μs 3.0 5.5 0.490μs≤tCYC≤66μs 2.2 5.5 Memory sustaining supply voltage VHD V DD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode 2.0 5.5 High level input voltage VIH(1) Ports 0, 1, 2, 3, 4 Port A 2.2 to 5.5 0.3VDD +0.7 V DD VIH(2) Ports 6, 7, PC2 2.2 to 5.5 0.3VDD +0.7 V DD VIH(3) CF1, RESB PC0, PC1 2.2 to 5.5 0.75VDD V DD VIH(4) P22, P23 I 2C side 2.2 to 5.5 0.7V DD V DD Low level input voltage VIL(1) When ports 1, 2, 3, 4 and port A, PnFSAn=0 Ports 0, 6, 7, PC2 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(2) 2.2 to 4.0 V SS 0.2V DD VIL(3) When ports 1, 2, 3, 4 and port A, PnFSAn=1 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(4) 2.2 to 4.0 V SS 0.2V DD VIL(5) CF1, RESB PC0, PC1 2.2 to 5.5 V SS 0.25V DD VIL(6) P22, P23 I 2C side 2.2 to 5.5 V SS 0.3V DD Instruction cycle time (Note 2-2) tCYC 4.5 to 5.5 0.081 66 μs 3.0 to 5.5 0.098 66 2.2 to 5.5 0.490 66 External system clock frequency FEXCF(1) CF1 • CF2 pin open

• System clock frequency division ratio=1/1
• External system clock DUTY50±5% 4.5 to 5.5 0.1 12 MHz 3.0 to 5.5 0.1 10 2.2 to 5.5 0.1 2
• CF2 pin open
• System clock frequency division ratio=1/2 4.5 to 5.5 0.2 24 3.0 to 5.5 0.2 20 2.2 to 5.5 0.2 4 Oscillation frequency range (Note 2-3) FmCF(1) CF1, CF2 12MHz ceramic oscillator mode See Fig. 1. 4.5 to 5.5 12 MHz FmCF(2) CF1, CF2 10MHz ceramic oscillator mode See Fig. 1. 3.0 to 5.5 10 FmCF(3) CF1, CF2 4MHz ceramic oscillator mode See Fig. 1. 2.2 to 5.5 4 FmSLRC Internal low-speed RC oscillation 2.2 to 5.5 18 30 45 kHz FsX'tal XT1, XT2 32.768kHz crystal oscillator mode See Fig. 2. 2.2 to 5.5 32.768 Note 2-1: VDD≥3.0V must be maintained when making onboard programming into flash ROM. Note 2-2: Relationship between tCYC and oscillation frequency is 1/FmCF when frequency division ratio is 1/1 and 2/FmCF when the ratio is 1/2. Note 2-3: See Tables 1 and 2 for oscillator constant values.

No.A1951-14/31 Parameter Symbol Applicable Pin /Remarks Conditions Specification VDD[V] min typ max unit High level input current IIH(1) Ports 0, 1, 2 Ports 3, 4 Ports 6, 7 Ports A, C RESB Output disabled Pull-up resistor off VIN=VDD (Including output Tr. off leakage current) 2.2 to 5.5 1 μA IIH(2) CF1 V IN=VDD 2.2 to 5.5 15 Low level input current IIL(1) Ports 0, 1, 2 Ports 3, 4 Ports 6, 7 Ports A, C RESB Output disabled Pull-up resistor off VIN=VSS (Including output Tr. off leakage current) 2.2 to 5.5 -1 IIL(2) CF1 V IN=VSS 2.2 to 5.5 -15 High level output voltage VOH(1) Ports 0, 1, 2 PA0 to PA3 P40 to P45 IOH=-1.0mA 4.5 to 5.5 V DD-1 V VOH(2) I OH=-0.4mA 3.0 to 5.5 V DD-0.4 VOH(3) I OH=-0.2mA 2.2 to 5.5 V DD-0.4 VOH(4) Port 6 P30 to P33 PC2 IOH=-0.4mA 3.0 to 5.5 V DD-0.4 VOH(5) I OH=-0.2mA 2.2 to 5.5 V DD-0.4 VOH(6) P46, P47 I OH=-10mA 4.5 to 5.5 V DD-1.5 VOH(7) I OH=-1.6mA 3.0 to 5.5 V DD-0.4 VOH(8) I OH=-1.0mA 2.2 to 5.5 V DD-0.4 Low level output voltage VOL(1) Ports 0, 1 Ports 4, 7 P20 to P21, P24 to P27 PA0 to PA3 IOL=10mA 4.5 to 5.5 1.5 VOL(2) I OL=1.6mA 3.0 to 5.5 0.4 VOL(3) I OL=1.0mA 2.2 to 5.5 0.4 VOL(4) P22, P23 I OL=11mA 4.5 to 5.5 1.5 VOL(5) I OL=3.0mA 3.0 to 5.5 0.4 VOL(6) I OL=1.3mA 2.2 to 5.5 0.4 VOL(7) Ports 6, C P30 to P33 IOL=1.6mA 3.0 to 5.5 0.4 VOL(8) I OL=1.0mA 2.2 to 5.5 0.4 Pull-up resistor Rpu(1) Ports 0, 1, 2, 3 Ports 4, 6, 7 Ports A, PC2 VOH=0.9VDD 4.5 to 5.5 15 35 80 kΩ Rpu(2) 2.2 to 4.5 18 55 150 Hysteresis voltage VHYS RESB When ports 1, 2, 3, 4, A PnFSAn=1 2.2 to 5.5 0.1VDD V Pin capacitance CP All pins Pins other than that under test VIN=VSS f=1MHz Ta=25°C 2.2 to 5.5 10 pF

No.A1951-15/31 Serial I/O Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1) Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Period tSCK(1) SCK0 (P12) • See Fig. 6. 2.2 to 5.5 tCYC Low level pulse width tSCKL(1) High level pulse width tSCKH(1) 2 tSCKHA(1) • Automatic communication mode

• See Fig. 6. tSCKHBSY(1a) • Automatic communication mode
• See Fig. 6. tSCKHBSY(1b) • Mode other than automatic communication mode
• See Fig. 6. Output clock Period tSCK(2) SCK0 (P12) • CMOS output selected
• See Fig. 6. 2.2 to 5.5 Low level pulse width tSCKL(2) tSCK High level pulse width tSCKH(2) tSCKHA(2) • Automatic communication mode
• CMOS output selected
• See Fig. 6. tCYC tSCKHBSY(2a) • Automatic communication mode
• CMOS output selected
• See Fig. 6. 4 23 tSCKHBSY(2b) • Mode other than automatic communication mode
• See Fig. 6. Serial input Data setup time tsDI(1) SI0 (P11), SB0 (P11)
• Specified with respect to rising edge of SIOCLK
• See Fig. 6. 2.2 to 5.5 0.03 μs Data hold time thDI(1) 0.03 Serial output Input clock Output delay time tdD0(1) SO0 (P10), SB0 (P11)
• (Note 4-1-2) 2.2 to 5.5 1tCYC +0.05 Output clock tdDO(2)
• (Note 4-1-2) 1tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6.

No.A1951-16/31 SIO0 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1) Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Period tSCK(3) SCK0 (P12) • See Fig. 6. 2.2 to 5.5 tCYC Low level pulse width tSCKL(3) High level pulse width tSCKH(3) 1 tSCKHBSY(3) 2 Serial input Data setup time tsDI(2) SI0 (P11), SB0 (P11)

• Specified with respect to rising edge of SIOCLK
• See Fig. 6. 2.2 to 5.5 0.03 μs Data hold time thDI(2) 0.03 Serial output Input clock Output delay time tdD0(3) SO0 (P10), SB0 (P11)
• (Note 4-2-2) 2.2 to 5.5 1tCYC +0.05 Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Note 4-2-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig.6.

No.A1951-17/31 SIO1 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-3-1) Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Period tSCK(4) SCK1(P45) • See Fig. 6. 2.2 to 5.5 tCYC Low level pulse width tSCKL(4) High level pulse width tSCKH(4) 2 tSCKHA(4) • Automatic communication mode

• See Fig. 6. tSCKHBSY(4a) • Automatic communication mode
• See Fig. 6. tSCKHBSY(4b) • Mode other than automatic communication mode
• See Fig. 6. Output clock Period tSCK(5) SCK1(P45) • CMOS output selected
• See Fig. 6. 2.2 to 5.5 Low level pulse width tSCKL(5) tSCK High level pulse width tSCKH(5) tSCKHA(5) • Automatic communication mode
• CMOS output selected
• See Fig. 6. tCYC tSCKHBSY(5a) • Automatic communication mode
• CMOS output selected
• See Fig. 6. 4 23 tSCKHBSY(5b) • Mode other than automatic communication mode
• See Fig. 6. Serial input Data setup time tsDI(3) SI1(P44), SB1(P44)
• Specified with respect to rising edge of SIOCLK
• See Fig. 6. 2.2 to 5.5 0.03 μs Data hold time thDI(3) 0.03 Serial output Input clock Output delay time tdD0(4) SO1(P43), SB1(P44)
• (Note 4-3-2) 2.2 to 5.5 1tCYC +0.05 μs Output clock tdDO(5)
• (Note 4-3-2) 1tCYC +0.05 Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6.

No.A1951-18/31 SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-4-1) Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Period tSCK(6) SCK1(P45) • See Fig. 6. 2.2 to 5.5 tCYC Low level pulse width tSCKL(6) High level pulse width tSCKH(6) 1 tSCKHBSY(6) 2 Serial input Data setup time tsDI(4) SI1(P44), SB1(P44)

• Specified with respect to rising edge of SIOCLK
• See Fig. 6. 2.2 to 5.5 0.03 μs Data hold time thDI(4) 0.03 Serial output Input clock Output delay time tdD0(6) SO1(P43), SB1(P44)
• (Note 4-4-2) 2.2 to 5.5 1tCYC +0.05 Note 4-4-1: These specifications are theoretical values. Add margin depending on its use. Note 4-4-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. SMIIC0 Simple SIO Mode Input/Output Characteristics Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Period tSCK(7) SM0CK(P22) See Fig. 6. 2.2 to 5.5 tCYC Low level pulse width tSCKL(7) High level pulse width tSCKH(7) 4 Output clock Period tSCK(8) SM0CK(P22) • CMOS output selected
• See Fig. 6. 2.2 to 5.5 Low level pulse width tSCKL(8) tSCK High level pulse width tSCKH(8) Serial input Data setup time tsDI(5) SM0DA(P23) • Specified with respect to rising edge of SIOCLK
• See Fig. 6. 2.2 to 5.5 0.03 μs Data hold time thDI(5) 0.03 Serial output Output delay time tdD0(7) SM0DO(P24), SM0DA(P23)
• Specified with respect to falling edge of SIOCLK
• Specified as interval up to time when output state starts changing.
• See Fig. 6. 2.2 to 5.5 1tCYC +0.05 Note 4-5-1: These specifications are theoretical values. Add margin depending on its use.

No.A1951-19/31 SMIIC0 I2C Mode Input/Output Characteristics Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Clock Input clock Period tSCL SM0CK(P22) • See Fig. 8. 2.2 to 5.5 Tfilt Low level pulse width tSCLL 2.5 High level pulse width tSCLH Output clock Period tSCLx SM0CK(P22) • Specified as interval up to time when output state starts changing. 2.2 to 5.5 Low level pulse width tSCLLx tSCL High level pulse width tSCLHx SM0CK and SM0DA pins input spike suppression time tsp SM0CK(P22) SM0DA(P23)

• See Fig. 8.

1 Tfilt

tBUF SM0CK(P22) SM0DA(P23)

• See Fig. 8. 2.2 to 5.5

2.5 Tfilt

tBUFx SM0CK(P22) SM0DA(P23)

• Standard clock mode
• Specified as interval up to time when output state starts changing. 5.5 μs
• High-speed clock mode
• Specified as interval up to time when output state starts changing. 1.6 Start/restart condition hold time Input tHD;STA SM0CK(P22) SM0DA(P23)
• When SMIIC register control bit, I2CSHDS=0
• See Fig. 8. 2.2 to 5.5 2.0 Tfilt
• When SMIIC register control bit, I2CSHDS=1
• See Fig. 8. 2.5 Output tHD;STAx SM0CK(P22) SM0DA(P23)
• Standard clock mode
• Specified as interval up to time when output state starts changing. 4.1 μs
• High-speed clock mode
• Specified as interval up to time when output state starts changing. 1.0 Restart condition setup time Input tSU;STA SM0CK(P22) SM0DA(P23)
• See Fig. 8. 2.2 to 5.5

1.0 Tfilt

tSU;STAx SM0CK(P22) SM0DA(P23)

• Standard clock mode
• Specified as interval up to time when output state starts changing. 5.5 μs
• High-speed clock mode
• Specified as interval up to time when output state starts changing. 1.6 Continued on next page.

No.A1951-20/31 Continued from preceding page Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Stop condition setup time Input tSU;STO SM0CK(P22) SM0DA(P23)

• See Fig. 8. 2.2 to 5.5

tSU;STOx SM0CK(P22) SM0DA(P23)

• Standard clock mode
• Specified as interval up to time when output state starts changing. 4.9 μs
• High-speed clock mode
• Specified as interval up to time when output state starts changing. 1.1 Data hold time Input tHD;DAT SM0CK(P22) SM0DA(P23)
• See Fig. 8. 2.2 to 5.5 Tfilt Output tHD;DATx SM0CK(P22) SM0DA(P23)
• Specified as interval up to time when output state starts changing. 1 1.5 Data setup time Input tSU;DAT SM0CK(P22) SM0DA(P23)
• See Fig. 8. 2.2 to 5.5 Tfilt Output tSU;DATx SM0CK(P22) SM0DA(P23)
• Specified as interval up to time when output state starts changing. 1tSCL -1.5Tfilt SM0CK and SM0DA pins fall time Input tF SM0CK(P22) SM0DA(P23)
• See Fig. 8. 2.2 to 5.5 300 ns Output tF SM0CK (P22) SM0DA (P23)
• When SMIIC register control bits, PSLW=1, P5V=1 5 20 +0.1Cb 250
• When SMIIC register control bits, PSLW=1, P5V=0 3 20 +0.1Cb 250
• SM0CK, SM0DA port output FAST mode
• Cb≤400pF 3 to 5.5 100 Note 4-6-1: These specifications are theoretical values. Add margin depending on its use. Note 4-6-2: The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 BRP0 Tfilt 0 0 tCYC ×1 0 1 tCYC ×2 1 0 tCYC ×3 1 1 tCYC ×4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range: 250ns ≥ Tfilt >140ns Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF Note 4-6-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt >140ns BRDQ (bit5) = 1 SCL frequency setting ≤ 100kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt >140ns BRDQ (bit5) = 0 SCL frequency setting ≤ 400kHz

No.A1951-21/31 UART2 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Transfer rate UBR2 U2RX(P16), U2TX(P17) 2.2 to 5.5 8 4096 tBGCYC Note 4-7: tBGCYC denotes one cycle of the baudrate clock source. UART0 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Transfer rate UBR0 U0RX(P13), U0TX(P14), U0BRG(P07) 2.2 to 5.5 4 8 tBGCYC Note 4-8: tBGCYC denotes one cycle of the baudrate clock source. Pulse Input Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit High/low level pulse width tPIH(1) tPIL(1) INT0(P30), INT1(P31), INT2(P32), INT3(P33), INT4(P20), INT5(P21), INT6(P40), INT7(P41)

• Interrupt source flag can be set.
• Event inputs for timers 2 and 3 are enabled. 2.2 to 5.5 2 tCYC tPIL(2) RESB Resetting is enabled. 2.2 to 5.5 10 μs

No.A1951-22/31 AD Converter Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V 12-bit AD Conversion Mode Parameter Symbol Applicable Pin /Remarks Conditions Specification VDD[V] min typ max unit Resolution NAD AN0(P60) to AN7(P67), AN8(P70) to AN11(P72) 2.9 to 5.5 12 bit Absolute accuracy ETAD (Note 6-1) 2.9 to 5.5 ±16 LSB Conversion time TCAD12 Conversion time calculated 4.7 to 5.5 17 209 μs 4.0 to 5.5 27 209 2.9 to 5.5 67 209 Analog input voltage range VAIN 2.9 to 5.5 V SS V DD V Analog port input current IAINH VAIN=V DD 2.9 to 5.5 1 μA IAINL VAIN=V SS 2.9 to 5.5 -1 Conversion time calculation formula: TCAD12= ((52/(AD division ratio))+2) × tCYC 8-bit AD Conversion Mode Parameter Symbol Applicable Pin /Remarks Conditions Specification VDD[V] min typ max unit Resolution NAD AN0(P60) to AN7(P67), AN8(P70) to AN11(P72) 2.9 to 5.5 8 bit Absolute accuracy ETAD (Note 6-1) 2.9 to 5.5 ±1.5 LSB Conversion time TCAD8 Conversion time calculated 4.7 to 5.5 11 129 μs 4.0 to 5.5 17 129 2.9 to 5.5 42 129 Analog input voltage range VAIN 2.9 to 5.5 V SS V DD V Analog port input current IAINH VAIN=V DD 2.9 to 5.5 1 μA IAINL VAIN=V SS 2.9 to 5.5 -1 Conversion time calculation formula: TCAD8= ((32/(AD division ratio))+2) × tCYC Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs:

• The first AD conversion is executed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode.

No.A1951-23/31 Consumption Current Characteristics at Ta=-40 to +85°C, VSS1=VSS2=VSS3=0V Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Normal mode consumption current (Note 7-1) IDDOP(1) V DD1 =VDD2 =VDD3

• FmCF=12MHz ceramic oscillation mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz
• Internal RC oscillation stopped
• 1/1 frequency division mode 4.5 to 5.5 9.3 15.0 mA IDDOP(2) • FmCF=10MHz ceramic oscillator mode
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 10MHz
• Internal RC oscillation stopped
• 1/1 frequency division mode 4.5 to 5.5 8.5 14.4 IDDOP(3) 3.0 to 4.5 5.0 8.3 IDDOP(4) • FmCF=4MHz ceramic oscillator mode
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 4MHz
• Internal RC oscillation stopped
• 1/2 frequency division mode 4.5 to 5.5 3.8 5.6 IDDOP(5) 2.2 to 4.5 2.5 4.6 IDDOP(6) • FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to internal RC oscillation
• 1/1 frequency division mode 4.5 to 5.5 2.5 5.6 IDDOP(7) 2.2 to 4.5 1.7 4.6 IDDOP(8) • FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 32.768kHz
• Internal RC oscillation stopped
• 1/1 frequency division mode 4.5 to 5.5 63 155 μA IDDOP(9) 2.2 to 4.5 39 102 IDDOP(10) • FmCF=12MHz ceramic oscillation mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz
• Internal RC oscillation stopped
• PLL oscillation mode
• 1/1 frequency division mode 4.5 to 5.5 11.0 17.5 mA IDDOP(11) • FmCF=10MHz ceramic oscillation mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 10MHz
• Internal RC oscillation stopped
• PLL oscillation mode
• 1/1 frequency division mode 4.5 to 5.5 10.3 17.0 IDDOP(12) 3.0 to 4.5 5.9 13.0 Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. Continued on next page.

No.A1951-24/31 Continued from preceding page. Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit HALT mode consumption current (Note 7-1) IDDHALT(1) V DD1 =VDD2 =VDD3

• HALT mode
• FmCF=12MHz ceramic mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz
• Internal RC oscillation stopped
• 1/1 frequency division mode 4.5 to 5.5 2.9 4.4 mA IDDHALT(2) • HALT mode
• FmCF=10MHz ceramic oscillator mode
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 10MHz
• Internal RC oscillation stopped
• 1/1 frequency division mode 4.5 to 5.5 2.5 4.2 IDDHALT(3) 3.0 to 4.5 1.3 3.0 IDDHALT(4) • HALT mode
• FmCF=4MHz ceramic oscillator mode
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 4MHz
• Internal RC oscillation stopped
• 1/2 frequency division mode 4.5 to 5.5 0.90 1.6 IDDHALT(5) 2.2 to 4.5 0.40 1.1 IDDHALT(6) • HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to internal RC oscillation
• 1/1 frequency division mode 4.5 to 5.5 0.42 1.25 IDDHALT(7) 2.2 to 4.5 0.20 0.85 IDDHALT(8)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 32.768kHz
• Internal RC oscillation stopped
• 1/1 frequency division mode 4.5 to 5.5 23 90 μA IDDHALT(9) 2.2 to 4.5 10 40 HOLD mode consumption current IDDHOLD(1) V DD1 HOLD mode
• CF1=VDD or open (external clock mode) 4.5 to 5.5 0.05 20 μA IDDHOLD(2) 2.2 to 4.5 0.03 15 HOLDX mode consumption current IDDHOLD(3) HOLDX mode
• CF1=VDD or open (external clock mode)
• FmX'tal=32.768kHz crystal oscillator mode 4.5 to 5.5 15 58 IDDHOLD(4) 2.2 to 4.5 4 35 Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors.

No.A1951-25/31 F-ROM Programming Characteristics at Ta = +10 to +55°C, VSS1=VSS2=VSS3=0V Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD[V] min typ max unit Onboard programming current IDDFW(1) V DD1 • Microcontroller erase current current is excluded. 3.0 to 5.5 5 10 mA Onboard programming time tFW(1) • 128-/1K-byte erase operation 3.0 to 5.5 20 30 ms tFW(2) • 2-byte programming operation 3.0 to 5.5 40 60 μs Power Pin Treatment Conditions 1 (VDD1, VSS1) Connect capacitors that meet the following conditions between the VDD1 and VSS1 pins:

• Connect among the VDD1 and VSS1 pins and the capacitors C1 and C2 with the shortest possible lead wires, of the same length (L1=L1', L2=L2') wherever possible.
• Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1μF or larger.
• The VDD1 and VSS1 traces must be thicker than the other traces. Power Pin Treatment Conditions 2 (VDD(2, 3), VSS(2, 3)) Connect capacitors that meet the following condition between the VDD (2, 3) and VSS (2, 3) pins:
• Connect among the VDD (2, 3) and VSS (2, 3) pins and the capacitor C3 with the shortest possible lead wires, of the same length (L3=L3') wherever possible.
• The capacitance of C3 should be approximately 0.1μF or larger.
• The VDD (2, 3) and VSS (2, 3) traces must be thicker than the other traces. VSS1 VDD1 L1’ L2’ C1 C2 VSS (2, 3) VDD (2, 3) L3’

No.A1951-26/31 Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator Nominal Frequency Vendor Name Resonator Circuit Constant Operating Voltage Range [V] Oscillation Stabilization Time Remarks [pF] [pF] Rf [Ω] Rd2 [Ω] typ [ms] max [ms] 12MHz MURATA CSTCE12M0G52-R0 (10) (10) OPEN 220 2.4 to 5.5 0.02 0.2 C1, C2 integrated type 10MHz CSTCE10M0G52-R0 (10) (10) OPEN 470 2.4 to 5.5 0.02 0.2 C1, C2 integrated type CSTLS10M0G53-B0 (15) (15) OPEN 680 2.6 to 5.5 0.02 0.2 C1, C2 integrated type 8MHz CSTCE8M00G52-R0 (10) (10) OPEN 470 2.3 to 5.5 0.02 0.2 C1, C2 integrated type CSTLS8M00G53-B0 (15) (15) OPEN 1k 2.5 to 5.5 0.02 0.2 C1, C2 integrated type 4MHz integrated type integrated type The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the lower limit level of the operating voltage range (see Figure 4) Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator Nominal Frequency Vendor Name Oscillator Name Circuit Constant Operating Voltage Range [V] Oscillation Stabilization Time Remarks [pF] [pF] Rf2 [Ω] Rd2 [Ω] typ [s] max [s] 32.768kHz EPSON TOYOCOM MC-306 10 10 OPEN 0 2.2 to 5.5 0.4 2.0 Applicable CL value=7.0pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillator circuit is executed plus the time interval that is required for the oscillation to get stabilized after the HOLD mode is released (see Figure 4). Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the oscillation characteristics are affected by their trace pattern.

No.A1951-28/31 Reset Time and Oscillation Stabilization Time HOLD Release and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time Timing Charts tmsX'tal tmsCF Internal RC oscillation CF1, CF2 XT1, XT2 State HOLD HALT Instruction execution HOLD release No HOLD release signal HOLD release signal valid Interrupt operation tmsX'tal tmsCF VDD Reset time Power RESB Internal RC oscillation CF1, CF2 XT1, XT2 Operating mode Unpredictable Reset Initialization instruction execution User instruction execution Operating VDD lower limit

No.A1951-31/31 PS ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s techn ical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC productsfor any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, anddistributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture oft h e part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.