LC87F2416A ONSEMI | Alldatasheet

Document overview

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Technical content

Features

„Flash ROM

  • Capable of On-board-programming with wide range (2.2 to 5.5V) of voltage source.
  • Block-erasable in 128 byte units
  • 16384 × 8 bits (LC87F2416A) „RAM
  • 512 × 9 bits (LC87F2416A) „Minimum bus cycle time
  • 83.3ns (12MHz at VDD = 2.7V to 5.5V)
  • 100ns (10MHz at VDD = 2.2V to 5.5V)
  • 250ns (4MHz at VDD = 1.8V to 5.5V) Note: The bus cycle time here refers to the ROM read speed. „Minimum instruction cycle time
  • 250ns (12MHz at VDD = 2.7V to 5.5V)
  • 300ns (10MHz at VDD = 2.2V to 5.5V)
  • 750ns (4MHz at VDD = 1.8V to 5.5V) CMOS LSI 8-bit Microcontroller 16K-byte Flash ROM / 512-byte RAM / 36-pin QFP36

No.A0782-2/28 „Ports

  • Normal withstand voltage I/O ports Ports I/O direction can be designated in 1 bit units 16 (P1n, P20, P21, P30, P31, P70 to P73) Ports I/O direction can be designated in 4 bit units 8 (P0n)
  • Dedicated oscillator ports/input ports 2 (CF1/XT1, CF2/XT2)
  • Reset pin 1 ( ____ RES)
  • Power pins 3 (V SS1, VSS2, VDD1) „Timers
  • Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register)
  • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + with an 8-bit prescaler 8-bit timer/counter (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
  • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
  • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
  • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts are programmable in 5 different time schemes 3) Base timer does not operate when selecting CF Oscillation circuit. „High-speed clock counter 1) Capable of counting clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Capable of generating real-time output. „SIO
  • SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units)
  • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)

No.A0782-3/28 „UART

  • Full duplex
  • 7/8/9 bit data bits selectable
  • 1 stop bit (2-bit in continuous data transmission)
  • Built-in baudrate generator „AD converter: 12 bits/8 bits × 10 channels
  • 12 bits/8 bits AD converter resolution selectable „PWM: Multifrequency 12-bit PWM × 2 channels „Remote control receiver circuit (sharing pins with P73, INT3, and T0IN)
  • Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) „Clock output function
  • Capable of outputting selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as system clock.
  • Capable of outputting oscillation clock of sub clock. „Watchdog timer
  • External RC watchdog timer
  • Interrupt and reset signals selectable „Interrupts
  • 20 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/T6/T7/PWM4, PWM5 10 0004BH H or L Port 0
  • Priority levels X > H > L
  • Of interrupts of the same level, the one with the smallest vector address takes precedence. „Subroutine stack levels: 256levels (the stack is allocated in RAM.)

No.A0782-4/28 „High-speed multiplication/division instructions

  • 16 bits × 8 bits (5 tCYC execution time)
  • 24 bits × 16 bits (12 tCYC execution time)
  • 16 bits ÷ 8 bits (8 tCYC execution time)
  • 24 bits ÷ 16 bits (12 tCYC execution time) „Oscillation circuits
  • RC oscillation circuit (internal) : For system clock
  • Frequency variable RC oscillation circuit (internal) : For system clock
  • CF oscillation circuit : For system clock, with internal Rf
  • Crystal oscillation circuit : For low-sp eed system clock, with internal Rf 1) CF and crystal oscillation circuit have a shared terminal, and it is software selectable. 2) When reset, CF and Crystal oscillators stop operation. After reset is released, CF oscillator starts operation. „System clock divider function
  • Capable of running with low current consumption. (at a main clock rate of 10MHz). „Internal reset function
  • Power-On-Reset (POR) function 1) POR resets the system when the power supply voltage is applied.
  • Low Voltage Detection reset (LVD) function 1) LVD used with POR resets the system when the supply voltage is applied and when it is lowered. 2) LVD function is selectable from enable/disable and the reset level is selectable from 3 levels (1.90V, 2.25V, 2.50V) by option. „Standby function
  • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt
  • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, and INT4 pins to the specified level (3) Having an interrupt source established at port 0
  • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, and INT4 pins to the specified level (3) Having an interrupt source established at port (4) Having an interrupt source established in the base timer circuit Note: X'tal HOLD mode can be used only when crystal oscillation is selected.

No.A0782-5/28 „Onchip-Debugger

  • Supports software debugging with the IC mounted on the target board.
  • For a small pin package, two-channel Onchip-Debugger port ((DBGP0(P0), DBGP1(P1)) are equipped. „Flash data security
  • Protects from illegal access to data in flash memory. Note: Flash data security cannot guarantee perfect security. „Package form
  • QFP36 (7 × 7): Lead-free type „Development tools
  • Onchip Debugger : TCB87 TypeB + LC87F2416A „Flash ROM programming boards Package Programming boards QFP36 (7×7) W87F24Q ■Flash ROM programmer Maker Model Supported version (Note) Device Single AF9708/AF9709/AF9709B (including product of Ando Electric Co.,Ltd) Revision : After 02.60 AF9723 (Main body) (including product of Ando Electric Co.,Ltd) Flash Support Group, Inc. Gang AF9833 (Unit) (including product of Ando Electric Co.,Ltd) LC87F2416A Our Company SKK Type-B( SANYOFWS) Application Version : 1.03 or later Chip Data Version : 2.03 or later LC87F2416A For information about AF series, please contact the following: Flash Support Group, Inc. TEL: 053-459-1030 E-mail: sales@j-fsg.co.jp „Same package and pin assignment as mask ROM version. 1) LC872400 series options can be set by using flash ROM data. Thus the board used for mass production can be used for debugging and evaluation without modifications. 2) If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as the mask ROM version.

No.A0782-6/28 Package Dimensions unit : mm LQFP36 7x7 / QFP36 CASE 561AV ISSUE A XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data GENERIC MARKING DIAGRAM* *This information is generic. Please refer to device data sheet for actual part marking. XXXXXXXX YMDDD XXXXX = Specific Device Code Y = Year DD = Additional Traceability Data XXXXXXXX YDD 7.0±0.1 12 0.65 (0.9) 0.13 7.0±0.1 9.0±0.2 9.0±0.2 0.3±0.1 0.5±0.2 0.15±0.05 0.10

1.7 MAX

(1.5)0.1±0.1 0~10° (Unit: mm) 8.40 8.40 0.430.65 1.00 SOLDERING FOOTPRINT* NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

No.A0782-7/28 Pin Assignment QFP36(7 × 7) “Lead-free Type” QFP36 NAME QFP36 NAME

1 P73/INT3/T0IN 19 P21/URX/INT4/T1IN

2 RES 20 P30/PWM4/INT5/T1IN

3 I.C. 21 P31/PWM5/INT5/T1IN 4 V SS1 22 N.C.

5 CF1/XT1 23 V SS2

6 CF2/XT2 24 P00/AN0

7 V DD1 25 P01/AN1

8 P10/SO0 26 P02/AN2

9 P11/SI0/SB0 27 P03/AN3

10 P12/SCK0 28 P04/AN4

11 P13/SO1/DBGP12 29 P05/AN5/CKO/DBGP00

12 P14/SI1/SB1/DBGP11 30 P06/AN6/T6O/DBGP01

13 P15/SCK1/DBGP10 31 P07/AN7/T7O/DBGP02

14 N.C. 32 N.C. 15 N.C. 33 N.C.

16 P16/T1PWML 34 P70/INT0/T0LCP/AN8

17 P17/T1PWMH/BUZ 35 P71/INT1/T0HCP/AN9

18 P20/UTX/INT4/T1IN

36 P72/INT2/T0IN

N.C. P31/PWM5/INT5/T1IN P30/PWM4/INT5/T1IN P21/URX/INT4/T1IN P73/INT3/T0IN RES I.C. VSS1 CF1/XT1 CF2/XT2 VDD1 P10/SO0 P11/SI0/SB0 P04/AN4 P05/AN5/CKO/DBGP00 P06/AN6/T6O/DBGP01 P07/AN7/T7O/DBGP02 N.C. N.C. P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P20/UTX/INT4/T1IN P17/T1PWMH/BUZ P16/T1PWML N.C. N.C. P15/SCK1/DBGP10 P14/SI1/SB1/DBGP11 P13/SO1/DBGP12 P12/SCK0 LC87F2416A Top view

No.A0782-8/28 System Block Diagram Interrupt control Standby control IR PLA Bus interface Port 0 Port 1 SIO0 SIO1 Timer 0 Timer 1 Port 3 Port 7 ADC ALU Flash ROM PC ACC B register C register PSW RAR RAM Stack pointer PWM4 Port 2 INT4 Base timer Timer 6 INT0-2 INT3 (Noise filter) Timer 7 On-chip-debugger PWM5 Clock generator CF/ X'tal RC MRC Port 2 Reset control Reset circuit (LVD/POR) WDT RES UART1 Port 3 INT5

No.A0782-9/28 Pin Function Chart Pin Name I/O Description Option VSS1, VSS2 - -power supply pins No VDD1 - +power supply pin No Port 0 P00 to P07 I/O • 8-bit I/O port

  • I/O specifiable in 4 bit units
  • Pull-up resistors can be turned on and off in 4 bit units.
  • HOLD reset input
  • Port 0 interrupt input
  • Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output P00 (AN0) to P07 (AN7): AD converter input P05 (DBGP00) to P07 (DBGP02): On-chip-debugger 0 port Yes Port 1 P10 to P17 I/O • 8-bit I/O port
  • I/O specifiable in 1 bit units
  • Pull-up resistors can be turned on and off in 1 bit units.
  • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output P15 (DBGP10) to P13 (DBGP12): On-chip-debugger 1 port Yes Port 2 • 2-bit I/O port
  • I/O specifiable in 1 bit units
  • Pull-up resistors can be turned on and off in 1 bit units.
  • Pin functions P20: UART transmit P21: UART receive P20 to P21: INT4 input/HOLD reset input/timer 1 event input /timer 0L capture input/timer 0H capture input Interrupt acknowledge type Rising Falling Rising & Falling H level L level P20 to P21 I/O Yes Port 3 • 2-bit I/O port
  • I/O specifiable in 1 bit units
  • Pull-up resistors can be turned on and off in 1 bit units.
  • Pin functions P30:PWM4 output P31:PWM5 output P30 to P31: INT5 input/HOLD reset input/timer 1 event input /timer 0L capture input/timer 0H capture input Interrupt acknowledge type Rising Falling Rising & Falling H level L level P30 to P31 I/O Yes Continued on next page.

No.A0782-10/28 Continued from preceding page. Pin Name I/O Description Option Port 7 • 4-bit I/O port

  • I/O specifiable in 1 bit units
  • Pull-up resistors can be turned on and off in 1 bit units.
  • Pin functions P70: INT0 input/HOLD reset input/timer 0L capture input /watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input /timer 0L capture input P73: INT3 input (with noise filter)/timer 0 event input /timer 0H capture input P70 (AN8), P71 (AN9): AD converter input Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT0 INT1 INT2 INT3 P70 to P73 I/O No RES I/O Reset Input pin and Internal reset output pin No CF1/XT1 Input • Ceramic resonator or 32.768kHz crystal oscillator input pin
  • Pin function General-purpose input port Must be set for General-purpose input port and connected to VSS1 if not to be used. No CF2/XT2 I/O • Ceramic resonator or 32.768kHz crystal oscillator output pin
  • Pin function General-purpose input port Must be set for General-purpose input port and connected to VSS1 if not to be used. No

No.A0782-11/28 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option selected in units of Option type Output type Pull-up resistor

1 CMOS Programmable (Note 1) P00 to P07 1 bit

2 Nch-open drain No

1 CMOS Programmable P10 to P17 1 bit

2 Nch-open drain Programmable

1 CMOS Programmable P20 to P21 1 bit

1 CMOS Programmable P30 to P31 1 bit

P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable Note1: Programmable pull-up resistors and selection of low-impedance-pull-up/high-impedance-pull-up for port 0 are controlled on lower four bits and upper four bits (P00 to P03, P04 to P07). Note: VSS1 and VSS2 should connect to each other and they should also be grounded. Onchip Debugger pin connection requirements Refer to the separate documents, "RD87 Onchip Debugger Installation Manual" and "LC87200series pin connection requirements Manual", for the requirements on Onchip Debugger pin connections.

No.A0782-12/28 1. Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. max. unit Maximum supply voltage VDD MAX V DD1 -0.3 - +6.5 Input voltage V I CF1 -0.3 - V DD+0.3 Input/output voltage VIO Ports 0, 1, 2, 3 Port 7 -0.3 - V DD+0.3 V IOPH(1) Ports 0, 1, 2, 3 CMOS output select Per 1 applicable pin -10 Peak output current IOPH(2) Ports P71 to P73 Per 1 applicable pin -5 IOMH(1) Ports 0, 1, 2, 3 CMOS output select Per 1 applicable pin -7.5 Mean output current (Note 1-1) IOMH(2) Ports P71 to P73 Per 1 applicable pin -3 ΣIOAH(1) Ports P71 to P73 Total of all applicable pins -10 ΣIOAH(2) Ports P10 to P14 Total of all applicable pins -20 ΣIOAH(3) Ports P15 to P17 Ports 0, 2, 3 Total of all applicable pins -20 High level output current Total output current ΣIOAH(4) Ports 0, 1, 2, 3 Total of all applicable pins -25 IOPL(1) Ports P02 to P07 Ports 1, 2, 3 Per 1 applicable pin 20 IOPL(2) Ports P00, P01 Per 1 applicable pin 30 Peak output current IOPL(3) Port 7 Per 1 applicable pin 10 IOML(1) Ports P02 to P07 Ports 1, 2, 3 Per 1 applicable pin 15 IOML(2) Ports P00, P01 Per 1 applicable pin 20 Mean output current (Note 1-1) IOML(3) Port 7 Per 1 applicable pin 7.5 ΣIOAL(1) Port 7 Total of all applicable pins 15 ΣIOAL(2) Ports 0 Total of all applicable pins 40 ΣIOAL(3) Ports P10 to P14 Total of all applicable pins 35 ΣIOAL(4) Ports 1, 2, 3 Total of all applicable pins 40 Low level output current Total output current ΣIOAL(5) Ports 0, 1, 2, 3 Total of all applicable pins 70 mA Pd max(1) Ta=-40 to +85 °C Package only 120Power dissipation Pd max(2) QFP36 Ta=-40 to +85°C Package with thermal resistance board (Note 1-2) 275 mW Operating ambient temperature Topg -40 - +85 Storage ambient temperature Tstg -55 - +125 Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

No.A0782-13/28 2. Allowable Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. max. unit VDD(1) 0.245 μs ≤ tCYC ≤ 200μs 2.7 5.5 VDD(2) 0.294 μs ≤ tCYC ≤ 200μs 2.2 5.5 Operating supply voltage (Note 2-1) VDD(3) VDD1 0.735μs ≤ tCYC ≤ 200μs 1.8 5.5 Memory sustaining supply voltage VHD V DD1 RAM and register contents sustained in HOLD mode. 1.6 VIH(1) Ports 1, 2, 3 P71 to P73 P70 port input /interrupt side 1.8 to 5.5 0.3VDD +0.7 V DD VIH(2) Ports 0 1.8 to 5.5 0.3VDD +0.7 V DD VIH(3) Port 70 watchdog timer side 1.8 to 5.5 0.9V DD V DD High level input voltage VIH(4) CF1, ____ RES 1.8 to 5.5 0.75VDD V DD 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(1) Ports 1, 2, 3 P71 to P73 P70 port input /interrupt side 1.8 to 4.0 V SS 0.2V DD 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(2) Ports 0 1.8 to 4.0 V SS 0.2V DD VIL(3) Port 70 watchdog timer side 1.8 to 5.5 V SS 0.8VDD -1.0 Low level input voltage VIL(4) CF1, ____ RES 1.8 to 5.5 V SS 0.25V DD V 2.7 to 5.5 0.245 200 2.2 to 5.5 0.294 200 Instruction cycle time (Note 2-1) tCYC (Note 2-2) 1.8 to 5.5 0.735 200 μs 2.7 to 5.5 0.1 12• CF2 pin open

  • System clock frequency division ratio = 1/1
  • External system clock duty = 50±5% 1.8 to 5.5 0.1 4 3.0 to 5.5 0.2 24.4 External system clock frequency FEXCF CF1
  • CF2 pin open
  • System clock frequency division ratio = 1/2
  • External system clock duty = 50±5% 2.0 to 5.5 0.1 8 FmCF(1) CF1, CF2 12MHz ceramic oscillation See Fig. 1. 2.7 to 5.5 12 FmCF(2) CF1, CF2 10MHz ceramic oscillation See Fig. 1. 2.2 to 5.5 10 FmCF(3) CF1, CF2 4MHz ceramic oscillation See Fig. 1. 1.8 to 5.5 4 FmMRC Frequency variable RC oscillation source oscillation 2.7 to 5.5 16 MHz Oscillation frequency range (Note 2-3) FsX’tal(1) XT1, XT2 32.768kHz crystal oscillation Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recomme nded Operating Ranges limits mayaffect device reliability.

No.A0782-14/28 3. Electrical Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. max. unit IIH(1) Ports 0, 1, 2, 3 Ports 7 ____ RES Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) 1.8 to 5.5 1 High level input current IIH(2) CF1 V IN=VDD 1.8 to 5.5 15 IIL(1) Ports 0, 1, 2, 3 Ports 7 ____ RES Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) 1.8 to 5.5 -1 Low level input current IIL(2) CF1 V IN=VSS 1.8 to 5.5 -15 VOH(1) I OH=-1mA 4.5 to 5.5 V DD-1 μA VOH(2) I OH=-0.35mA 2.7 to 5.5 V DD-0.4 VOH(3) Ports 0, 1, 2 P71 to P73 IOH=-0.15mA 1.8 to 5.5 V DD-0.4 VOH(4) I OH=-6mA 4.5 to 5.5 V DD-1 VOH(5) I OH=-1.4mA 2.7 to 5.5 V DD-0.4 High level output voltage VOH(6) Port 3 (Note 3-1) IOH=-0.8mA 1.8 to 5.5 V DD-0.4 VOL(1) I OL=10mA 4.5 to 5.5 1.5 VOL(2) I OL=1.4mA 2.7 to 5.5 0.4 VOL(3) Ports 0, 1, 2, 3 IOL=0.8mA 1.8 to 5.5 0.4 VOL(4) I OL=1.4mA 2.7 to 5.5 0.4 VOL(5) Port 7 IOL=0.8mA 1.8 to 5.5 0.4 VOL(6) I OL=25mA 4.5 to 5.5 1.5 VOL(7) I OL=4mA 2.7 to 5.5 0.4 Low level output voltage VOL(8) P00, P01 IOL=2mA 1.8 to 5.5 0.4 V Rpu(1) 4.5 to 5.5 15 35 80 Rpu(2) Ports 0, 1, 2, 3 Port 7 VOH=0.9VDD When Port 0 selected low-impedance pull-up. 1.8 to 4.5 18 50 230 Pull-up resistance Rpu(3) Ports 0 High-impedance pull-up. 1.8 to 5.5 100 210 400 kΩ VHYS(1) 2.7 to 5.5 0.1V DD Hysteresis voltage VHYS(2) RES 1.8 to 2.7 0.07V DD V Pin capacitance CP All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 1.8 to 5.5 10 pF Note 3-1: High level output current on port 3 flows as 4 to 6 times as that of mask ROM version (LC872416A/12A/08A). Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per formance may not be indicated by the Electrical Characteristics if operated under different conditions.

No.A0782-15/28 4. Serial I/O Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = 0V 4-1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. max. unit Frequency tSCK(1) 2 Low level pulse width tSCKL(1) 1 tSCKH(1)

  • See Fig. 5. Input clock High level pulse width tSCKHA(1) SCK0(P12)
  • Continuous data transmission/reception mode
  • See Fig. 5. (Note 4-1-2) 1.8 to 5.5 Frequency tSCK(2) 4/3 tCYC Low level pulse width tSCKL(2) tSCKH(2)
  • CMOS output selected
  • See Fig. 5. tSCK Serial clock Output clock High level pulse width tSCKHA(2) SCK0(P12)
  • Continuous data transmission/reception mode
  • CMOS output selected
  • See Fig. 5. 1.8 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tCYC Data setup time tsDI(1) 0.05 Serial input Data hold time thDI(1) SB0(P11), SI0(P11)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 5. 1.8 to 5.5 0.05 tdD0(1) • Continuous data transmission/reception mode (Note 4-1-3) (1/3)tCYC +0.08 Input clock tdD0(2) • Synchronous 8-bit mode (Note 4-1-3) 1tCYC +0.08 Serial output Output clock Output delay time tdD0(3) SO0(P10), SB0(P11) (Note 4-1-3) 1.8 to 5.5 (1/3)tCYC +0.08 μs Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 5.

No.A0782-16/28 4-2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. max. unit Frequency tSCK(3) 2 Low level pulse width tSCKL(3) 1 Input clock High level pulse width tSCKH(3) SCK1(P15) • See Fig. 5. 1.8 to 5.5 Frequency tSCK(4) 2 tCYC Low level pulse width tSCKL(4) 1/2 Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) • CMOS output selected

  • See Fig. 5. 1.8 to 5.5 tSCK Data setup time tsDI(2) 0.05 Serial input Data hold time thDI(2) SB1(P14), SI1(P14)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 5. 1.8 to 5.5 0.05 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
  • Must be specified with respect to falling edge of SIOCLK.
  • Must be specified as the time to the beginning of output state change in open drain output mode.
  • See Fig. 5. 1.8 to 5.5 (1/3)tCYC +0.08 μs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.

No.A0782-17/28 5. Pulse Input Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. max. unit tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P21), INT5(P30 to P31)

  • Interrupt source flag can be set.
  • Event inputs for timer 0 or 1 are enabled. 1.8 to 5.5 1 tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is 1/1
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 1.8 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is 1/32
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 1.8 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is 1/128
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 1.8 to 5.5 256 tCYC High/low level pulse width tPIL(5) ____ RES • External reset input mode.
  • Resetting is enabled. 1.8 to 5.5 200 μs

No.A0782-18/28 6. AD Converter Characteristics at VSS1 = VSS2 = 0V <12-bit AD Converter Mode / Ta = -40 to +85°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. max. unit Resolution N 2.4 to 5.5 12 bit (Note 6-1) 3.0 to 5.5 ±16Absolute accuracy ET (Note 6-1)

  • Ta=-10 to +50°C 2.4 to 3.6 ±20 LSB 4.0 to 5.5 32 115• See Conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 64 115 Conversion time TCAD
  • See Conversion time calculation formulas. (Note 6-2)
  • Ta=-10 to +50°C 2.4 to 3.6 410 425 μs Analog input voltage range VAIN 2.4 to 5.5 V SS V DD V IAINH VAIN=V DD 2.4 to 5.5 1Analog port input current IAINL AN0(P00) to AN7(P07) AN8(P70) AN9(P71) VAIN=VSS 2.4 to 5.5 -1 μA <8-bit AD Converter Mode / Ta = -40 to +85°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. max. unit Resolution N 2.4 to 5.5 8 bit Absolute accuracy ET (Note 6-1) 2.4 to 5.5 ±1.5 LSB 4.0 to 5.5 20 90• See Conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 40 90 Conversion time TCAD
  • See Conversion time calculation formulas. (Note 6-2) Ta=-10 to +50°C 2.4 to 3.6 250 265 μs Analog input voltage range VAIN 2.4 to 5.5 V SS V DD V IAINH VAIN=V DD 2.4 to 5.5 1Analog port input current IAINL AN0(P00) to AN7(P07) AN8(P70) AN9(P71) VAIN=VSS 2.4 to 5.5 -1 μA Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when:
  • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
  • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. Conversion time calculation formulas : 12-bits AD Converter Mode : TCAD (Conversion time) = ((52/(division ratio))+2) × (1/3) × tCYC 8-bits AD Converter Mode : TCAD (Conversion time) = ((32/(division ratio))+2) × (1/3) × tCYC AD conversion time (TCAD) External oscillation (FmCF) Operating supply voltage range (VDD) System division ratio (SYSDIV) Cycle time (tCYC) AD division ratio (ADDIV) 12bit AD 8bit AD 4.0V to 5.5V 1/1 250ns 1/8 34.8 μs 21.5 μs CF-12MHz 3.0V to 5.5V 1/1 250ns 1/16 69.5 μs 42.8 μs 4.0V to 5.5V 1/1 300ns 1/8 41.8 μs 25.8 μs CF-10MHz 3.0V to 5.5V 1/1 300ns 1/16 83.4 μs 51.4 μs 3.0V to 5.5V 1/1 750ns 1/8 104.5 μs 64.5 μs CF-4MHz 2.4V to 3.6V 1/1 750ns 1/32 416.5 μs 256.5 μs

No.A0782-19/28 7. Power-on reset (POR) Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage min. typ. max. unit 1.55V 1.38 1.55 1.72 1.72V 1.54 1.72 1.90 2.00V 1.81 2.00 2.19 2.37V 2.12 2.37 2.62 POR release voltage PORR • Select from option. (Note 7-1) 2.65V 2.39 2.65 2.91 Detection voltage unknown state POUKS • See Fig. 7. (Note 7-2) 0.7 0.95 V Power supply rise time PORIS • Power supply rise time from 0V to 1.4V. 100 ms Note 7-1: The POR release level can be selected out of 5 levels only when the LVD reset function is disabled. Note 7-2: POR is in an unknown state before transistors start operation. 8. Low voltage detection reset (LVD) Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage min. typ. max. unit 1.90V 1.72 1.90 2.08 2.25V 2.03 2.25 2.47 LVD reset Voltage

  • See Fig. 8. (Note 8-2) LVDET 2.50V 2.26 2.50 2.74 1.90V LVDET ×0.054 2.25V LVDET ×0.062 LVD hysteresys width LVHYS
  • Select from option. (Note 8-1) (Note 8-3) 2.50V LVDET ×0.065 Detection voltage unknown state LVUKS • See Fig. 8. (Note 8-4) 0.7 0.95 V Low voltage detection minimum Width (Reply sensitivity) TLVDW • See Fig. 9. 0.2 ms Note 8-1: The LVD reset level can be selected out of 3 levels only when the LVD reset function is enabled. Note 8-2: LVD reset voltage specification values do not include hysteresis voltage. Note 8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note 8-4: LVD is in an unknown state before transistors start operation.

No.A0782-20/28 9. Consumption Current Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. Max. unit 2.7 to 5.5 8.3 15.1 IDDOP(1) • FmCF=12MHz ceramic oscillation mode

  • System clock set to 12MHz side
  • Internal RC oscillation stopped.
  • Frequency variable RC oscillation stopped.
  • 1/1 frequency division ratio 2.7 to 3.6 4.8 8.7 3.0 to 5.5 9 16.2 IDDOP(2) • CF1=24MHz external clock
  • System clock set to CF1 side
  • Internal RC oscillation stopped.
  • Frequency variable RC oscillation stopped.
  • 1/2 frequency division ratio 3.0 to 3.6 5.2 8.7 2.2 to 5.5 7.3 13.8 IDDOP(3) • FmCF=10MHz ceramic oscillation mode
  • System clock set to 10MHz side
  • Internal RC oscillation stopped.
  • Frequency variable RC oscillation stopped.
  • 1/1 frequency division ratio 2.2 to 3.6 4.3 8.3 1.8 to 5.5 3.6 7.8 IDDOP(4) • FmCF=4 MHz ceramic oscillation mode
  • System clock set to 4MHz side
  • Internal RC oscillation stopped.
  • Frequency variable RC oscillation stopped.
  • 1/1 frequency division ratio 1.8 to 3.6 2.5 4.9 1.8 to 5.5 0.7 2.4 IDDOP(5) • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to internal RC oscillation.
  • Frequency variable RC oscillation stopped.
  • 1/2 frequency division ratio 1.8 to 3.6 0.4 1.2 1.8 to 5.5 1.3 2.8 IDDOP(6) • FsX’tal=32.768kHz crystal oscillation mode
  • Internal RC oscillation stopped.
  • System clock set to 1MHz with Frequency variable RC oscillation
  • 1/2 frequency division ratio 1.8 to 3.6 0.8 1.6 mA 1.8 to 5.5 39 139 IDDOP(7) • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 32.768kHz side
  • Internal RC oscillation stopped.
  • Frequency variable RC oscillation stopped.
  • 1/2 frequency division ratio 1.8 to 3.6 17 66 5.0 39 101 3.3 17 47 Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(8) VDD1
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 32.768kHz side
  • Internal RC oscillation stopped.
  • Frequency variable RC oscillation stopped.
  • 1/2 frequency division ratio
  • Ta=-10 to +50°C 2.5 10 29 μA Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note 9-2: The consumption current values do not include operational current of LVD function if not specified. Continued on next page.

No.A0782-21/28 Continued from preceding page. Specification Parameter Symbol Pin/remarks Conditions VDD[V] min. typ. max. unit 2.7 to 5.5 3.4 6.2 IDDHALT(1) • HALT mode

  • FmCF=12MHz ceramic oscillation mode
  • System clock set to 12MHz side
  • Internal RC oscillation stopped.
  • Frequency variable RC oscillation stopped.
  • 1/1 frequency division ratio 2.7 to 3.6 1.8 3.1 3.0 to 5.5 4.9 8.6 IDDHALT(2) • HALT mode
  • CF1=24MHz external clock
  • System clock set to CF1 side
  • Internal RC oscillation stopped.
  • Frequency variable RC oscillation stopped.
  • 1/2 frequency division ratio 3.0 to 3.6 2.3 3.8 2.2 to 5.5 2.9 5.6 IDDHALT(3) • HALT mode
  • FmCF=10MHz ceramic oscillation mode
  • System clock set to 10MHz side
  • Internal RC oscillation stopped.
  • Frequency variable RC oscillation stopped.
  • 1/1 frequency division ratio 2.2 to 3.6 1.5 2.8 1.8 to 5.5 1.5 3.7 IDDHALT(4) • HALT mode
  • FmCF=4MHz ceramic oscillation mode
  • System clock set to 4MHz side
  • Internal RC oscillation stopped.
  • Frequency variable RC oscillation stopped.
  • 1/1 frequency division ratio 1.8 to 3.6 0.7 1.6 1.8 to 5.5 0.5 1.4 IDDHALT(5) • HALT mode
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to internal RC oscillation
  • Frequency variable RC oscillation stopped.
  • 1/2 frequency division ratio 1.8 to 3.6 0.2 0.6 IDDHALT(6) • HALT mode
  • FsX’tal=32.768kHz crystal oscillation mode
  • Internal RC oscillation stopped.
  • System clock set to 1MHz with Frequency variable RC oscillation
  • 1/2 frequency division ratio mA 1.8 to 5.5 25 112 HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(7) VDD1
  • HALT mode
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 32.768kHz side
  • Internal RC oscillation stopped
  • Frequency variable RC oscillation stopped.
  • 1/2 frequency division ratio 1.8 to 3.6 8.5 56 μA Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note 9-2: The consumption current values do not include operational current of LVD function if not specified. Continued on next page.

No.A0782-22/28 Continued from preceding page. Specification Parameter Symbol Pin/remarks Conditions VDD[V] min. typ. max. unit 5.0 25 69 3.3 8.5 29 HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(8) • HALT mode

  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 32.768kHz side
  • Internal RC oscillation stopped
  • Frequency variable RC oscillation stopped.
  • 1/2 frequency division ratio
  • Ta=-10 to +50°C 2.5 4.2 15 1.8 to 5.5 0.04 30IDDHOLD(1) HOLD mode
  • CF1=VDD or open (External clock mode) 1.8 to 3.6 0.02 21 5.0 0.04 2.3 3.3 0.02 1.5 IDDHOLD(2) HOLD mode
  • CF1=VDD or open (External clock mode)
  • Ta=-10 to 50°C 2.5 0.017 1.2 1.8 to 5.5 2.2 34IDDHOLD(3) HOLD mode
  • CF1=VDD or open (External clock mode)
  • LVD option selected 1.8 to 3.6 1.7 24 5.0 2.2 5.4 3.3 1.7 3.8 HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(4) HOLD mode
  • CF1=VDD or open (External clock mode)
  • Ta=-10 to 50°C
  • LVD option selected 2.5 1.5 3.3 1.8 to 5.5 22 106IDDHOLD(5) Timer HOLD mode
  • FsX’tal=32.768kHz crystal oscillation mode 1.8 to 3.6 7.5 45 5.0 22 62 3.3 7.5 23 Timer HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(6) VDD1 Timer HOLD mode
  • FsX’tal=32.768kHz crystal oscillation mode
  • Ta=-10 to 50°C 2.5 2.9 12 μA Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note 9-2: The consumption current values do not include operational current of LVD function if not specified.

No.A0782-23/28 10. F-ROM Programming Characteristics at Ta = +10 to +55°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. max. unit Onboard programming current IDDFW V DD1 • Only current of the Flash block. 2.2 to 5.5 5 10 mA tFW(1) • Erasing time 20 30 ms Programming time tFW(2)

  • Programming time 2.2 to 5.5 40 60 μs 11. UART (Full Duplex) Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min. typ. max. unit Transfer rate UBR P20, P21 1.8 to 5.5 16/3 8192/3 tCYC Data length : 7/8/9 bits (LSB first) Stop bits : 1 bit(2-bit in continuous data transmission) Parity bits : None Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H) Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H) Transmit data (LSB first) Start of transmission End of transmission UBR Start bit Stop bit Receive data (LSB first) UBR Start of reception End of reception

No.A0782-25/28 Figure 3 Oscillation Stabilization Times Power supply RES Internal RC oscillation CF1, CF2 Operating mode Reset time Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time Internal RC oscillation CF1, CF2 State HOLD reset signal HOLD reset signal absent HOLD reset signal valid tmsCF/tmsX’tal HOLD HALT VDD Operating VDD lower limit HOLD Reset Signal and Oscillation Stabilization Time tmsCF/tmsX’tal

PS No.A0782-28/28 Figure 9 Low voltage detection minimum width (Example of momentary power loss / Voltage variation waveform)

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Device Package Shipping (Qty / Packing) LC87F2416AU-EB-2E QFP36 (Pb-Free) 1250 / Tray JEDEC VDD LVD reset voltage TLVDW LVD release voltage LVDET-0.5V VSS ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A lis ting of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended tosupport or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject t oa l l applicable copyright laws and is not for resale in any manner.