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Technical content

Features

■Flash ROM

  • 65536×8 bits
  • Capable of on-board programming with a wide range of supply voltage from 3.0 to 5.5V
  • Block-erasable in 128-byte units
  • Data written in 2-byte units ■RAM
  • 8192×9 bits ■Package Form
  • SQFP48 (7×7): Lead-/halogen-free product ■Bus Cycle Time
  • 83.3ns (when CF=12MHz) Note: The bus cycle time here refers to the ROM read speed. ■Minimum Instruction Cycle Time (tCYC)
  • 250ns (when CF=12MHz) CMOS IC 8-bit Microcontroller with USB-host Controller 64K-byte Flash ROM / 8K-byte RAM / 48-pin SQFP48(7X7) SQFP48(7X7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5)0.1 1.7max 0.180.5 (0.75) 11 2 2536

ORDERING INFORMATION

See detailed ordering and shipping information on page 35 of this data sheet. * This product is licensed from Silicon Storage Technology, Inc. (USA).

No.A2197-2/35 ■Ports

  • I/O ports Ports whose input/output can be specified in 1-bit units: 34 (P00 to P07, P10 to P17, P20 to P25, P30 to P34, P70 to P73, PWM0, PWM1, XT2)
  • USB ports 4 (UHAD+, UHAD–, UHBD+, UHBD–)
  • Dedicated oscillator ports 2 (CF1, CF2)
  • Input-only port (also used for the oscillator) 1 (XT1)
  • Reset pin 1 ( RES)
  • Power supply pins 6 (V SS1 to 3, VDD1 to 3) ■Timers
  • Timer 0: 16-bit timer/counter with 2 capture registers Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers)
  • Timer 1: 16-bit timer/counter that supports PWM/toggle output Mode 0: 8-bit timer with an 8-bit prescaler (with toggle output) + 8-bit timer/counter with an 8-bit prescaler (with toggle output) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle output) (Toggle output also possible from low-order 8 bits.) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle output) (Low-order 8 bits can be used as a PWM output.)
  • Timer 4: 8-bit timer with a 6-bit prescaler
  • Timer 5: 8-bit timer with a 6-bit prescaler
  • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
  • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
  • Base timer 1) The clock can be selected from among a subclock (32.768kHz crystal oscillator), low-speed RC oscillator clock, system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes. ■Serial Interfaces
  • SIO0: Synchronous serial interface 1) LSB first/MSB first selectable 2) Transfer clock cycle: 4/3 to 512/3 tCYC 3) Continuous automatic data transmission (1 to 256 bits can be specified in 1-bit units) (Suspension and resumption of data transfer possible in 1-byte units)
  • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clock) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrate) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clock) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
  • SIO4: Synchronous serial interface 1) LSB first/MSB first selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Continuous automatic data transmission (1 to 8192 bytes can be specified in 1-byte units) (Suspension and resumption of data transmission possible in 1-byte units or in word units) 4) Clock polarity can be selected. 5) CRC16 calculator circuit built- in
  • SMIIC0: Single-master I 2C/8-bit synchronous SIO Mode 0: Communication in single-master mode. Mode 1: 8-bit synchronous serial I/O (data MSB first)

No.A2197-3/35 ■Full Duplex UART 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Parity bits: None/even/odd selectable (for 8-bit data only) 4) Baudrate: 16/3 to 8192/3 tCYC ■AD Converter: 12 bits × 12 channels ■PWM: Variable frequency 12-bit PWM × 2 channels ■Infrared Remote Control Receiver Circuit 1) Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is selected as the reference clock) 2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding. 3) X'tal HOLD mode release function ■USB Interface (host control function) × 2 ports 1) Supports full-speed (12Mbps) and low-speed (1.5Mbps) specifications. 2) Supports four transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer). ■Audio Interface 1) Sampling frequencies (fs): 8kHz/11.025kHz/12kHz/16kHz/22.05kHz/24kHz/32kHz/44.1kHz/48kHz 2) Master clock: 256fs/384fs 3) Bit clock: 48fs/64fs 4) Data bit length: 16bits/18bits/20bits/24bits 5) LSB first/MSB first selectable. 6) Left justified/right justified/I2S format selectable ■Watchdog Timer

  • External RC time constant type 1) Interrupt generation/reset generation selectable 2) Operation in HALT/HOLD mode can be selected from “continue operation” and “suspend operation.”
  • Internal timer type 1) Capable of generating a internal reset signal on an overflow of the timer running on the low-speed RC oscillator clock, or subclock. 2) Operation in HALT/HOLD mode can be selected from among “continue count operation,” “suspend operation,” and “retain the count value.” ■Clock Output Function 1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as the system clock. 2) Can output the source oscillator clock for the subclock.

No.A2197-4/35 ■Interrupts

  • 44 sources, 10 vectors 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt request of the level equal to or lower than the current interrupt level is not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the lowest vector address is given priority. No. Vector Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4/UHC-A bus active/UHC-B bus active/remote control receive 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H/INT6/UHC-A device connected, disconnected, resumed 6 0002BH H or L T1L/T1H/INT7/AIF start/SMIIC0/UHC-B device connected, disconnected, resumed 7 00033H H or L SIO0/UART1 reception completed 8 0003BH H or L SIO1/SIO4/UART1 buffer em pty/UART1 transmission completed/AIF end 9 00043H H or L ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC-STALL 10 0004BH H or L Port 0/PWM0/PWM1/T4/T5/UHC-SOF
  • Priority levels X > H > L
  • When interrupts of the same level occur at the same time, the interrupt with the lowest vector address is given priority. ■Subroutine Stack Levels: Up to 4096 levels (The stack is allocated in RAM.) ■High-speed Multiplication/Division Instructions
  • 16 bits × 8 bits (5 tCYC execution time)
  • 24 bits × 16 bits (12 tCYC execution time)
  • 16 bits ÷ 8 bits (8 tCYC execution time)
  • 24 bits ÷ 16 bits (12 tCYC execution time) ■Oscillator Circuit and PLL
  • Medium-speed RC oscillator circuit (internal): For system clock (approx. 1MHz)
  • Low-speed RC oscillator circuit (internal): For system clock, timer, and watchdog timer (approx. 30kHz)
  • CF oscillator circuit: For system clock
  • Crystal oscillator circuit: For system clock and time-of-day clock
  • PLL circuit (internal): For USB interface (s ee Fig. 5) and audio interface (see Fig. 6) ■Internal Reset Functions
  • Power-on reset (POR) function 1) POR is activated at power-on. by setting options.
  • Low voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a threshold level. 2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, and 4.28V) can be selected by setting options.

No.A2197-5/35 ■Standby Function

  • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillators do not stop automatically. 2) There are three ways of releasing HOLD mode. (1) Setting the reset pin to a low level. (2) Generating a reset signal by watchdog timer or low-voltage detection (3) Occurrence of an interrupt
  • HOLD mode: Suspends instruction execution and operation of the peripheral circuits. 1) The PLL, CF, RC and crystal oscillators automatically stop operation. Note: Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in standby mode is also controlled. 2) There are five ways of releasing HOLD mode. (1) Setting the reset pin to a low level (2) Generating a reset signal by the watchdog timer or low-voltage detection (3) Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins * INT0 and INT1 HOLD mode release is available only when level detection is configured. (4) Establishing an interrupt source at port 0 (5) Establishing an bus active interrupt source in the USB host control circuit
  • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer and infrared remote control receiver circuit. 1) The PLL, CF and RC oscillators automatically stop operation. Note: Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in standby mode is also controlled. Note: The low-speed RC oscillator retains the state that is established on entry into X'tal HOLD mode if the base timer is running with the low-speed RC oscillator selected as the base timer input clock source. 2) The state of crystal oscillator established when the X'tal HOLD mode is entered is retained. 3) There are seven ways of releasing X'tal HOLD mode. (1) Setting the reset pin to a low level (2) Generating a reset signal by the watchdog timer or low-voltage detection (3) Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins * INT0 and INT1 X'tal HOLD mode release is available only when level detection is configured. (4) Establishing an interrupt source at port 0 (5) Establishing an interrupt source in the base timer circuit (6) Establishing an interrupt source in the infrared remote control receiver circuit (7) Establishing an bus active interrupt source in the USB host control circuit ■Development Tools
  • On-chip debugger: TCB87–Type B + LC87F1K64A or TCB87–Type C (3-wire communication cable) + LC87F1K64A ■Flash ROM Programming Board Package Programming Board SQFP48 (7×7) W87F55256SQ

No.A2197-6/35 ■Flash ROM Programmer Maker Model Supported Version Device Flash Support Group Company (FSG) Single AF9709C Rev.03.32 and later 87F064JU AF9101/AF9103 (main unit) (FSG model) Flash Support Group Company (FSG) Our company (Note 1) Onboard single/ganged SIB87 Type C (interface driver) (Our company model) (Note 2) LC87F1K64A Single/ganged SKK/SKK Type C (SANYO FWS) Our company Onboard single/ganged SKK-DBG Type C (SANYO FWS) Application version 1.07 and later Chip data version 2.39 and later LC87F1K64 (Further information on the AF series) Flash Support Group Company (TOA ELECTRONICS, Inc.) Phone: 053-459-1050 E-mail: sales@j- fsg.co.jp Note 1: PC-less standalone onboard programming is possible using the FSG onboard programmer (AF9101/AF9103) and the serial interface driver (SIB87 Type C) provided by Our company in pair. Note 2: Dedicated programming device and program are required depending on the programming conditions. Contact Our company or FSG if you have any questions or difficulties regarding this matter.

No.A2197-7/35 Package Dimensions unit : mm (typ) 3163B Pin Assignment SQFP48 (7×7) (Lead-/halogen-free product) SQFP48(7X7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5)0.1 1.7max 0.180.5 (0.75) 11 2 2536 UHBD+ UHBD- P25/INT5 P24/INT5/INT7/SCK4 P23/INT4/SI4 P22/INT4/SO4 P21/INT4 P20/INT4/INT6 P07/AN7/T7O/LRCK P06/AN6/T6O/BCLK P05/AN5/CKO/SDAT P04/AN4/DBGP2 P73/INT3/T0IN/RMIN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1/SM0CK1 UHAD- UHAD+ VDD3 VSS3 P34/UFILT P33/AFILT P32 P31/URX1 P30/UTX1 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1 P00/AN0 VSS2 VDD2 PWM0/MCLKO PWM1/MCLKI P17/T1PWMH/BUZ/SM0CK0 P16/T1PWML/SM0DA0 P15/SCK1/SM0DO P14/SI1/SB1/SM0DA1 LC87F1K64A Top view

No.A2197-8/35 SQFP48 NAME SQFP48 NAME

1 P73/INT3/T0IN/RMIN 25 P04/AN4/DBGP2

2 RES 26 P05/AN5/CKO/SDAT

3 XT1/AN10 27 P06/AN6/T6O/BCLK

4 XT2/AN11 28 P07/AN7/T7O/LRCK

5 V SS1 29 P20/INT4/INT6

6 CF1 30 P21/INT4

7 CF2 31 P22/INT4/SO4

8 V DD1 32 P23/INT4/SI4

9 P10/SO0 33 P24/INT5/INT7/SCK4

10 P11/SI0/SB0 34 P25/INT5

11 P12/SCK0 35 UHBD-

12 P13/SO1/SM0CK1 36 UHBD+

13 P14/SI1/SB1/SM0DA1 37 UHAD-

14 P15/SCK1/SM0DO 38 UHAD+

15 P16/T1PWML/SM0DA0 39 V DD3

16 P17/T1PWMH/BUZ/SM0CK0 40 V SS3

17 PWM1/MCLKI 41 P34/UFILT

18 PWM0/MCLKO 42 P33/AFILT

19 V DD2 43 P32

20 V SS2 44 P31/URX1

21 P00/AN0 45 P30/UTX1

22 P01/AN1 46 P70/INT0/T0LCP/AN8

23 P02/AN2/DBGP0 47 P71/INT1/T0HCP/AN9

24 P03/AN3/DBGP1

48 P72/INT2/T0IN

No.A2197-9/35 System Block Diagram Interrupt control ROM Standby control Clock generator CF X’tal RC IR PLA PC Bus interface Port 0 Port 1 ACC B register C register ALU PSW RAR RAM Stack pointer Watchdog timer Base timer PWM1 INT0 to INT7 Noise filter SIO0 Port 2 USB PLL Port 7 Port 3 ADC SIO1 Timer 0 Timer 1 PWM0 Timer 6 Timer 7 UART1 On-chip debugger USB host Timer 4 Timer 5 SIO4 Audio interface IFR control receiver circuit WDT Reset control Reset circuit (LVD/POR) RES SMIIC0

No.A2197-10/35 Pin Description Pin Name I/O Description Option VSS1, VSS2, VSS3 - -power supply No VDD1, VDD2 - +power supply No VDD3 - USB reference voltage Yes Port 0 P00 to P07 I/O • 8-bit I/O port

  • I/O can be specified in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • HOLD release input
  • Port 0 interrupt input
  • Pin functions AD converter input port: AN0 to AN7 (P00 to P07) On-chip debugger pins: DBGP0 to DBGP2 (P02 to P04) P05: System clock output / audio interface SDAT I/O P06: Timer 6 toggle output / audio interface BCLK I/O P07: Timer 7 toggle output / audio interface LRCK I/O Yes Port 1 P10 to P17 I/O • 8-bit I/O port
  • I/O can be specified in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P10: SIO0 data output P11: SIO0 data input / bus I/O P12: SIO0 clock I/O P13: SIO1 data output / SMIIC0 clock I/O P14: SIO1 data input / bus I/O / SMIIC0 bus I/O / data input P15: SIO1 clock I/O / SMIIC0 data output (used in 3-wire SIO mode) P16: Timer 1 PWML output / SMIIC0 bus I/O / data input P17: Timer 1 PWMH output / buzzer output / SMIIC0 clock I/O Yes Port 2 • 6-bit I/O port
  • I/O can be specified in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P20 to P23: INT4 input / HOLD release input / timer 1 event input / timer 0L capture input / timer 0H capture input P24 to P25: INT5 input / HOLD release input / timer 1 event input / timer 0L capture input / timer 0H capture input P20: INT6 input / timer 0L capture 1 input P22: SIO4 data I/O P23: SIO4 data I/O P24: INT7 input / timer 0H capture 1 input / SIO4 clock I/O Interrupt acknowledge types Rising Falling Rising & Falling H Level L Level INT4 Enable Enable Enable Disable Disable INT5 Enable Enable Enable Disable Disable INT6 Enable Enable Enable Disable Disable INT7 Enable Enable Enable Disable Disable P20 to P25 I/O Yes Port 3 P30 to P34 I/O • 5-bit I/O port
  • I/O can be specified in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P30: UART1 transmit P31: UART1 receive P33: Connected to audio interface PLL filter circuit (see Fig. 6). P34: Connected to USB interface PLL filter circuit (see Fig. 5). Yes Continued on next page.

No.A2197-11/35 Continued from preceding page. Pin Name I/O Description Option Port 7 • 4-bit I/O port

  • I/O can be specified in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P70: INT0 input / HOLD release input / timer 0L capture input / watchdog timer output P71: INT1 input / HOLD release input / timer 0H capture input P72: INT2 input / HOLD release input / timer 0 event input / timer 0L capture input / high-speed clock counter input P73: INT3 input (input with noise filter) / timer 0 event input / timer 0H capture input / infrared remote control receiver input AD converter input port: AN8 (P70), AN9 (P71) Interrupt acknowledge types Rising Falling Rising & Falling H Level L Level INT0 Enable Enable Disable Enable Enable INT1 Enable Enable Disable Enable Enable INT2 Enable Enable Enable Disable Disable INT3 Enable Enable Enable Disable Disable P70 to P73 I/O No PWM0 PWM1 I/O PWM0 and PWM1 output port General-purpose input port
  • Pin functions PWM0: Audio interface master clock output PWM1: Audio interface master clock input No UHAD- UHAD+ I/O USB-A port data I/O pin / general-purpose I/O port No UHBD- UHBD+ I/O USB-B port data I/O pin / general-purpose I/O port No RES I/O External reset input / internal reset output No XT1 I • 32.768kHz crystal resonator input
  • Pin functions General-purpose input port AD converter input port: AN10 No XT2 I/O • 32.768kHz crystal resonator output
  • Pin functions General-purpose I/O port AD converter input port: AN11 No CF1 I Ceramic/crystal resonator input No CF2 O Ceramic/crystal resonator output No

No.A2197-12/35 On-chip Debugger Pin Treatment For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87 On-chip Debugger Installation Manual." Recommended Unused Pin Treatment Recommended Unused Pin Treatment Pin Name Board Software P00 to P03, P05 to P07 Open Set output low. P04 Pull-down with a 100k Ω resistor. - P10 to P17 Open Set output low. P20 to P25 Open Set output low. P30 to P34 Open Set output low. P70 to P73 Open Set output low. PWM0, PWM1 Open Set output low. UHAD+, UHAD- Open Set output low. UHBD+, UHBD- Open Set output low. XT1 Pull-down with a resistor of 100k Ω or lower. - XT2 Open Set output low. Note: Since P34 is multiplexed with UFILT, it must be configured for input when the USB function is to be used. Since P33 is multiplexed with AFILT, it must be configured for input when the audio interface PLL circuit is to be used. Port Output Types The table below lists the type of port output and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in output mode. Port Name Option Selected in Units of Option Type Output Type Pull-up Resistor

1 CMOS Programmable P00 to P07

2 N-channel open drain Programmable

P70 - No N-channel open drain Programmable P71 to P73 - No CMOS Programmable PWM0, PWM1 - No CMOS No UHAD+, UHAD- UHBD+, UHBD- - No CMOS No XT1 - No Input only No XT2 - No 32.768kHz crystal resonator output (N-channel open drain when in general-purpose output mode) No

No.A2197-13/35 User Option Table Option Name Option to be Applied on Flash-ROM Version Option Selected in Units of Option Selection CMOS P00 to P07 ○ 1 bit N-channel open drain CMOS P10 to P17 ○ 1 bit N-channel open drain CMOS P20 to P25 ○ 1 bit N-channel open drain CMOS Port output type P30 to P34 ○ 1 bit N-channel open drain 00000h Program start address - ○ - 0FE00h Use USB regulator ○ - Non-use Use USB regulator (HOLD mode) ○ - Non-use Use USB regulator USB regulator (HALT mode) ○ - Non-use Enable Main clock 8MHz selection - ○ - Disable Enable: Use Detection function ○ - Disable: Non-use Low-voltage detection reset function Detection level ○ - 7 levels Power-on reset function Power-on reset level ○ - 8 levels

No.A2197-14/35 USB Reference Power Option When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be switched by selecting an option. The procedure for making the option selection is described below. (1) (2) (3) (4) USB regulator Use Use Use Non-use USB regulator at HOLD mode Use Non-use N on-use Non-use Option settings USB regulator at HALT mode Use Non-use Use Non-use Normal mode Active Active Active Inactive HOLD mode Active Inactive Inactive Inactive Reference voltage circuit state HALT mode Active Inactive Active Inactive

  • When the USB reference voltage circuit is made inactive, the level of the reference voltage for the USB port output is equal to VDD1.
  • Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
  • When the reference voltage circuit is activated, the current drain increases by approximately 100μA compared with when the reference voltage circuit is inactive. Example 1: VDD1=VDD2=3.3V
  • Inactivating the reference voltage circuit (selection (4)).
  • Connecting VDD3 to VDD1 and VDD2. Example 2: VDD1=VDD2=5.0V
  • Activating the reference voltage circuit (selection (1)).
  • Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS. VSS1 VSS2V SS3 VDD1 VDD2 VDD3 Power supply 3.3V IC UHAD+ /UHBD+ UHAD- /UHBD- UFILT 15kΩ To USB connector 33Ω 5pF 2.2μF 2.2μF VSS1 VSS2 V SS3 VDD1 VDD2 VDD3 Power supply IC UFILT 2.2μF 15kΩ To USB connector 33Ω 5pF 2.2μF 0.1μF UHAD+ /UHBD+ UHAD- /UHBD- (Note: Do not apply the voltage of more than 3.6V to UHAD+, UHAD-, UHBD+ and UHBD- when the reference voltage circuit is active.

No.A2197-15/35 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Maximum supply voltage VDD max V DD1, VDD2, VDD3 V DD1=VDD2=VDD3 -0.3 +6.5 Input voltage V I(1) XT1, CF1, RES -0.3 V DD+0.3 Input/output voltage VIO(1) Ports 0, 1, 2, 3, 7 PWM0, PWM1 XT2 -0.3 V DD+0.3 V IOPH(1) Ports 0, 1, 2 • When CMOS output type is selected

  • Per 1 applicable pin -10 IOPH(2) PWM0, PWM1 • Per 1 applicable pin -20 Peak output current IOPH(3) Port 3 P71 to P73
  • When CMOS output type is selected
  • Per 1 applicable pin IOMH(1) Ports 0, 1, 2 • When CMOS output type is selected
  • Per 1 applicable pin -7.5 IOMH(2) PWM0, PWM1 Per 1 applicable pin -15 Average output current (Note 1-1) IOMH(3) Port 3 P71 to P73
  • When CMOS output type is selected
  • Per 1 applicable pin ΣIOAH(1) Ports 0, 2 To tal current of all applicable pins -25 ΣIOAH(2) Port 1 PWM0, PWM1 Total current of all applicable pins -25 ΣIOAH(3) Ports 0, 1, 2 PWM0, PWM1 Total current of all applicable pins -45 ΣIOAH(4) Port 3 P71 to P73 Total current of all applicable pins -10 High level output current Total output current ΣIOAH(5) UHAD+, UHAD- UHBD+, UHBD- Total current of all applicable pins -50 IOPL(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin IOPL(2) P00, P01 Per 1 applicable pin 30 Peak output current IOPL(3) Ports 3, 7 XT2 Per 1 applicable pin 10 IOML(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin IOML(2) P00, P01 Per 1 applicable pin 20 Average output current (Note 1-1) IOML(3) Ports 3, 7 XT2 Per 1 applicable pin 7.5 ΣIOAL(1) Ports 0, 2 Total current of all applicable pins ΣIOAL(2) Port 1 PWM0, PWM1 Total current of all applicable pins ΣIOAL(3) Ports 0, 1, 2 PWM0, PWM1 Total current of all applicable pins ΣIOAL(4) Ports 3, 7 XT2 Total current of all applicable pins Low level output current Total output current ΣIOAL(5) UHAD+, UHAD- UHBD+, UHBD- Total current of all applicable pins mA Allowable power dissipation Pd max SQFP48(7 ×7) Ta=-40 to +85°C 140 mW Operating ambient Temperature Topr -40 +85 Storage ambient temperature Tstg -55 +125 Note 1-1: The average output current is an average of current values measured over 100ms intervals. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Oper ating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No.A2197-16/35 Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit 0.245μs ≤ tCYC ≤ 200μs 3.0 5.5 0.245μs ≤ tCYC ≤ 0.383μs USB circuit active. 3.0 5.5 Operating supply voltage (Note 2-1) VDD(1) V DD1=VDD2=VDD3 0.490μs ≤ tCYC ≤ 200μs Except for onboard programming mode 2.7 5.5 Memory retention supply voltage VHD V DD1=VDD2=VDD3 RAM and register contents are retained in HOLD mode 2.0 5.5 VIH(1) Ports 0, 1, 2, 3, 7 PWM0, PWM1 2.7 to 5.5 0.3VDD +0.7 V DD High level input voltage VIH(2) XT1, XT2, CF1, RES 2.7 to 5.5 0.75V DD V DD VIL(1) 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(2) Ports 1, 2, 3, 7 2.7 to 4.0 V SS 0.2V DD VIL(3) 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(4) Port 0 PWM0, PWM1 2.7 to 4.0 V SS 0.2V DD Low level input voltage VIL(5) XT1, XT2, CF1, RES 2.7 to 5.5 V SS 0.25V DD V 3.0 to 5.5 0.245 200 Instruction cycle time (Note 2-2) tCYC Except for onboard programming mode 2.7 to 5.5 0.490 200 μs

  • CF2 pin open
  • System clock frequency division ratio =1/1
  • External system clock duty =50±5% 3.0 to 5.5 0.1 12 External system clock frequency FEXCF(1) CF1
  • CF2 pin open
  • System clock frequency division ratio =1/1
  • External system clock duty =50±5% 2.7 to 5.5 0.1 6 MHz FmCF CF1, CF2 12MHz ceramic oscillation mode See Fig. 1. 3.0 to 5.5 12 FmRC Internal medium-speed RC MHz FmSRC Internal low-speed RC oscillation 2.7 to 5.5 15 30 60 Oscillation frequency range (Note 2-3) FsX'tal XT1, XT2 32.768kHz crystal oscillation mode See Fig. 2. 2.7 to 5.5 32.768 kHz Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants.

No.A2197-17/35 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit IIH(1) Ports 0, 1, 2, 3, 7 RES PWM0, PWM1 Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) 2.7 to 5.5 1 IIH(2) XT1, XT2 Input port configuration VIN=VDD 2.7 to 5.5 1 High level input current IIH(3) CF1 V IN=VDD 2.7 to 5.5 15 IIL(1) Ports 0, 1, 2, 3, 7 RES PWM0, PWM1 Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) 2.7 to 5.5 -1 IIL(2) XT1, XT2 Input port configuration VIN=VSS 2.7 to 5.5 -1 Low level input current IIL(3) CF1 V IN=VSS 2.7 to 5.5 -15 μA VOH(1) I OH=-1mA 4.5 to 5.5 V DD-1 VOH(2) I OH=-0.4mA 3.0 to 5.5 V DD-0.4 VOH(3) Ports 0, 1, 2, 3 P71 to P73 IOH=-0.2mA 2.7 to 5.5 V DD-0.4 VOH(4) I OH=-10mA 4.5 to 5.5 V DD-1.5 VOH(5) I OH=-1.6mA 3.0 to 5.5 V DD-0.4 High level output voltage VOH(6) PWM0, PWM1 P05 to P07 (Note 3-1) IOH=-1mA 2.7 to 5.5 V DD-0.4 VOL(1) I OL=30mA 4.5 to 5.5 1.5 VOL(2) I OL=5mA 3.0 to 5.5 0.4 VOL(3) P00, P01 IOL=2.5mA 2.7 to 5.5 0.4 VOL(4) I OL=10mA 4.5 to 5.5 1.5 VOL(5) I OL=1.6mA 3.0 to 5.5 0.4 VOL(6) Ports 0, 1, 2 PWM0, PWM1 XT2 IOL=1mA 2.7 to 5.5 0.4 VOL(7) I OL=1.6mA 3.0 to 5.5 0.4 Low level output voltage VOL(8) Ports 3, 7 IOL=1mA 2.7 to 5.5 0.4 V Rpu(1) 4.5 to 5.5 15 35 80Pull-up resistance Rpu(2) Ports 0, 1, 2, 3, 7 V OH=0.9VDD 2.7 to 4.5 18 50 150 kΩ Hysteresis voltage VHYS RES Ports 1, 2, 3, 7 2.7 to 5.5 0.1V DD V Pin capacitance CP All pins For pins other than those under test: VIN=VSS f=1MHz Ta=25°C 2.7 to 5.5 10 pF Note 3-1: When the CKO system clock output function (P05) or the audio interface output function (P05 to P07) is used.

No.A2197-18/35 Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(1) 2 Low level pulse width tSCKL(1) 1 tSCKH(1) See Fig. 9. tSCKHA(1a) • Continuous data transmission/ reception mode

  • USB, AIF, SIO4 not used at the same time.
  • See Fig. 9.
  • (Note 4-1-2) tSCKHA(1b) • Continuous data transmission/ reception mode
  • USB used at the same time
  • AIF, SIO4 not used at the same time.
  • See Fig. 9.
  • (Note 4-1-2) Input clock High level pulse width tSCKHA(1c) SCK0(P12)
  • Continuous data transmission/ reception mode
  • USB, AIF, SIO4 used at the same time.
  • See Fig. 9.
  • (Note 4-1-2) 2.7 to 5.5 Frequency tSCK(2) 4/3 tCYC Low level pulse width tSCKL(2) tSCKH(2)
  • When CMOS output type is selected.
  • See Fig. 9. tSCK tSCKHA(2a) • Continuous data transmission/ reception mode
  • USB, AIF, SIO4 not used at the same time.
  • When CMOS output type is selected.
  • See Fig. 9. tSCKH(2) +2tCYC tSCKH(2) (10/3)tCYC tSCKHA(2b) • Continuous data transmission/ reception mode
  • USB used at the same time
  • AIF, SIO4 not used at the same time.
  • When CMOS output type is selected.
  • See Fig. 9. tSCKH(2) +2tCYC tSCKH(2) (19/3)tCYC Serial clock Output clock High level pulse width tSCKHA(2c) SCK0(P12)
  • Continuous data transmission/ reception mode
  • USB, AIF, SIO4 used at the same time
  • When CMOS output type is selected.
  • See Fig. 9. 2.7 to 5.5 tSCKH(2) +2tCYC tSCKH(2) (25/3)tCYC tCYC Note 4-1-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-1-2: In an application where the serial clock input is to be used in continuous data transmission/reception mode, the time from SI0RUN being set when serial clock is high to the falling edge of the first serial clock must be longer than tSCKHA. Continued on next page.

No.A2197-19/35 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Data setup time tsDI(1) 0.03 Serial input Data hold time thDI(1) SB0(P11), SI0(P11)

  • Must be specified with respect to rising edge of SIOCLK
  • See Fig. 9. 2.7 to 5.5 0.03 tdDO(1) • Continuous data transmission/ reception mode
  • (Note 4-1-3) (1/3)tCYC +0.05 Input clock tdDO(2) • Synchronous 8-bit mode
  • (Note 4-1-3) 1tCYC +0.05 Serial output Output clock Output delay time tdDO(3) SO0(P10), SB0(P11) (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 μs Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be defined as the time up to the beginning of output state change in open drain output mode. See Fig. 9. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pins/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(3) Low level pulse width tSCKL(3) Input clock High level pulse width tSCKH(3) SCK1(P15) • See Fig. 9. 2.7 to 5.5 Frequency tSCK(4) tCYC Low level pulse width tSCKL(4) Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) • When CMOS output type is selected.
  • See Fig. 9. 2.7 to 5.5 tSCK Data setup time tsDI(2) 0.03 Serial input Data hold time thDI(2) SB1(P14), SI1(P14)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 9. 2.7 to 5.5 0.03 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
  • Must be specified with respect to falling edge of SIOCLK.
  • Must be specified as the time up to the beginning of output state change in open drain output mode.
  • See Fig. 9. 2.7 to 5.5 (1/3)tCYC +0.05 μs Note 4-2-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions.

No.A2197-20/35 3. SIO4 Serial I/O Characteristics (Note 4-3-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(5) 2 Low level pulse width tSCKL(5) 1 tSCKH(5) See Fig. 9. tSCKHA(5a) • USB, SIO0 continuous transfer mode, AIF not used at the same time.

  • See Fig. 9.
  • (Note 4-3-2) tSCKHA(5b) • USB used at the same time.
  • SIO0 continuous transfer mode, AIF not used at the same time.
  • See Fig. 9.
  • (Note 4-3-2) Input clock High level pulse width tSCKHA(5c) SCK4(P24)
  • USB, SIO0 continuous transfer mode used at the same time.
  • AIF not used at the same time.
  • See Fig. 9.
  • (Note 4-3-2) 2.7 to 5.5 Frequency tSCK(6) 4/3 tCYC Low level pulse width tSCKL(6) 1/2 tSCKH(6)
  • When CMOS output type is selected.
  • See Fig. 9. tSCK tSCKHA(6a) • USB, SIO0 continuous transfer mode AIF not used at the same time.
  • When CMOS output type is selected.
  • See Fig. 9. tSCKH(6) (5/3)tCYC tSCKH(6) (10/3)tCYC tSCKHA(6b) • USB used at the same time.
  • SIO0 continuous transfer mode AIF not used at the same time.
  • When CMOS output type is selected.
  • See Fig. 9. tSCKH(6) (5/3)tCYC tSCKH(6) (19/3)tCYC Serial clock Output clock High level pulse width tSCKHA(6c) SCK4(P24)
  • USB, SIO0 continuous transfer mode used at the same time
  • AIF not used at the same time.
  • When CMOS output type is selected.
  • See Fig. 9. 2.7 to 5.5 tSCKH(6) (5/3)tCYC tSCKH(6) (28/3)tCYC tCYC Data setup time tsDI(3) 0.03 Serial input Data hold time thDI(3) SO4(P22), SI4(P23)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 9. 2.7 to 5.5 0.03 Serial output Output delay time tdDO(5) SO4(P22), SI4(P23)
  • Must be specified with respect to falling edge of SIOCLK.
  • Must be specified as the time up to the beginning of output state change in open drain output mode
  • See Fig. 9. 2.7 to 5.5 (1/3)tCYC +0.05 μs Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-3-2: In an application where the serial clock input is to be used, the time from SI4RUN being set when serial clock is high to the falling edge of the first serial clock must be longer than tSCKHA when continuous data transmission/reception is started.

No.A2197-21/35 4-1. SMIIC0 Simple SIO Mode I/O Characteristics (Note 4-4-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(7) 4/3 Low level pulse width tSCKL(7) 2/3 Input clock High level pulse width tSCKH(7) SM0CK0(P17), SM0CK1(P13) See Fig. 9. 2.7 to 5.5 Frequency tSCK(8) 4/3 tCYC Low level pulse width tSCKL(8) Serial clock Output clock High level pulse width tSCKH(8) SM0CK0(P17), SM0CK1(P13)

  • When CMOS output type is selected.
  • See Fig. 9. 2.7 to 5.5 tSCK Data setup time tsDI(4) 0.03 Serial input Data hold time thDI(4) SM0DA0(P16), SM0DA1(P14)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 9. 2.7 to 5.5 0.03 Serial output Output delay time tdDO(6) SM0DO(P15), SM0DA0(P16), SM0DA1(P14)
  • Must be specified with respect to falling edge of SIOCLK.
  • Must be specified as the time to the beginning of output state change.
  • See Fig. 9. 2.7 to 5.5 (1/3)tCYC +0.05 μs Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions.

No.A2197-22/35 4-2. SMIIC0 I2C Mode I/O Characteristics (Note 4-5-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCL 5 Low level pulse width tSCLL 2.5 Input clock High level pulse width tSCLH SM0CK0(P17), SM0CK1(P13) See Fig. 11. 2.7 to 5.5 Frequency tSCLx 10 Tfilt Low level pulse width tSCLLx Serial clock Output clock HIghlevel pulse width tSCLHx SM0CK0(P17), SM0CK1(P13) Must be specified as the time up to the beginning of output state change. 2.7 to 5.5 tSCL SM0CK, SM0DA pin input spike suppression time tsp SM0CK0(P17), SM0CK1(P13), SM0DA0(P16), SM0DA1(P14) See Fig. 11. 2.7 to 5.5 1 Tfilt input tBUF See Fig. 11.

2.5 Tfilt

  • Standard clock mode
  • Must be specified as the time up to the beginning of output state change. 5.5 Bus relinquish time between start and stop Output tBUFx SM0CK0(P17), SM0CK1(P13), SM0DA0(P16), SM0DA1(P14)
  • High-speed clock mode
  • Must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1.6 μs
  • When SMIIC register control bit SHDS=0
  • See Fig. 11. 2.0 input tHD; STA
  • When SMIIC register control bit SHDS=1
  • See Fig. 11. 2.5 Tfilt
  • Standard clock mode
  • Must be specified as the time up to the beginning of output state change. 4.1 Start, restart condition hold time Output tHD; STAx SM0CK0(P17), SM0CK1(P13), SM0DA0(P16), SM0DA1(P14)
  • High-speed clock mode
  • Must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1.0 μs input tSU; STA See Fig. 11.

1.0 Tfilt

  • Standard clock mode
  • Must be specified as the time up to the beginning of output state change. 5.5 Restart condition setup time Output tSU; STAx SM0CK0(P17), SM0CK1(P13), SM0DA0(P16), SM0DA1(P14)
  • High-speed clock mode
  • Must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1.6 μs Continued on next page.

No.A2197-23/35 Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit input tSU; STO See Fig. 11.

  • Standard clock mode
  • Must be specified as the time up to the beginning of output state change. 4.9 Stop condition setup time Output tSU; STOx SM0CK0(P17), SM0CK1(P13), SM0DA0(P16), SM0DA1(P14)
  • High-speed clock mode
  • Must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1.1 μs Input tHD; DAT See Fig. 11. Data hold time Output tHD; DATx SM0CK0(P17), SM0CK1(P13), SM0DA0(P16), SM0DA1(P14) Must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1 1.5 Tfilt Input tSU; DAT See Fig. 11. Data setup time Output tSU; DATx SM0CK0(P17), SM0CK1(P13), SM0DA0(P16), SM0DA1(P14) Must be specified as the time up to the beginning of output state change. 2.7 to 5.5 1tSCL- 1.5Tfilt Tfilt Note 4-5-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-5-2: The value of Tfilt is determined by bits 7 and 6 (BRP1 and BRP0) of the SMIC0BRG register and the system clock frequency. BRP1 BRP0 Tfilt 0 0 (1/3) tCYC ×1 0 1 (1/3) tCYC ×2 1 0 (1/3) tCYC ×3 1 1 (1/3) tCYC ×4 Set the value of the BRP1 and BRP0 bits so that the value of Tfilt falls within the following value range: 250ns ≥ Tfilt > 140ns Note 4-5-3: For standard clock mode operation, set up the SMIC0BRG register so that the following conditions are satisfied: 250ns ≥ Tfilt > 140ns BRDQ (bit5) = 1 SCL frequency value ≤ 100kHz For high-speed clock mode operation, set up the SMIC0BRG register so that the following conditions are satisfied: 250ns ≥ Tfilt > 140ns BRDQ (bit5) = 1 SCL frequency value ≤ 400kHz

No.A2197-24/35 Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P25), INT6(P20), INT7(P24)

  • Interrupt source flag can be set.
  • Event inputs for timer 0/1 are enabled. 2.7 to 5.5 1 tPIH(2) tPIL(2) INT3(P73) when noisefilter time constant is 1/1.
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.7 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noisefilter time constant is 1/32.
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.7 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noisefilter time constant is 1/128.
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.7 to 5.5 256 tCYC tPIL(5) RMIN(P73) Recognized as a signal by infrared remote control receiver circuit 2.7 to 5.5 4 RMCK (Note 5-1) High/low level pulse width tPIL(6) RES Resetting is enabled. 2.7 to 5.5 200 μs Note 5-1: Denotes the reference frequency of the infrared remote control receiver circuit (1tCYC to 128tCYC or source oscillation frequency of the subclock)

No.A2197-25/35 AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V <12-bit AD Converter Mode> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 3.0 to 5.5 12 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 ±16 LSB 4.0 to 5.5 32 115 Conversion time TCAD See conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 64 115 μs Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V IAINH VAIN=V DD 3.0 to 5.5 1 Analog port input current IAINL AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) VAIN=VSS 3.0 to 5.5 -1 μA <8-bit AD Converter Mode> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 3.0 to 5.5 8 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 ±1.5 LSB 4.0 to 5.5 20 90 Conversion time TCAD See conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 40 90 μs Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V IAINH VAIN=V DD 3.0 to 5.5 1 A Analog port input current IAINL AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) VAIN=VSS 3.0 to 5.5 -1 μA Conversion time calculation formulas : 12-bits AD Converter Mode : TCAD (Conversion time) = ((52/(AD division ratio))+2) × (1/3) × tCYC 8-bits AD Converter Mode : TCAD (Conversion time) = ((32/(AD division ratio))+2) × (1/3) × tCYC <Recommended Operating Conditions> Conversion Time (TCAD)[μs] External Oscillator FmCF[MHz] Supply Voltage Range VDD[V] System Clock Division (SYSDIV) Cycle Time tCYC [ns] AD Frequency Division Ratio (ADDIV) 12-bit AD 8-bit AD 4.0 to 5.5 1/1 250 1/8 34.8 21.5 12 3.0 to 5.5 1/1 250 1/16 69.5 42.8 Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller’s state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process until the time the conversion result register is loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is doubled in the following cases:

  • The AD conversion is carried out in the 12-bit AD conversion mode for the first time after a system reset.
  • The AD conversion is carried out for the first time after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode.

No.A2197-26/35 Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Conditions Option selected voltage min typ max unit 1.67V 1.55 1.67 1.79 1.97V 1.85 1.97 2.09 2.07V 1.95 2.07 2.19 2.37V 2.25 2.37 2.49 2.57V 2.45 2.57 2.69 2.87V 2.75 2.87 2.99 3.86V 3.73 3.86 3.99 POR release voltage PORRL Select from option (Note 7-1) 4.35V 4.21 4.35 4.49 Detection voltage unknown state POUKS See Fig. 13 V Power supply rise time PORIS Power supply rise time from VDD=0V to 1.6V 100 ms Note 7-1: The POR release level can be selected out of 8 levels only when LDV reset function is disabled. Note 7-2: POR is in unknown state before transistors start operation. Low Voltage Detection (LVD) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Conditions Option selected voltage min typ max unit 1.91V 1.81 1.91 2.01 2.01V 1.91 2.01 2.11 2.31V 2.21 2.31 2.41 2.51V 2.41 2.51 2.61 2.81V 2.71 2.81 2.91 3.79V 3.69 3.79 3.89 LVD reset voltage (Note 8-2) LVDET 4.28V 4.18 4.28 4.38 V 1.91V 55 2.01V 55 2.31V 55 2.51V 55 2.81V 55 3.79V 60 LVD hysteresis width LVHYS Select from option. See Fig. 14. (Note 8-1) (Note 8-3) 4.28V 65 mV Detection voltage unknown state LVUKS See Fig. 14. (Note 8-4) 0.7 0.95 V Low voltage detection minimum width (Reply sensitivity) TLVDW LVDET-0.5V See Fig. 15. 0.2 ms Note 8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled. Note 8-2: LVD reset voltage specification values do not include hysteresis voltage. Note 8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note 8-4: LVD is in an unknown state before transistors start operation.

No.A2197-27/35 Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit 4.5 to 5.5 9.8 18 IDDOP(1) • FmCF=12MHz ceramic oscillation mode

  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation stopped
  • Internal low-/medium-speed RC oscillation stopped
  • USB circuit stopped
  • 1/1 frequency division ratio 3.0 to 3.6 5.7 11 4.5 to 5.5 15 28 IDDOP(2) • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation mode active
  • Internal low-/medium-speed RC oscillation stopped
  • USB circuit active
  • 1/1 frequency division ratio 3.0 to 3.6 8.1 15 4.5 to 5.5 6.7 12 3.0 to 3.6 4.2 7.1 IDDOP(3) • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 6MHz side
  • Internal low-/medium-speed RC oscillation stopped
  • 1/2 frequency division ratio 2.7 to 3.0 3.5 5.8 4.5 to 5.5 0.77 2.8 3.0 to 3.6 0.46 1.5 IDDOP(4) • External oscillation FmCF stopped
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to internal medium-speed RC oscillation
  • Internal low-speed RC oscillation stopped
  • 1/2 frequency division ratio 2.7 to 3.0 0.39 1.3 mA 4.5 to 5.5 28 170 3.0 to 3.6 18 100 IDDOP(5) • External oscillation FsX'tal /FmCF stopped
  • System clock set to internal low-speed RC oscillation
  • Internal medium-speed RC oscillation stopped
  • 1/1 frequency division ratio 2.7 to 3.0 16 87 4.5 to 5.5 45 124 3.0 to 3.6 18 60 Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(6) • External oscillation FmCF stopped
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 32.768kHz side
  • Internal low-/medium-speed RC oscillation stopped
  • 1/2 frequency division ratio 2.7 to 3.0 14 48 μA 4.5 to 5.5 4.0 7.0 HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(1) VDD1 =VDD2 =VDD3
  • HALT mode
  • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation stopped
  • Internal low-/medium-speed RC oscillation stopped
  • USB circuit stopped
  • 1/1 frequency division ratio 3.0 to 3.6 2.2 3.8 mA Note 9-1: The consumption current value do not include current that flows into the output transistors and internal pull-up resistors. Note 9-2: The consumption current values do not include operational current of LVD (Low Voltage Detection) function if not specified. Continued on next page.

No.A2197-28/35 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit 4.5 to 5.5 9.2 18 IDDHALT(2) • HALT mode

  • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation active
  • Internal low-/medium-speed RC oscillation stopped
  • USB circuit active
  • 1/1 frequency division ratio 3.0 to 3.6 4.7 8.6 4.5 to 5.5 2.5 4.5 3.0 to 3.6 1.3 2.3 IDDHALT(3) • HALT mode
  • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 6MHz side
  • Internal low-/medium-speed RC oscillation stopped
  • 1/2 frequency division ratio 2.7 to 3.0 1.1 1.8 4.5 to 5.5 0.41 1.5 3.0 to 3.6 0.20 0.72 IDDHALT(4) • HALT mode
  • External oscillation FmCF stopped
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to internal medium-speed RC oscillation
  • Internal low-speed RC oscillation stopped
  • 1/2 frequency division ratio 2.7 to 3.0 0.17 0.53 mA 4.5 to 5.5 7.2 95 3.0 to 3.6 4.0 51 IDDHALT(5) • HALT mode
  • External oscillation FsX'tal /FmCF stopped
  • System clock set to internal low-speed RC oscillation
  • Internal medium-speed RC oscillation stopped.
  • 1/1 frequency division ratio 2.7 to 3.0 3.4 43 4.5 to 5.5 30 112 3.0 to 3.6 8.4 51 HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(6) • HALT mode
  • External oscillation FmCF stopped
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 32.768kHz side
  • Internal low-/medium-speed RC oscillation stopped.
  • 1/2 frequency division ratio 2.7 to 3.0 5.8 40 4.5 to 5.5 0.28 67 3.0 to 3.6 0.22 35 IDDHOLD(1) • HOLD mode
  • CF1=VDD or open (External clock mode) 2.7 to 3.0 0.21 30 4.5 to 5.5 2.8 70 3.0 to 3.6 2.3 38 IDDHOLD(2) • HOLD mode
  • LVD option selected
  • CF1=VDD or open (External clock mode) 2.7 to 3.0 2.1 33 4.5 to 5.5 0.98 68 3.0 to 3.6 0.62 36 HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(3) • HOLD mode
  • Internal timer type watchdog timer active (Internal low-speed RC oscillation circuit active)
  • CF1=VDD or open (External clock mode) 2.7 to 3.0 0.51 31 4.5 to 5.5 26 106 3.0 to 3.6 6.1 49 IDDHOLD(4) • X'tal HOLD mode
  • CF1=VDD or open (External clock mode)
  • FsX'tal=32.768kHz crystal oscillation mode 2.7 to 3.0 3.8 38 4.5 to 5.5 1.0 68 3.0 to 3.6 0.64 36 X'tal HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(5) VDD1 =VDD2 =VDD3
  • X'tal HOLD mode
  • CF1=VDD or open (External clock mode)
  • FmSRC=30kHz internal low-speed RC oscillation mode 2.7 to 3.0 0.53 31 μA Note 9-1: The consumption current value do not include current that flows into the output transistors and internal pull-up resistors. Note 9-2: The consumption current values do not include operational current of LVD (Low Voltage Detection) function if not specified.

No.A2197-29/35 USB Characteristics and Timing at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Conditions Parameter Symbol Pin/Remarks min typ max unit High level output V OH(USB) • 15k Ω±5% to GND 2.8 3.6 V Low level output VOL(USB) • 1.5k Ω±5% to 3.6V 0.0 0.3 V Output signal crossover voltage V CRS 1.3 2.0 V Differential input sensitivity V DI • |(UHAD+) – (UHAD–)|

  • |(UHBD+) – (UHBD–)| 0.2 V Differential input common mode range V CM 0.8 2.5 V High level input V IH(USB) 2.0 3.6 V Low level input V IL(USB) 0.0 0.8 V Rise time (full-speed) t FR R S=33Ω, CL=50pF 4 20 ns Fall time (full-speed) t FF R S=33Ω, CL=50pF 4 20 ns Rise time (low-speed) t LR R S=33Ω, CL=200 to 600pF 75 300 ns Fall time (low-speed) t LF R S=33Ω, CL=200 to 600pF 75 300 ns F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Onboard programming current IDDFW(1) V DD1 • Excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 mA tFW(1) • Erase operation 20 30 ms Programming time tFW(2)
  • Write operation 3.0 to 5.5 40 60 μs

No.A2197-30/35 Main System Clock Oscillation The characteristics of a sample main system clock oscillator circuit shown in Table 1 are measured using a Our specification oscillation characteristics evaluation board and external components with circuit constant values with which the resonator vendor confirmed normal and stable oscillation. Table 1 shows the characteristics of a oscillator circuit when USB host function is not used. If USB host function is to be used, it is absolutely recommended to use a resonator that satisfies the precision and stability according to the USB standards (±500ppm) Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator Circuit Constant Oscillation Stabilization Time Nominal Frequency Vendor Name Resonator Name [pF] [pF] Rd1 [Ω] Operating Voltage Range [V] typ [ms] max [ms] Remarks 12MHz MURATA CSTCE12M0GH5L**-R0 (33) (33) 470 3.0 to 5.5 0.1 0.5 C1 and C2 integrated SMD type The oscillation stabilization time is required for the oscillator to get stabilized in the following cases (see Figure 4):

  • Until oscillation is stabilized after VDD goes above the operating voltage lower limit
  • Until oscillation is stabilized after the instruction for starting the main clock oscillator circuit is executed
  • Until oscillation is stabilized after HOLD mode is released.
  • Until oscillation is stabilized after X'tal HOLD mode is released with CFSTOP (OCR register, bit 0) set to 0 and oscillation is started. Subsystem Clock Oscillation Table 2 shows the characteristics of a sample subsystem clock oscillator circuit that are measured using a Our specification oscillation characteristics evaluation board and external components with circuit constant values with which the resonator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator Circuit Constant Oscillation Stabilization Time Nominal Frequency Vendor Name Resonator Name C3 [pF] [pF] Rf [Ω] Rd2 [Ω] Operating Voltage Range [V] typ [s] max [s] Remarks Applicable CL value=12.5pF SMD type The oscillation stabilization time is required for the oscillator to get stabilized in the following cases (see Figure 4):
  • Until oscillation is stabilized after the instruction for starting the subclock oscillator circuit is executed
  • Until oscillation is stabilized after HOLD mode is released with EXTOSC (OCR register, bit 6) set to 1 and oscillation is started. Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. Figure 1 CF Oscillator Circuit Figure 2 Crystal Oscillator Circuit Rf Rd2 XT1 XT2 X’tal Rd1 CF1 CF2 CF