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Technical content

Features

Flash ROM

  • 196608 × 8 bits
  • Capable of on-board programming with a wide range of supply voltages: 3.0 to 5.5V
  • Block-erasable in 128 byte units
  • Writes data in 2-byte units RAM
  • 16384 × 9 bits Package Form
  • SQFP48(7×7): Lead-/Halogen-free type SANYO : SQFP48(7X7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5)0.1 1.7max 0.180.5 (0.75) 11 2 2536 Package Dimensions unit : mm (typ) 3163B CMOS IC FROM 192K byte, RAM 16384 byte on-chip 8-bit 1-chip Microcontroller with USB-host controller * This product is licensed from Silicon Storage Technology, Inc. (USA).

No.A1453-2/27 Bus Cycle Time

  • 83.3ns (When CF=12MHz) Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time (tCYC)
  • 250ns (When CF=12MHz) Ports
  • I/O ports Ports whose I/O direction can be designated in 1-bit units 28 (P10 to P17, P20 to P27, P30 to P34, P70 to P73, PWM0, PWM1, XT2) Ports whose I/O direction can be designated in 4-bit units 8 (P00 to P07)
  • USB ports 2 (UHD+, UHD-)
  • Dedicated oscillator ports 2 (CF1, CF2)
  • Input-only port (also used for oscillation) 1 (XT1)
  • Reset pin 1 ( RES)
  • Power supply pins 6 (V SS1 to VSS3, VDD1 to VDD3) Timers
  • Timer 0: 16-bit timer/counter with 2 capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers)
  • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as PWM outputs)
  • Timer 4: 8-bit timer with a 6-bit prescaler
  • Timer 5: 8-bit timer with a 6-bit prescaler
  • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
  • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
  • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes SIO
  • SIO0: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 512/3 tCYC 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units) (Suspension and resumption of data transmission possible in 1 byte units)
  • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
  • SIO4: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 8192 bytes, specifiable in 1 byte units) (Suspension and resumption of data transmission possible in 1 byte units or in word units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in

No.A1453-3/27

  • SIO9: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 8192 bytes, specifiable in 1 byte units) (Suspension and resumption of data transmission possible in 1 byte units or word units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in Full Duplex UART 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Baud rate: 16/3 to 8192/3 tCYC AD Converter: 8 bits × 12 channels PWM: Multifrequency 12-bit PWM × 2 channels Infrared Remote Control Receiver Circuit 1) Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is selected as the base clock) 2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding. 3) X'tal HOLD mode release function USB Interface (host control function) 1) Compliant with full-speed (12M bps) specifications 2) Supports 4 transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer). Audio Interface 1) Sampling frequency (fs): 8kHz/11.025kHz/12kHz/16kHz/22.05kHz/24kHz/32kHz/44.1kHz/48kHz 2) Master clock frequency: 256fs/384fs 3) Bit clock selectable: 48fs/64fs 4) Data bit length: 16/18/20/24 bits 5) LSB first/MSB first mode selectable 6) Left-justification/right-justification/I2S format selectable Watchdog Timer
  • Watchdog timer using external RC circuitry
  • Interrupt and reset signals selectable Clock Output Function 1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as the system clock. 2) Can output the source oscillation clock for the subclock.

No.A1453-4/27 Interrupts

  • 41 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/IN T4/UHC bus active/remote control signal receive 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H/INT6/UHC device attach/UHC device detach/UHC resume 6 0002BH H or L T1L/T1H /INT7/SIO9/AIF start 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/SIO4/UART1 transmit/AIF end 9 00043H H or L ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC-STALL 10 0004BH H or L Port 0/PWM0/PWM1/T4/T5/UHC-SOF/DMCOPY/AIF error
  • Priority levels X > H > L
  • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 8192 levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions
  • 16 bits × 8 bits (5 tCYC execution time)
  • 24 bits × 16 bits (12 tCYC execution time)
  • 16 bits ÷ 8 bits (8 tCYC execution time)
  • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation and PLL Circuits
  • RC oscillation circuit (internal): For system clock
  • CF oscillation circuit: For system clock
  • Crystal oscillation circuit: For system clock, and realtime clock
  • PLL circuit (internal): For USB interface (s ee Fig.5) and audio interface (see Fig. 6)

No.A1453-5/27 Standby Function

  • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of releasing the HALT mode. (1) Setting the reset pin to the lower level. (2) System resetting by watchdog timer (3) Generating an interrupt
  • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation. 2) There are five ways of releasing the HOLD mode. (1) Setting the reset pin to the lower level (2) System resetting by watchdog timer (3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4, and INT5 pins * The INT0 and INT1 pins must be configured only for level detection. (4) Having an interrupt source established at port 0 (5) Having an bus active interrupt source established in the USB host control circuit
  • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The PLL base clock generator, CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are seven ways of releasing the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) System resetting by watchdog timer (3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4, and INT5 pins * The INT0 and INT1 pins must be configured only for level detection. (4) Having an interrupt source established at port 0 (5) Having an interrupt source established in the base timer circuit (6) Having an bus active interrupt source established in the USB host control circuit (7) Having an interrupt source established in the infrared remote controller receiver circuit Development Tools
  • On-chip debugger: TCB87- type B + LC87F1JJ2A Flash ROM Programming Boards Package Programming board SQFP48(7×7) W87F55256SQ  Flash ROM Programmer Maker Model Supported Version Device Flash Support Group, Inc. (FSG) Single AF9708/ AF9709/AF9709B/AF9709C (including Ando Electric Co., Ltd. models) Rev. 03.12 or later LC87F1JJ2A Flash Support Group, Inc. (FSG) Our company(Note 1) Onboard single/ganged AF9101/AF9103(main unit) (FSG) (Note 2) LC87F1JJ2A SIB87(interface driver) (Our company model) Our company Single/ganged SKK/SKK Type B (SANYO FWS) Application version: 1.04 or later Chip data version: 2.17 or later LC87F1JJ2 Onboard single/ganged SKK-DBG Type B (SANYO FWS) Note 1: PC-less standalone onboard programming is possible using the FSG onboard programmer (AF9101/AF9103) and the serial interface driver (SIB87) provided by Our company in pair. Note 2: Dedicated programming device and program are required depending on the programming conditions. Contact Our company or FSG if you have any questions or difficulties regarding this matter.

No.A1453-6/27 Pin Assignment SQFP48(7×7) “Lead-/Halogen-free type” SQFP48 NAME SQFP48 NAME

1 P73/INT3/T0IN/RMIN 25 P04/AN4/DBGP2

2 RES 26 P05/AN5/CKO/SDAT

3 XT1/AN10 27 P06/AN6/T6O/BCLK

4 XT2/AN11 28 P07/AN7/T7O/LRCK

5 V SS1 29 P20/INT4/INT6

6 CF1 30 P21/INT4

7 CF2 31 P22/INT4/SO4/ RD

8 V DD1 32 P23/INT4/SI4/ WR

9 P10/SO0 33 P24/INT5/INT7/SCK4

10 P11/SI0/SB0 34 P25/INT5/SO9/ RD9

11 P12/SCK0 35 P26/INT5/SI9/ WR9

12 P13/SO1 36 P27/INT5/SCK9

13 P14/SI1/SB1 37 UHD-

14 P15/SCK1 38 UHD+

15 P16/T1PWML 39 V DD3

16 P17/T1PWMH/BUZ 40 V SS3

17 PWM1/MCLKI 41 P34/UFILT

18 PWM0/MCLKO 42 P33/AFILT

19 V DD2 43 P32

20 V SS2 44 P31/URX1

21 P00/AN0 45 P30/UTX1

22 P01/AN1 46 P70/INT0/T0LCP/AN8

23 P02/AN2/DBGP0 47 P71/INT1/T0HCP/AN9

24 P03/AN3/DBGP1 48 P72/INT2/T0IN

No.A1453-7/27 System Block Diagram Interrupt control FROM Standby control Clock generator CF X’tal RC IR PLA PC Bus interface Port 0 Port 1 ACC B register C register ALU PSW RAR RAM Stack pointer Watchdog timer Base timer Timer 4 PWM1 INT0 to INT7 noise filter SIO0 Port 2 USB PLL Port 7 Port 3 ADC SIO1 Timer 0 Timer 1 PWM0 Timer 5 Timer 6 Timer 7 UART1 SIO4 On-chip debugger USB host SIO9 Audio interface Infrared remote control receiver circuit

No.A1453-8/27 Pin Description Pin Name I/O Description Option VSS1,VSS2, VSS3 - - power supply No VDD1, VDD2 - + power supply No VDD3 - USB reference voltage Yes Port 0 I/O • 8-bit I/O ports

  • I/O specifiable in 4-bit units
  • Pull-up resistors can be turned on and off in 4-bit units.
  • HOLD release input
  • Port 0 interrupt input
  • Pin functions AD converter input ports: AN0 to AN7(P00 to P07) On-chip debugger pins: DBGP0 to DBGP2(P02 to P04) P05: System clock output/audio interface SDAT input/output P06: Timer 6 toggle output/audio interface BCLK input/output P07: Timer 7 toggle output/audio interface LRCK input/output Yes P00 to P07 Port 1 I/O • 8-bit I/O ports
  • I/O specifiable in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P10: SIO0 data output P14: SIO1 data input/bus input/output P11: SIO0 data input/bus input/output P15: SIO1 clock input/output P12: SIO0 clock input/output P16: Timer 1 PWML output P13: SIO1 data output P17: Timer 1 PWMH output/beeper output Yes P10 to P17 Port 2 I/O • 8-bit I/O ports
  • I/O specifiable in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P20 to P23: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P20: INT6 input/timer 0L capture 1 input P22: SIO4 data input/output/parallel interface RD output P23: SIO4 data input/output/parallel interface WR output P24: SIO4 clock input/output/INT7 input/timer 0H capture 1 input P25: SIO9 data input/output/parallel interface RD9 output P26: SIO9 data input/output/parallel interface WR9 output P27: SIO9 clock input/output Interrupt acknowledge types Yes P20 to P27 Rising Falling Rising & Falling H level L level INT4 enable enable enable disable disable INT5 enable enable enable disable disable INT6 enable enable enable disable disable INT7 enable enable enable disable disable Port 3 I/O • 5-bit I/O ports
  • I/O specifiable in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P30: UART1 transmit P31: UART1 receive P33: Audio interface PLL filter circuit connection pin (See Fig. 6.) P34: USB interface PLL filter circuit connection pin (See Fig. 5.) Yes P30 to P34 Continued on next page.

No.A1453-9/27 Continued from preceding page. Pin Name I/O Description Option Port 7 I/O • 4-bit I/O ports

  • I/O specifiable in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (input with noise filter)/timer 0 event input/timer 0H capture input/ infrared remote control receiver input AD converter input ports: AN8(P70), AN9(P71) Interrupt acknowledge types No P70 to P73 Rising Falling Rising & Falling H level L level INT0 enable enable disable enable enable INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable PWM0 PWM1 I/O PWM0, PWM1 output ports General-purpose input port
  • Pin functions PWM0: Audio interface master clock output PWM1: Audio interface master clock input No UHD- I/O USB data I/O pin UHD-/general-purpose I/O port No UHD+ I/O USB data I/O pin UHD+/general-purpose I/O port No RES I Reset pin No XT1 I • 32.768kHz crystal oscillator input
  • Pin functions General-purpose input port AD converter input port: AN10 Must be connected to VDD1 when not to be used. No XT2 I/O • 32.768kHz crystal oscillator output
  • Pin functions General-purpose input port AD converter input port: AN11 Must be configured for oscillation and kept open if not to be used. No CF1 I Ceramic/crystal resonator input No CF2 O Ceramic/crystal resonator output No Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of Option Type Output Type Pull-up Resistor P00 to P07 1 bit 1 CMOS Programmable (Note 1)

2 Nch-open drain No

2 Nch-open drain Programmable

P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable PWM0, PWM1 - No CMOS No UHD+, UHD- - No CMOS No XT1 - No Input only No XT2 - No 32.768kHz crystal resonator output (Nch-open drain when in general-purpose output mode) No Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).

No.A1453-10/27 User Options Option Name Type Flash ROM Version Option Selected in Units of Setting Port output type P00 to P07  1 bit CMOS Nch-open drain P10 to P17  1 bit CMOS Nch-open drain P20 to P27  1 bit CMOS Nch-open drain P30 to P34  1 bit CMOS Nch-open drain Program start address -  - 00000h 1FE00h USB Regulator USB Regulator  - Use Nonuse USB Regulator (at HOLD mode)  - Use Nonuse USB Regulator (at HALT mode)  - Use Nonuse Power Pin Treatment Connect the IC as shown below to minimize the noise input to the VDD1 pin and extend the backup period. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of output ports is supplied by their backup capacitors. Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode. VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply For backup LSI LSI VSS1V SS2V SS3 VDD1 VDD2 VDD3 Power supply For backup

No.A1453-11/27 USB Reference Power Option When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be switched by optional settings. The procedure for marking the optional settings is described below. (1) (2) (3) (4) Option settings USB regulator Use Use Use Nonuse USB regulator in HOLD mode Use Nonuse Nonuse Nonuse USB regulator in HALT mode Use Nonuse Use Nonuse Reference voltage circuit state Normal mode Active Active Active Inactive HOLD mode Active Inactive Inactive Inactive HALT mode Active Inactive Active Inactive

  • When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is equal to VDD1.
  • Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
  • When the reference voltage circuit is activated, the current drain increases by approximately 100μA compared with when the reference voltage circuit is inactive. Circuit example 1: When VDD1=VDD2=3.3V
  • Inactivating the reference voltage circuit (selection (4)).
  • Connecting VDD3 to VDD1 and VDD2. *1: Needs adjustment on target board. Circuit example 2: When VDD1=VDD2=5.0V
  • Activating the reference voltage circuit (selection (1)).
  • Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS. VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply 3.3V LSI UHD+ UHD- UFILT 15kΩ To USB connector 33Ω 5pF 2.2μF 2.2μF VSS1 VSS2 V SS3 VDD1 VDD2 VDD3 Power supply LSI UHD+ UHD- UFILT 2.2μF 15kΩ To USB connector 33Ω 5pF 2.2μF 0.1μF

No.A1453-12/27 Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Maximum supply voltage V DD max V DD1, VDD2, VDD3 V DD1= VDD2= VDD3 -0.3 +6.5 V Input voltage V I(1) XT1, CF1 -0.3 V DD+0.3 Input/output voltage VIO(1) Ports 0, 1, 2, 3, 7 PWM0, PWM1 XT2 -0.3 V DD+0.3 High level output current Peak output current IOPH(1) Ports 0, 1, 2 • When CMOS output type is selected

  • Per 1 applicable pin -10 mA IOPH(2) PWM0, PWM1 Per 1 applicable pin -20 IOPH(3) Port 3 P71 to P73
  • When CMOS output type is selected
  • Per 1 applicable pin Average output current (Note 1-1) IOMH(1) Ports 0, 1, 2 • When CMOS output type is selected
  • Per 1 applicable pin -7.5 IOMH(2) PWM0, PWM1 Per 1 applicable pin -15 IOMH(3) Port 3 P71 to P73
  • When CMOS output type is selected
  • Per 1 applicable pin Total output current ΣIOAH(1) Ports 0, 2 To tal current of all applicable pins -25 ΣIOAH(2) Port 1 PWM0, PWM1 Total current of all applicable pins -25 ΣIOAH(3) Ports 0, 1, 2 PWM0, PWM1 Total current of all applicable pins -45 ΣIOAH(4) Port 3 P71 to P73 Total current of all applicable pins -10 ΣIOAH(5) UHD+, UHD- Total current of all applicable pins -25 Low level output current Peak output current IOPL(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin 2 0 IOPL(2) P00, P01 Per 1 applicable pin 3 0 IOPL(3) Ports 3, 7 XT2 Per 1 applicable pin 1 0 Average output current (Note 1-1) IOML(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin 1 5 IOML(2) P00, P01 Per 1 applicable pin 2 0 IOML(3) Ports 3, 7 XT2 Per 1 applicable pin 7.5 Total output current ΣIOAL(1) Ports 0, 2 Total current of all applicable pins 4 5 ΣIOAL(2) Port 1 PWM0, PWM1 Total current of all applicable pins 4 5 ΣIOAL(3) Ports 0, 1, 2 PWM0, PWM1 Total current of all applicable pins 8 0 ΣIOAL(4) Ports 3, 7 XT2 Total current of all applicable pins 1 5 ΣIOAL(5) UHD+, UHD- Total current of all applicable pins 2 5 Allowable power dissipation Pd max SQFP48(7 ×7) Ta=-40 to +85 °C 140 mW Operating ambient temperature Topr -40 +85 Storage ambient temperature Tstg -55 +125 Note 1-1: The average output current is an average of current values measured over 100ms intervals. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Oper ating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No.A1453-13/27 Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Operating supply voltage (Note 2-1) VDD(1) V DD1=VDD2=VDD3 0.245 μs ≤ tCYC ≤ 200μs 3.0 5.5 V 0.490μs ≤ tCYC ≤ 200μs Except in onboard programming mode 2.7 5.5 Memory sustaining supply voltage VHD V DD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode. 2.0 5.5 High level input voltage VIH(1) Ports 0, 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 2.7 to 5.5 0.3VDD +0.7 V DD VIH(2) Port 70 watchdog timer side 2.7 to 5.5 0.9V DD V DD VIH(3) XT1, XT2, CF1, RES 2.7 to 5.5 0.75V DD V DD Low level input voltage VIL(1) Ports 1, 2, 3 P71 to P73 P70 port input/ interrupt side 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(2) 2.7 to 4.0 V SS 0.2V DD VIL(3) Port 0 PWM0, PWM1 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(4) 2.7 to 4.0 V SS 0.2V DD VIL(5) Port 70 watchdog timer side 2.7 to 5.5 V SS 0.8VDD -1.0 VIL(6) XT1, XT2, CF1, RES 2.7 to 5.5 V SS 0.25V DD Instruction cycle time (Note 2-2) tCYC 3.0 to 5.5 0.245 200 μs Except in onboard programming mode 2.7 to 5.5 0.490 200 External system clock frequency FEXCF(1) CF1 • CF2 pin open

  • System clock frequency division ratio=1/1
  • External system clock duty =50±5% 3.0 to 5.5 0.1 12 MHz
  • CF2 pin open
  • System clock frequency division ratio=1/1
  • External system clock duty =50±5% 2.7 to 5.5 0.1 6 Oscillation frequency range (Note 2-3) FmCF(1) CF1, CF2 When 12M Hz ceramic oscillation See Fig. 1. 3.0 to 5.5 12 MHz FmCF(2) CF1, CF2 When 6M Hz ceramic oscillation See Fig. 1. 2.7 to 5.5 6 FsX’tal XT1, XT2 32.768kHz crystal oscillation Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See oscillation characteristics examples.

No.A1453-14/27 Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit High level input current IIH(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 UHD+, UHD- Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) 2.7 to 5.5 1 μA IIH(2) XT1, XT2 Input port configuration VIN=VDD 2.7 to 5.5 1 IIH(3) CF1 V IN=VDD 2.7 to 5.5 15 Low level input current IIL(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 UHD+, UHD- Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) 2.7 to 5.5 -1 IIL(2) XT1, XT2 Input port configuration VIN=VSS 2.7 to 5.5 -1 IIL(3) CF1 V IN=VSS 2.7 to 5.5 -15 High level output voltage VOH(1) Ports 0, 1, 2, 3 P71 to P73 IOH=-1mA 4.5 to 5.5 V DD-1 V VOH(2) I OH=-0.4mA 3.0 to 5.5 V DD-0.4 VOH(3) I OH=-0.2mA 2.7 to 5.5 V DD-0.4 VOH(4) PWM0, PWM1 P05 to P07 (Note 3-1) IOH=-10mA 4.5 to 5.5 V DD-1.5 VOH(5) I OH=-1.6mA 3.0 to 5.5 V DD-0.4 VOH(6) I OH=-1mA 2.7 to 5.5 V DD-0.4 Low level output voltage VOL(1) P00, P01 I OL=30mA 4.5 to 5.5 1.5 VOL(2) I OL=5mA 3.0 to 5.5 0.4 VOL(3) I OL=2.5mA 2.7 to 5.5 0.4 VOL(4) Ports 0, 1, 2 PWM0, PWM1 XT2 IOL=10mA 4.5 to 5.5 1.5 VOL(5) I OL=1.6mA 3.0 to 5.5 0.4 VOL(6) I OL=1mA 2.7 to 5.5 0.4 VOL(7) Ports 3, 7 IOL=1.6mA 3.0 to 5.5 0.4 VOL(8) I OL=1mA 2.7 to 5.5 0.4 Pull-up resistance Rpu(1) Ports 0, 1, 2, 3 Port 7 VOH=0.9VDD 4.5 to 5.5 15 35 80 kΩ Rpu(2) 2.7 to 4.5 18 50 150 Hysteresis voltage VHYS RES Port 1, 2, 3, 7 2.7 to 5.5 0.1VDD V Pin capacitance CP All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.7 to 5.5 10 pF Note 3-1: When the CKO system clock output function (P05) or audio interface output function (P05 to P07) is used.

No.A1453-15/27 Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(1) SCK0(P12) See Fig. 9. 2.7 to 5.5 tCYC Low level pulse width tSCKL(1) 1 High level pulse width tSCKH(1) tSCKHA(1a) • Continuous data transfer mode

  • USB, AIF, SIO4, SIO9, and DMCOPY not used at the same time.
  • See Fig. 9.
  • (Note 4-1-2) tSCKHA(1b) • Continuous data transfer mode
  • USB used at the same time.
  • AIF, SIO4, SIO9, and DMCOPY not used at the same time.
  • See Fig. 9.
  • (Note 4-1-2) tSCKHA(1c) • Continuous data transfer mode
  • USB, AIF, SIO4, SIO9, and DMCOPY used at the same time.
  • See Fig. 9.
  • (Note 4-1-2) Output clock Frequency tSCK(2) SCK0(P12) • When CMOS output type is selected
  • See Fig. 9. 2.7 to 5.5 Low level pulse width tSCKL(2) tSCK High level pulse width tSCKH(2) tSCKHA(2a) • Continuous data transfer mode
  • USB, AIF, SIO4, SIO9, and DMCOPY not used at the same time.
  • When CMOS output type is selected
  • See Fig. 9. tSCKH(2) +2tCYC tSCKH(2) (10/3)tCYC tCYC tSCKHA(2b) • Continuous data transfer mode
  • USB used at the same time.
  • AIF, SIO4, SIO9, and DMCOPY not used at the same time.
  • When CMOS output type is selected.
  • See Fig.9. tSCKH(2) +2tCYC tSCKH(2) (19/3)tCYC tSCKHA(2c) • Continuous data transfer mode
  • USB, AIF, SIO4, SIO9, and DMCOPY used at the same time
  • When CMOS output type is selected
  • See Fig.9. tSCKH(2) +2tCYC tSCKH(2) (25/3)tCYC Note 4-1-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-1-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the time from SI0RUN being set when serial clock is high to the falling edge of the first serial clock must be longer than tSCKHA. Continued on next page.

No.A1453-16/27 Continued from preceding page. Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Serial input Data setup time tsDI(1) SB0(P11), SI0(P11)

  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 9. 2.7 to 5.5 0.03 μs Data hold time thDI(1) 0.03 Serial output Input clock Output delay time tdDO(1) SO0(P10), SB0(P11)
  • Continuous data transfer mode
  • (Note 4-1-3) 2.7 to 5.5 (1/3)tCY C +0.05 tdDO(2)
  • Synchronous 8-bit mode
  • (Note 4-1-3) 1tCYC +0.05 Output clock tdDO(3) (Note 4-1-3) (1/3)tCY C +0.05 Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 9. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(3) SCK1(P15) See Fig. 9. 2.7 to 5.5 tCYC Low level pulse width tSCKL(3) 1 High level pulse width tSCKH(3) 1 Output clock Frequency tSCK(4) SCK1(P15) • When CMOS output type is selected
  • See Fig. 9. 2.7 to 5.5 Low level pulse width tSCKL(4) 1/2 tSCK High level pulse width tSCKH(4) 1/2 Serial input Data setup time tsDI(2) SB1(P14), SI1(P14)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 9. 2.7 to 5.5 0.03 μs Data hold time thDI(2) 0.03 Serial output Output delay time tdDO(4) SO1(P13), SB1(P14)
  • Must be specified with respect to falling edge of SIOCLK.
  • Must be specified as the time to the beginning of output state change in open drain output mode.
  • See Fig. 9. 2.7 to 5.5 (1/3)tCYC +0.05 Note 4-2-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions.

No.A1453-17/27 3. SIO4 Serial I/O Characteristics (Note 4-3-1) Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(5) SCK4(P24) See Fig. 9. 2.7 to 5.5 tCYC Low level pulse width tSCKL(5) 1 High level pulse width tSCKH(5) tSCKHA(5a) • USB, SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time.

  • See Fig. 9.
  • (Note 4-3-2) tSCKHA(5b) • USB used at the same time
  • SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time.
  • See Fig. 9.
  • (Note 4-3-2) tSCKHA(5c) • USB, SIO0 continuous transfer mode, SIO9, and DMCOPY used at the same time.
  • AIF not used at the same time.
  • See Fig. 9.
  • (Note 4-3-2) Output clock Frequency tSCK(6) SCK4(P24) • When CMOS output type is selected.
  • See Fig. 9. 2.7 to 5.5 Low level pulse width tSCKL(6) tSCK High level pulse width (Note 4-3-3) tSCKH(6) tSCKHA(6a) • USB, SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time.
  • When CMOS output type is selected.
  • See Fig. 9. tSCKH(6) (5/3)tCYC tSCKH(6) (10/3)tCYC tCYC tSCKHA(6b) • USB used at the same time.
  • SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time.
  • When CMOS output type is selected.
  • See Fig. 9. tSCKH(6) (5/3)tCYC tSCKH(6) (19/3)tCYC tSCKHA(6c) • USB, SIO0 continuous transfer mode, SIO9, and DMCOPY used at the same time.
  • AIF not used at the same time.
  • When CMOS output type is selected.
  • See Fig. 9. tSCKH(6) (5/3)tCYC tSCKH(6) (34/3)tCYC Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-3-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period from the time SI4RUN is set with the serial clock set high to the falling edge of the first serial clock must be longer than tSCKHA. Note 4-3-3: When using the serial clock output, make sure that the load at the SCK4 (P24) pin meets the following conditions: Clock rise time tSCKR < 0.037μs (see Figure 12.) at Ta=+25°C, VDD=3.3V Continued on next page.

No.A1453-18/27 Continued from preceding page. Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Serial input Data setup time tsDI(3) SO4(P22), SI4(P23)

  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 9 2.7 to 5.5 0.03 μs Data hold time thDI(3) 0.03 Serial output Output delay time tdDO(5) SO4(P22), SI4(P23)
  • Must be specified with respect to falling edge of SIOCLK.
  • Must be specified as the time to the beginning of output state change in open drain output mode.
  • See Fig. 9. 2.7 to 5.5 (1/3)tCYC +0.05 4. SIO9 Serial I/O Characteristics (Note 4-4-1) Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(7) SCK9(P27) See Fig. 9. 2.7 to 5.5 tCYC Low level pulse width tSCKL(7) 1 High level pulse width tSCKH(7) tSCKHA(7a) • USB, SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time.
  • See Fig. 9.
  • (Note 4-4-2) tSCKHA(7b) • USB used at the same time.
  • SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time.
  • See Fig. 9.
  • (Note 4-4-2) tSCKHA(7c) • USB, SIO0 continuous transfer mode, SIO4, and DMCOPY used at the same time.
  • AIF not used at the same time.
  • See Fig. 9.
  • (Note 4-4-2) Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-4-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period from the time SI9RUN is set with the serial clock set high to the falling edge of the first serial clock must be longer than tSCKHA. Continued on next page.

No.A1453-19/27 Continued from preceding page. Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Serial clock Output clock Frequency tSCK(8) SCK9(P27) • When CMOS output type is selected.

  • See Fig. 9. 2.7 to 5.5 4/3 tCYC Low level pulse width tSCKL(8) tSCK High level pulse width (Note 4-4-3) tSCKH(8) tSCKHA(8a) • USB, SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time.
  • When CMOS output type is selected.
  • See Fig. 9. tSCKH(8) (5/3)tCYC tSCKH(8) (10/3)tCYC tCYC tSCKHA(8b) • USB used at the same time.
  • SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time.
  • When CMOS output type is selected
  • See Fig. 9. tSCKH(8) (5/3)tCYC tSCKH(8) (19/3)tCYC tSCKHA(8c) • USB, SIO0 continuous transfer mode , SIO4, and DMCOPY used at the same time.
  • AIF not used at the same time.
  • When CMOS output type is selected.
  • See Fig. 9. tSCKH(8) (5/3)tCYC tSCKH(8) (43/3)tCYC Serial input Data setup time tsDI(4) SO9(P25), SI9(P26)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 9. 2.7 to 5.5 0.03 μs Data hold time thDI(4) 0.03 Serial output Output delay time tdDO(6) SO9(P25), SI9(P26)
  • Must be specified with respect to falling edge of SIOCLK.
  • Must be specified as the time to the beginning of output state change in open drain output mode
  • See Fig. 9. 2.7 to 5.5 (1/3)tCYC +0.05 Note 4-4-3: When using the serial clock output, make sure that the load at the SCK9 (P27) pin meets the following conditions: Clock rise time tSCKR < 0.037μs (see Figure 12.) at Ta=+25°C, VDD=3.3V

No.A1453-20/27 Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit High/low level pulse width tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27), INT6(P20), INT7(P24)

  • Interrupt source flag can be set.
  • Event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tCYC tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.7 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.7 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.7 to 5.5 256 tPIL(5) RMIN(P73) Recognized by the infrared remote control receiver circuit as a signal 2.7 to 5.5 4 RMCK (Note 5-1) tPIL(6) RES Resetting is enabled. 2.7 to 5.5 200 μs Note 5-1: Represents the period of the reference clock (1 tCYC to 128 tCYC or the source frequency of the subclock) for the infrared remote control receiver circuit. AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Resolution N AN0(P00) to AN7(P07), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) 3.0 to 5.5 8 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 ±1.5 LSB Conversion time TCAD AD conversion time=32 ×tCYC (when ADCR2=0) (Note 6-2) 4.5 to 5.5 15.68 (tCYC= 0.490µs) 97.92 (tCYC= 3.06µs) μs 3.0 to 5.5 23.52 (tCYC= 0.735µs) 97.92 (tCYC= 3.06µs) AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) 4.5 to 5.5 18.82 (tCYC= 0.294µs) 97.92 (tCYC= 1.53µs) 3.0 to 5.5 47.04 (tCYC= 0.735µs) 97.92 (tCYC= 1.53µs) Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V Analog port input current IAINH VAIN=V DD 3.0 to 5.5 1 μA IAINL VAIN=V SS 3.0 to 5.5 -1 Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the period from the time when an instruction for starting a conversion process is issued to the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value.

No.A1453-21/27 Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Normal mode consumption current (Note 7-1) IDDOP(1) VDD1 =VDD2 =VDD3

  • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation stopped
  • Internal RC oscillation stopped
  • USB circuit stopped
  • 1/1 frequency division ratio 4.5 to 5.5 11 27 mA IDDOP(2) 3.0 to 3.6 6.2 16 IDDOP(3)
  • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation mode active
  • Internal RC oscillation stopped
  • USB circuit active
  • 1/1 frequency division ratio 4.5 to 5.5 16 37 IDDOP(4) 3.0 to 3.6 8.0 21 IDDOP(5) • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 6MHz side
  • Internal RC oscillation stopped
  • 1/2 frequency division ratio 4.5 to 5.5 7.2 17 IDDOP(6) 3.0 to 3.6 4.4 11 IDDOP(7) 2.7 to 3.0 3.6 8.2 IDDOP(8) • FmCF=0Hz (oscillation stopped)
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to internal RC oscillation
  • 1/2 frequency division ratio 4.5 to 5.5 0.77 3.7 IDDOP(9) 3.0 to 3.6 0.43 2.0 IDDOP(10) 2.7 to 3.0 0.36 1.6 IDDOP(11)
  • FmCF=0Hz (oscillation stopped)
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to crystal oscillation side (32.768kHz)
  • Internal RC oscillation stopped
  • 1/2 frequency division ratio 4.5 to 5.5 47 184 μA IDDOP(12) 3.0 to 3.6 19 65 IDDOP(13) 2.7 to 3.0 15 51 HALT mode consumption current (Note7-1) IDDHALT(1)
  • HALT mode
  • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation stopped
  • Internal RC oscillation stopped
  • USB circuit stopped
  • 1/1 frequency division ratio 4.5 to 5.5 4.9 12 mA IDDHALT(2) 3.0 to 3.6 2.7 6.4 IDDHALT(3)
  • HALT mode
  • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation mode active
  • Internal RC oscillation stopped
  • USB circuit active
  • 1/1 frequency division ratio 4.5 to 5.5 9.5 23 IDDHALT(4) 3.0 to 3.6 4.7 12 IDDHALT(5)
  • HALT mode
  • FmCF=12MHz ceramic oscillation mode
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 6MHz side
  • Internal RC oscillation stopped
  • 1/2 frequency division ratio 4.5 to 5.5 3.0 7.3 IDDHALT(6) 3.0 to 3.6 1.6 3.8 IDDHALT(7) 2.7 to 3.0 1.3 2.9 IDDHALT(8) • HALT mode
  • FmCF=0Hz (oscillation stopped)
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to internal RC oscillation
  • 1/2 frequency division ratio 4.5 to 5.5 0.41 2.0 IDDHALT(9) 3.0 to 3.6 0.20 0.95 IDDHALT(10) 2.7 to 3.0 0.17 0.70 Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page.

No.A1453-22/27 Continued from preceding page. Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit HALT mode consumption current (Note 7-1) IDDHALT(11) VDD1 =VDD2 =VDD3

  • HALT mode
  • FmCF=0Hz (oscillation stopped)
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to crystal oscillation side (32.768kHz)
  • Internal RC oscillation stopped
  • 1/2 frequency division ratio 4.5 to 5.5 31 132 μA IDDHALT(12) 3.0 to 3.6 9.1 53 IDDHALT(13) 2.7 to 3.0 6.3 42 HOLD mode consumption current IDDHOLD(1) V DD1 • HOLD mode
  • CF1=VDD or open (External clock mode) 4.5 to 5.5 0.24 72 IDDHOLD(2) 3.0 to 3.6 0.12 38 IDDHOLD(3) 2.7 to 3.0 0.11 33 Timer HOLD mode consumption current IDDHOLD(4) • Timer HOLD mode
  • CF1=VDD or open (External clock mode)
  • FsX’tal=32.768kHz crystal oscillation mode 4.5 to 5.5 26 115 IDDHOLD(5) 3.0 to 3.6 6.1 50 IDDHOLD(6) 2.7 to 3.0 3.8 40 Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. USB Characteristics and Timing at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Conditions Specification min typ max unit High level output V OH(USB) • 15kΩ±5% to GND 2.8 3.6 V Low level output V OL(USB) • 1.5kΩ±5% to 3.6V 0.0 0.3 V Output signal crossover voltage V CRS 1.3 2.0 V Differential input sensitivity V DI • ⏐(UHD+)-(UHD-)⏐ 0.2 V Differential input common mode range V CM 0.8 2.5 V High level input V IH(USB) 2.0 V Low level input V IL(USB) 0.8 V USB data rise time t R • RS=33Ω, CL=50pF 4 20 ns USB data fall time t F • RS=33Ω, CL=50pF 4 20 ns F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Onboard programming current IDDFW(1) V DD1 • Excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 mA Programming time tFW(1) • Erase operation 3.0 to 5.5 20 30 ms tFW(2) • Write operation 40 60 μs Main System Clock Oscillation The constant values of the oscillator and oscillation circuit for the main and system clocks must be determined after exercising extensive oscillation evaluation tests. For an application in which the USB host function is to be used, use an oscillator having the accuracy and precision that satisfy the USB specifications. The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 4):
  • Till the oscillation gets stabilized after VDD goes above the operating voltage lower limit.
  • Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed.
  • Till the oscillation gets stabilized after the HOLD mode is released.
  • Till the oscillation gets stabilized after the X'tal HOLD mode is released with CFSTOP (OCR register, bit 0) set to 0.

No.A1453-24/27 Reset Time and Oscillation Stabilization Time HOLD Release Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time Operating VDD lower limit Power supply RES Internal RC oscillation CF1, CF2 XT1, XT2 Operating mode Reset time tmsCF tmsX’tal Unpredictable Reset Instruction execution VDD GND Execute oscillation enable instruction. Internal RC oscillation CF1, CF2 XT1, XT2 Operating mode HOLD release signal HOLD release signal valid tmsCF tmsX’tal HOLD HALT * When oscillation is enabled before entry into HOLD mode