LC87F1A32A

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 26

Technical content

Features

Flash ROM 32768  8 bits Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source. Block-erasable in 128 byte units Writable in 2-byte units RAM 2048  9 bits Package Form  SQFP48(77) : Lead-Free, Halogen free product CMOS IC 8-bit Microcontroller with Full-Speed USB 32K-byte Flash ROM / 2048-byte RAM / 48-pin * This product is licensed from Silicon Storage Technology, Inc. (USA). SQFP48(7X7) P27/INT5 P26/INT5 P25/INT5 P24/INT5/SCK4 P23/INT4/SI4/WR P22/INT4/SO4/RD P21/INT4/URX1 P20/INT4/UTX1 P07/AN7/T7O P06/AN6/T6O P05/AN5/CKO P04/AN4 P73/INT3/T0IN/RMIN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 VDD3 VSS3 P34/UFILT P33 P32/DBG2 P31/DBG1 P30/DBG0 P70/INT0/T0LCP/AN8/DPUP P71/INT1/T0HCP/AN9 P72/INT2/T0IN P03/AN3 P02/AN2 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 LC87F1A32A Top view

No.A0704-2/26 Minimum Bus Cycle 83.3ns (CF=12MHz) Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time 250ns (CF=12MHz) Ports  I/O ports Ports whose I/O direction can be designated in 1 bit units 28 (P10 to P17, P20 to P27, P30 to P34, P70 to P73, PWM0, PWM1, XT2) Ports whose I/O direction can be designated in 4 bit units 8 (P00 to P07)  U S B p o r t s 2 ( D + , D - )  Dedicated oscillator ports 2 (CF1, CF2)  Input-only port (also used for oscillation) 1 (XT1)  Reset pins 1 ( RES  Power pins 6 (V SS1 to 3, VDD1 to 3) Timers  Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)  2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register)  Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an-8bit prescaler  2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)  Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)  Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)  Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes

No.A0704-3/26 SIO  SIO0: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 512/3 tCYC 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units)  SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)  SIO4: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 2048 bytes, specifiable in 1 byte units, suspension and resumption of data transmission possible in 1 byte or 2 bytes units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in Full Duplex UART 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Baud rate: 16/3 to 8192/3 tCYC AD Converter: 12 bits  12 channels  12-/8-bit resolution selectable AD converter  Reference-voltage automatic generation control PWM: Multifrequency 12-bit PWM  2 channels Infrared Remote Controller Receiver Circuit 1) Noise rejection function (noise filter time constant: Approx. 120s when the 32.768kHz crystal oscillator is selected as the reference voltage source) 2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding 3) X'tal HOLD mode release function USB Interface (function controller) Compliant with USB 2.0 Full-Speed Supports a maximum of 4 user-defined endpoints. Endpoint EP0 EP1 EP2 EP3 EP4 Transfer Type Control  - - - - Bulk -     Interrupt -     Isochronous -     Max. payload 64 64 64 64 64 Watchdog Timer  External RC watchdog timer  Interrupt and reset signals selectable Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock.

No.A0704-4/26 Interrupts  28 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4/USB bus active/Remote control receive 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/USB bus reset/USB suspend/UART1 receive 8 0003BH H or L SIO1/USB endpoint/USB-SOF/SIO4/UART1 transmit 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0/PWM0/PWM1  Priority Level: X > H > L  Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 1024 levels (the stack is allocated in RAM.) High-speed Multiplication/Division Instructions 16 bits  8 bits (5 tCYC execution time) 24 bits  16 bits (12 tCYC execution time) 16 bits  8 bits (8 tCYC execution time) 24 bits  16 bits (12 tCYC execution time) Oscillation Circuits  RC oscillation circuit (internal): For system clock  CF oscillation circuit: For system clock  Crystal oscillation circuit: For system clock, time-of-day clock  PLL circuit (internal): For USB interface (see Fig.5) Standby Function  HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt.  HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The PLL base clock generator , CF, RC and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an bus active interrupt source established in the USB interface circuit  X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except for reception of a remote control signal. 1) The PLL base clock generator, CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are six ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an bus active interrupt source established in the USB interface circuit (6) Having an interrupt source established in the infrared remote controller receiver circuit.

No.A0704-5/26 Development Tools  On-chip debugger: TCB87 type-B + LC87F1A32A Flash ROM Programming Boards Package Programming boards SQFP48(77) W87F55256SQ Recommended EPROM Programmer Maker Model Supported version Device Flash Support Group, Inc. (Single) AF9708/AF9709/AF9709B (including product of Ando Electric Co., Ltd.) After Rev02.73 LC87F1A32A Our company SKK (SanyoFWS) Application Version: After 1.03 Chip Data Version: After 2.07 LC87F1A32 Package Dimensions unit : mm SPQFP48 7x7 / SQFP48 CASE 131AJ ISSUE A XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data GENERIC MARKING DIAGRAM* *This information is generic. Please refer to device data sheet for actual part marking. XXXXXXXX YMDDD XXXXX = Specific Device Code Y = Year DD = Additional Traceability Data XXXXXXXX YDD 7.0 0.1 0.5 (0.75) 0.10 7.0 0.1 9.0 0.2 9.0 0.2 0.18 +0.08 0.03 0.10

1.7 MAX

(1.5)0.1±0.1 0~10° 0.5 0.2 0.15 0.05 (Unit: mm) 8.40 8.40 0.280.50 1.00 SOLDERING FOOTPRINT* NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

No.A0704-6/26 Pin Assignment SQFP48(77) “Lead-free Type” SQFP48 NAME SQFP48 NAME

1 P73/INT3/T0IN/ RMIN 25 P04/AN4

2 RES 26 P05/AN5/CKO

3 XT1/AN10 27 P06/AN6/T6O

4 XT2/AN11 28 P07/AN7/T7O

5 V SS1 29 P20/INT4/UTX1

6 CF1 30 P21/INT4/URX1

7 CF2 31 P22/INT4/SO4/ RD

8 V DD1 32 P23/INT4/SI4/ WR

9 P10/SO0 33 P24/INT5/SCK4

10 P11/SI0/SB0 34 P25/INT5

11 P12/SCK0 35 P26/INT5

12 P13/SO1 36 P27/INT5

13 P14/SI1/SB1 37 D-

14 P15/SCK1 38 D+

15 P16/T1PWML 39 V DD3

16 P17/T1PWMH/BUZ 40 V SS3

17 PWM1 41 P34/UFILT

18 PWM0 42 P33

19 V DD2 43 P32/DBGP2

20 V SS2 44 P31/ DBGP1

21 P00/AN0 45 P30/ DBGP0

22 P01/AN1 46 P70/INT0/T0LCP/AN8/DPUP

23 P02/AN2 47 P71/INT1/T0HCP/AN9

24 P03/AN3 48 P72/INT2/T0IN

No.A0704-7/26 System Block Diagram Interrupt control FROM Standby control Clock generator CF X’tal RC IR PLA PC Bus interface Port 0 Port 1 ACC B register C register ALU PSW RAR RAM Stack pointer Watchdog timer PWM1 Timer 6 INT0 to 5 Noise filter SIO0 Port 2 USB PLL Port 7 Port 3 ADC SIO1 Timer 0 Timer 1 USB interface Timer 7 Base timer PWM0 UART1 SIO4 On-chip debugger Infrared remote controller receiver circuit

No.A0704-8/26 Pin Description Pin Name I/O Description Option VSS1, VSS2, VSS3 - - power supply pin No VDD1, VDD2 - + power supply pin No VDD3 - USB reference voltage pin Yes Port 0 I/O • 8-bit I/O port

• I/O specifiable in 4-bit units
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
• Pins functions AD converter input port: AN0 to AN7 (P00 to P07) P05: System Clock Output P06: Timer 6 toggle outputs P07: Timer 7 toggle outputs Yes P00 to P07 Port 1 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output/beeper output Yes P10 to P17 Port 2 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P20: UART1 transmit P21: UART1 receive P22: SIO4 date I/O/parallel interface RD output P23: SIO4 date I/O/parallel interface WR output P24: SIO4 clock I/O Interrupt acknowledge type Yes P20 to P27 Rising Falling Rising & Falling H level L level INT4 enable enable enable disable disable INT5 enable enable enable disable disable Continued on next page.

No.A0704-9/26 Continued from preceding page. Pin Name I/O Description Option Port 3 I/O • 5-bit I/O port

• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions P34: USB interface PLL filter pin (see Fig.5) Onchip debugger pin: DBGP0 to DBGP2 (P30 to P32) Yes P30 to P34 Port 7 I/O • 4-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output/ D+ 1.5k pull-up resistor connect pin P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/ High speed clock counter input P73: INT3 input (input with a noise filter)/timer 0 event input/ timer 0H capture input/ infrared remote controller receiver input AD converter input port: AN8(P70), AN9(P71) Interrupt acknowledge type No P70 to P73 Rising Falling Rising & Falling H level L level INT0 enable enable disable enable enable INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable PWM0 PWM1 I/O • PWM0 and PWM1 output port
• General-purpose input port No D- I/O • USB data I/O pin D-
• General-purpose I/O port No D+ I/O • USB data I/O pin D+
• General-purpose I/O port No RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input pin
• Pin functions General-purpose input port AD converter input port: AN10 Must be connected to VDD1 if not to be used. No XT2 I/O 32.768kHz crystal oscillator output pin
• Pin functions General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used. No CF1 Input Ceramic resonator input pin No CF2 Output Ceramic resonator output pin No

No.A0704-10/26 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of Option Type Output Type Pull-up Resistor P00 to P07 1 bit 1 CMOS Programmable (Note 1)

2 Nch-open drain No

2 Nch-open drain Programmable

P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable PWM0, PWM1 - No CMOS No D+, D- - No CMOS No XT1 - No Input only No XT2 - No 32.768kHz crystal oscillator output (Nch-open drain when in general-purpose output mode) No Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). Power Pin Treatment Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of output ports is supplied by their backup capacitors. Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode. VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply For backup LSI LSI VSS1 VSS2V SS3 VDD1 VDD2 VDD3 Power supply For backup

No.A0704-11/26 USB Reference Power Option When a voltage 4.4 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the reference voltage for USB port output is generated. The active/inactive state of reference voltage circuit can be switched by the option select. The procedure for marking the option selection is described below. (1) (2) (3) (4) Option select USB Regulator USE USE USE NONUSE USB Regulator at HOLD mode USE NONUSE NONUSE NONUSE USB Regulator at HALT mode USE NONUSE USE NONUSE Reference voltage circuit state Normal state active active active inactive HOLD mode active inactive inactive inactive HALT mode active inactive active inactive When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is equal to VDD1. Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode. When the reference voltage circuit is activated, the current drain increase by approximately 100A compared with when the reference voltage circuit is inactive. Example 1: VDD1=VDD2=3.3V Inactivating the reference voltage circuit (selection (4)). Connecting VDD3 to VDD1 and VDD2. Example 2: VDD1=VDD2=5.0V Activating the reference voltage circuit (selection (1)). Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS. VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply 3.3V For backup LSI UFILT To USB connector 27 to 33 5pF 2.2F 1.5k P70 VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply For backup LSI UFILT 2.2F To USB connector27 to 33 5pF 1.5k P70 2.2F 0.1µF

No.A0704-12/26 Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Maximum supply voltage VDD max V DD1, VDD2, VDD3 V DD1=VDD2=VDD3 0.3 +6.5 V Input voltage V I(1) XT1, CF1 0.3 V DD+0.3 Input/output voltage VIO(1) Ports 0, 1, 2, 3, 7 PWM0, PWM1, XT2 0.3 V DD+0.3 High level output current Peak output current IOPH(1) Ports 0, 1, 2 • When CMOS output type is selected

• Per 1 applicable pin 10 mA IOPH(2) PWM0, PWM1 Per 1 applicable pin 20 IOPH(3) Ports 3 P71 to P73
• When CMOS output type is selected
• Per 1 applicable pin Average output current (Note 1-1) IOMH(1) Ports 0, 1, 2 • When CMOS output type is selected
• Per 1 applicable pin 7.5 IOMH(2) PWM0, PWM1 Per 1 applicable pin 15 IOMH(3) Ports 3 P71 to P73
• When CMOS output type is selected
• Per 1 applicable pin Total output current IOAH(1) Ports 0, 2 Total of all applicable pins 25 IOAH(2) Port 1 PWM0, PWM1 Total of all applicable pins 25 IOAH(3) Ports 0, 1, 2 PWM0, PWM1 Total of all applicable pins 45 IOAH(4) Ports 3 P71 to P73 Total of all applicable pins 10 IOAH(5) D+, D  Total of all applicable pins 25 Low level output current Peak output current IOPL(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin IOPL(2) P00, P01 Per 1 applicable pin 30 IOPL(3) Ports 3, 7, XT2 Per 1 applicable pin 10 Average output current (Note 1-1) IOML(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin IOML(2) P00, P01 Per 1 applicable pin 20 IOML(3) Ports 3, 7, XT2 Per 1 applicable pin 7.5 Total output current IOAL(1) Ports 0, 2 Total of all applicable pins 45 IOAL(2) Port 1 PWM0, PWM1 Total of all applicable pins 45 IOAL(3) Ports 0, 1, 2 PWM0, PWM1 Total of all applicable pins 80 IOAL(4) Ports 3, 7, XT2 Total of all applicable pins 15 IOAL(5) D+, D  Total of all applicable pins 25 Allowable power Dissipation Pd max SQFP48(7 7) Ta=-30to+70 C 190 mW Operating ambient Temperature Topr 30 +70 Storage ambient temperature Tstg 55 +125 Note 1-1: The mean output current is a mean value measured over 100ms. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

No.A0704-13/26 Allowable Operating Conditions at Ta = 30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Operating supply voltage (Note 2-1) VDD(1) V DD1=VDD2=VDD3 0.245 s  tCYC  200s 3.0 5.5 V 0.245s  tCYC  0.383s USB circuit operation mode 3.0 5.5 0.490s  tCYC  200s Except for onboard programming 2.7 5.5 Memory sustaining supply voltage VHD V DD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode. 2.0 5.5 High level input voltage VIH(1) Ports 0, 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 2.7 to 5.5 0.3VDD +0.7 VDD VIH(2) Port 70 watchdog timer side 2.7 to 5.5 0.9V DD V DD VIH(3) XT1, XT2, CF1, RES 2.7 to 5.5 0.75V DD V DD Low level input voltage VIL(1) Ports 1, 2, 3 P71 to P73 P70 port input/ interrupt side 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(2) 2.7 to 4.0 V SS 0.2V DD VIL(3) Port 0 PWM0, PWM1 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(4) 2.7 to 4.0 V SS 0.2V DD VIL(5) Port 70 watchdog timer side 2.7 to 5.5 V SS 0.8VDD 1.0 VIL(6) XT1, XT2, CF1, RES 2.7 to 5.5 V SS 0.25VDD Instruction cycle time (Note 2-2) tCYC 3.0 to 5.5 0.245 200 s Except for onboard programming 2.7 to 5.5 0.490 200 External system clock frequency FEXCF(1) CF1 • CF2 pin open

• System clock frequency division ratio=1/1
• External system clock duty =505% 3.0 to 5.5 0.1 12 MHz
• CF2 pin open
• System clock frequency division ratio=1/1
• External system clock duty =505% 2.7 to 5.5 0.1 6 Oscillation frequency range (Note 2-3) FmCF(1) CF1, CF2 12 MHz ceramic oscillation See Fig. 1. 3.0 to 5.5 12 MHzFmCF(2) CF1, CF2 6 MHz ceramic oscillation See Fig. 1. 2.7 to 5.5 6 FsX’tal XT1, XT2 32.768kHz crystal oscillation Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recomme nded Operating Ranges limits mayaffect device reliability.

No.A0704-14/26 Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit High level input current IIH(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 D+, D Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) 2.7 to 5.5 1 IIH(2) XT1, XT2 For input port specification VIN=VDD 2.7 to 5.5 1 IIH(3) CF1 V IN=VDD 2.7 to 5.5 15 Low level input current IIL(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 D+, D Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) 2.7 to 5.5 1 IIL(2) XT1, XT2 For input port specification VIN=VSS 2.7 to 5.5 1 IIL(3) CF1 V IN=VSS 2.7 to 5.5 15 High level output voltage VOH(1) Ports 0, 1, 2, 3 P71 to P73 IOH=1mA 4.5 to 5.5 V DD1 V VOH(2) IOH=0.4mA 3.0 to 5.5 V DD0.4 VOH(3) IOH=0.2mA 2.7 to 5.5 V DD0.4 VOH(4) PWM0, PWM1 P05 (CK0 when using system clock output function) IOH=10mA 4.5 to 5.5 V DD1.5 VOH(5) IOH=1.6mA 3.0 to 5.5 V DD0.4 VOH(6) IOH=1mA 2.7 to 5.5 V DD0.4 Low level output voltage VOL(1) P00, P01 I OL=30mA 4.5 to 5.5 1.5 VOL(2) IOL=5mA 3.0 to 5.5 0.4 VOL(3) IOL=2.5mA 2.7 to 5.5 0.4 VOL(4) Ports 0, 1, 2 PWM0, PWM1 XT2 IOL=10mA 4.5 to 5.5 1.5 VOL(5) IOL=1.6mA 3.0 to 5.5 0.4 VOL(6) IOL=1mA 2.7 to 5.5 0.4 VOL(7) Ports 3, 7 I OL=1.6mA 3.0 to 5.5 0.4 VOL(8) IOL=1mA 2.7 to 5.5 0.4 Pull-up resistance Rpu(1) Ports 0, 1, 2, 3 Port 7 VOH=0.9VDD 4.5 to 5.5 15 35 80 Rpu(2) 2.7 to 5.5 18 50 150 Hysteresis voltage VHYS RES Ports 1, 2, 3, 7 2.7 to 5.5 0.1V DD V Pin capacitance CP All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25C 2.7 to 5.5 10 pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per formance may not be indicated by the Electrical Characteristics if operated under different conditions.

No.A0704-15/26 Serial I/O Characteristics at Ta = 30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(1) SCK0(P12) See Fig.9. 2.7 to 5.5 tCYC Low level pulse width tSCKL(1) 1 High level pulse width tSCKH(1) tSCKHA(1a) • Continuous data transmission/ reception mode

• USB nor SIO4 are not in use simultaneous.
• See Fig.8.
• (Note 4-1-2) tSCKHA(1b) • Continuous data transmission/reception mode
• USB is in use simultaneous.
• SIO4 is not in use simultaneous.
• See Fig.8.
• (Note 4-1-2) tSCKHA(1c) • Continuous data transmission/ reception mode
• USB and SIO4 are in use simultaneous.
• See Fig.8.
• (Note 4-1-2) Output clock Frequency tSCK(2) SCK0(P12) • CMOS output selected
• See Fig.8. 2.7 to 5.5 Low level pulse width tSCKL(2) tSCK High level pulse width tSCKH(2) tSCKHA(2a) • Continuous data transmission/ reception mode
• USB nor SIO4 are not in use simultaneous.
• CMOS output selected
• See Fig.8. tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tCYC tSCKHA(2b) • Continuous data transmission/ reception mode
• USB is in use simultaneous.
• SIO4 is not in use simultaneous.
• CMOS output selected
• See Fig.8. tSCKH(2) +2tCYC tSCKH(2) +(19/3) tCYC tSCKHA(2c) • Continuous data transmission/ reception mode
• USB and SIO4 are in use simultaneous.
• CMOS output selected
• See Fig.8. tSCKH(2) +2tCYC tSCKH(2) +(25/3) tCYC Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page.

No.A0704-16/26 Continued from preceding page. Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial input Data setup time tsDI(1) SB0(P11), SI0(P11)

• Must be specified with respect to rising edge of SIOCLK.
• See Fig.8. 2.7 to 5.5 0.03 Data hold time thDI(1) 2.7 to 5.5 0.03 Serial output Input clock Output delay time tdD0(1) SO0(P10), SB0(P11)
• Continuous data transmission/reception mode
• (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3) 2.7 to 5.5 1tCYC +0.05 Output clock tdD0(3) (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.8. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(3) SCK1(P15) See Fig.8. 2.7 to 5.5 tCYC Low level pulse width tSCKL(3) 1 High level pulse width tSCKH(3) 1 Output clock Frequency tSCK(4) SCK1(P15) • CMOS output selected
• See Fig.8. 2.7 to 5.5 Low level pulse width tSCKL(4) 1/2 tSCKHigh level pulse width tSCKH(4) Serial input Data setup time tsDI(2) SB1(P14), SI1(P14)
• Must be specified with respect to rising edge of SIOCLK.
• See Fig.8. 2.7 to 5.5 0.03 Data hold time thDI(2) 2.7 to 5.5 0.03 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
• Must be specified with respect to falling edge of SIOCLK.
• Must be specified as the time to the beginning of output state change in open drain output mode.
• See Fig.8. 2.7 to 5.5 (1/3)tCYC +0.05 Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.

No.A0704-17/26 3. SIO4 Serial I/O Characteristics (Note 4-3-1) Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(5) SCK4(P24) See Fig.8. 2.7 to 5.5 tCYC Low level pulse width tSCKL(5) 1 High level pulse width tSCKH(5) tSCKHA(5a) • USB nor continuous data Transmission/reception mode Of SIO0 are not in use simultaneous.

• See Fig.8.
• (Note 4-3-2) tSCKHA(5b) • USB is in use simultaneous.
• Do not use SIO0 continuous data transmission mode at the same time.
• See Fig.8.
• (Note 4-3-2) tSCKHA(5c) • USB and continuous data transmission/ reception mode of SIO0 are in use simultaneous.
• See Fig.8.
• (Note 4-3-2) Output clock Frequency tSCK(6) SCK4(P24) • CMOS output selected
• See Fig.8 2.7 to 5.5 Low level pulse width tSCKL(6) tSCK High level pulse width tSCKH(6) tSCKHA(6a) • USB, AIF nor continuous data transmission/reception mode of SIO0 are not in use simultaneous.
• CMOS output selected
• See Fig.8. tSCKH(6) +(5/3) tCYC tSCKH(6) +(10/3) tCYC tCYC tSCKHA(6b) • USB is in use simultaneous.
• Do not use SIO0 continuous data transmission mode at the same time.
• CMOS output selected
• See Fig8. tSCKH(6) +(5/3) tCYC tSCKH(6) +(19/3) tCYC tSCKHA(6c) • USB and continuous data transmission/reception mode of SIO0 are in use simultaneous.
• CMOS output selected
• See Fig.8. tSCKH(6) +(5/3) tCYC tSCKH(6) +(28/3) tCYC Serial input Data setup time tsDI(3) SO4(P22), SI4(P23)
• Must be specified with respect to rising edge of SIOCLK.
• See Fig.8. 2.7 to 5.5 0.03 Data hold time thDI(3) 2.7 to 5.5 0.03 Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input in continuous trans/rec mode, a time from SI4RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page.

No.A0704-18/26 Continued from preceding page. Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Serial output Output delay time tdD0(5) SO4(P22), SI4(P23)

• Must be specified with respect to rising edge of SIOCLK.
• Must be specified as the time to the beginning of output state change in open drain output mode.
• See Fig.8. 2.7 to 5.5 (1/3)tCYC +0.05 s Pulse Input Conditions at Ta = 30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit High/low level pulse width tP1H(1) tP1L(1) INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27)
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tCYC tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is 1/1
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.7 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is 1/32
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.7 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is 1/128
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.7 to 5.5 256 tPIL(5) RMIN(P73) Recognized by the infrared remote controller receiver circuit as a signal. 2.7 to 5.5 4 RMC K (Note 5- tPIL(6) RES Resetting is enabled. 2.7 to 5.5 200 s Note5-1: Represents the period of the reference clock (1 tCYC to 128 tCYC or the source frequency of the subclock) for the infrared remote controller receiver circuit.

No.A0704-19/26 AD Converter Characteristics at Ta= 30C to +70C, VSS1 = VSS2 = VSS3 = 0V <12-bits AD Converter Mode> Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Resolution N AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) 3.0 to 5.5 12 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 16 LSB Conversion time TCAD See conversion time calculation formulas. (Note 6-2) 4.0 to 5.5 32 115 3.0 to 5.5 64 115 Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V Analog port input current IAINH VAIN=V DD 3.0 to 5.5 1 IAINL VAIN=V SS 3.0 to 5.5 1 <8-bits AD Converter Mode> Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Resolution N AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) 3.0 to 5.5 8 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 1.5 LSB Conversion time TCAD See conversion time calculation formulas. (Note 6-2) 4.0 to 5.5 20 90 3.0 to 5.5 40 90 Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V Analog port input current IAINH VAIN=V DD 3.0 to 5.5 1 IAINL VAIN=V SS 3.0 to 5.5 1 Conversion time calculation formulas: 12-bits AD Converter Mode: TCAD (Conversion time) = ((52/(AD division ratio))+2)  (1/3)  tCYC 8-bits AD Converter Mode: TCAD (Conversion time) = ((32/(AD division ratio))+2)  (1/3)  tCYC <Recommended Operating Conditions> External oscillator FmCF[MHz] Supply Voltage Range VDD[V] System Clock Division (SYSDIV) Cycle Time tCYC [ns] AD Frequency Division Ratio (ADDIV) Conversion Time (TCAD)[s] 12-bit AD 8-bit AD 4.0 to 5.5 1/1 250 1/8 34.8 21.5 3.0 to 5.5 1/1 250 1/16 69.5 42.8 Note 6-1: The quantization error (1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.

No.A0704-20/26 Consumption Current Characteristics at Ta = 30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit Normal mode consumption current (Note 7-1) IDDOP(1) VDD1 =VDD2 =VDD3

• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation stopped
• Internal RC oscillation stopped
• USB circuit stopped
• 1/1 frequency division ration 4.4 to 5.5 9.8 24 mA IDDOP(2) 3.0 to 3.6 5.6 14 IDDOP(3)
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation mode
• Internal RC oscillation stopped
• USB circuit operation mode
• 1/1 frequency division ration 4.4 to 5.5 14 34 IDDOP(4) 3.0 to 3.6 7.7 19 IDDOP(5) • FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
• Internal RC oscillation stopped
• 1/2 frequency division ration 4.4 to 5.5 6.1 14 IDDOP(6) 3.0 to 3.6 3.7 8.5 IDDOP(7) 2.7 to 3.0 3.0 6.7 IDDOP(8) • FmCF=0MHz (oscillation stopped)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• 1/2 frequency division ration 4.4 to 5.5 0.63 3.0 IDDOP(9) 3.0 to 3.6 0.35 1.6 IDDOP(10) 2.7 to 3.0 0.30 1.3 IDDOP(11) • FmCF=0MHz (oscillation stopped)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
• 1/2 frequency division ration 4.4 to 5.5 39 150 IDDOP(12) 3.0 to 3.6 17 58 IDDOP(13) 2.7 to 3.0 14 43 HALT mode consumption current (Note 7-1) IDDHALT(1) VDD1 =VDD2 =VDD3
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation stopped
• Internal RC oscillation stopped
• USB circuit stopped
• 1/1 frequency division ration 4.4 to 5.5 4.9 12 mA IDDHALT(2) 3.0 to 3.6 2.6 6.3 IDDHALT(3)
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal PLL oscillation mode
• Internal RC oscillation stopped
• USB circuit operation mode
• 1/1 frequency division ration 4.4 to 5.5 8.9 23 IDDHALT(4) 3.0 to 3.6 4.6 12 IDDHALT(5)
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
• Internal RC oscillation stopped
• 1/2 frequency division ration 4.4 to 5.5 3.0 7.2 IDDHALT(6) 3.0 to 3.6 1.6 3.8 IDDHALT(7) 2.7 to 3.0 1.3 2.9 Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page.

No.A0704-21/26 Continued from preceding page. Parameter Symbol Pin/ Remarks Conditions Specification VDD[V] min typ max unit HALT mode consumption current (Note 7-1) IDDHALT(8) V DD1 =VDD2 =VDD3

• HALT mode
• FmCF=0MHz (oscillation stopped)
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• 1/2 frequency division ration 4.4 to 5.5 0.37 1.8 mA IDDHALT(9) 3.0 to 3.6 0.18 0.83 IDDHALT(10) 2.7 to 3.0 0.15 0.62 IDDHALT(11)
• HALT mode
• FmCF=0MHz (oscillation stopped)
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
• 1/2 frequency division ration 4.4 to 5.5 24 93 IDDHALT(12) 3.0 to 3.6 7.9 33 IDDHALT(13) 2.7 to 3.0 5.8 22 HOLD mode consumption current IDDHOLD(1) V DD1 HOLD mode
• CF1=VDD or open (External clock mode) 4.4 to 5.5 0.08 24 IDDHOLD(2) 3.0 to 3.6 0.03 11 IDDHOLD(3) 2.7 to 3.0 0.02 9.6 Timer HOLD mode consumption current IDDHOLD(4) V DD1 Timer HOLD mode
• CF1=VDD or open (External clock mode)
• FsX’tal=32.768kHz crystal oscillation mode 4.4 to 5.5 19 77 IDDHOLD(5) 3.0 to 3.6 5.1 23 IDDHOLD(6) 2.7 to 3.0 3.3 14 Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. USB Characteristics and Timing at Ta = 0°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Conditions Specification min typ max unit High level output V OH(USB) • 15k ±5% to GND 2.8 3.6 V Low level output V OL(USB) • 1.5k ±5% to 3.6 V 0.0 0.3 V Output signal crossover voltage V CRS 1.3 2.0 V Differential input sensitivity V DI • |(D+) (D)| 0.2 V Differential input common mode range V CM 0.8 2.5 V High level input V IH(USB) 2.0 V Low level input V IL(USB) 0.8 V USB data rise time t R • R S=27 to 33, CL=50pF
• VDD3=3.0 to 3.6V 4 20 ns USB data fall time t F • R S=27 to 33, CL=50pF
• VDD3=3.0 to 3.6V 4 20 ns F-ROM Programming Characteristics at Ta = +10C to +55C, VSS1 = VSS2= VSS3 =0V Parameter Symbol Pin Conditions Specification VDD[V] min typ max unit Onboard programming current IDDFW(1) V DD1 • Excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 mA Programming time tFW(1) • Erase operation 3.0 to 5.5 20 30 ms tFW(2) • Write operation 40 60 s

No.A0704-23/26 Reset Time and Oscillation Stabilization Time HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time Operating VDD lower limit Power Supply RES Internal RC oscillation CF1, CF2 XT1, XT2 Operating mode Reset time tmsCF tmsX’tal Unpredictable Reset Instruction execution VDD GND Internal RC oscillation CF1, CF2 XT1, XT2 Operating mode HOLD reset signal HOLD reset signal valid tmsCF tmsX’tal HOLD HALT

No.A0704-26/26

ORDERING INFORMATION

Device Package Shipping (Qty / Packing) LC87F1A32AUWA-2H SPQFP-48 / SQFP-48 (Pb-Free / Halogen Free) 2500 / Tray JEDEC PS ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A lis ting of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended tosupport or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject t oa l l applicable copyright laws and is not for resale in any manner.