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Technical content

Features

 ROM

  • 16384×8 bits RAM
  • 512 × 9 bits Minimum Bus Cycle
  • 250ns (4MHz) VDD=2.4V to 3.6V Note: The bus cycle time here refers to the ROM read speed. Minimum instruction cycle time
  • 750ns (4MHz) VDD=2.4 to 3.6V Temperature range
  • -40°C to +85°C CMOS IC 16K-byte ROM and 512-byte RAM integrated 8-bit 1-chip Microcontroller

No.A1840-2/29 Ports

  • Input/output ports Data direction programmable for each bit individually: 21 (P0n, P1n, P30, P70-P73) Other function LCD ports (segment output): 8 (P1n)
  • LCD ports & General I/O ports Segment output: 32 (S00-S31) Common output: 4 (COM0-COM3) Bias terminals for LCD driver 5 (V1-V3, CUP1, CUP2) Other functions Input/output ports: 36 (LPAn, LPBn, LPCn, LPLn, P1n)
  • Oscillator pins: 4 (CF1, CF2, XT1, XT2)
  • Reset pin: 1 ( RES
  • Power supply: 5 (V SS1-2, VDD1-2, V2) 1 (VDC) LCD Controller (1) Seven display modes are available (2) Duty 1/3duty, 1/4duty (3) Bias 1/2bias, 1/3bias (4) Segment output can be switched to general purpose input/output ports. (5) LCD frame rate frequency: 16 to 85.3Hz (programmable) (6) LCD power range 1) 1/3bias V1 : 1.2V to 1.8V V2 : 2.4V to 3.6V V3 : 3.6V to 5.4V Please use the LCD panel for V2 (=V DD)× 1.5[V], when you select 1/3bias. For example, if the power supply voltage is 3.0V, the LCD panel must be 4.5V. 2) 1/2bias V1 : 1.2V to 1.8V V2 : 2.4V to 3.6V V3 : 2.4V to 3.6V (connect V2 and V3) Please use the LCD panel for V2 (=V DD)[V], when you select 1/3bias. For example, if the power supply voltage is 3.0V, the LCD panel must be 3.0V. Timers
  • Timer 0: 16 bit timer / counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit Counter with 8-bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register
  • Timer 1: PWM / 16 bit timer/ counter with toggle output function Mode 0: 2 channel 8 bit timer/ counter (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer/ counter (with toggle output) Toggle output from lower 8 bits is also possible. Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM.
  • Timer 4: 8-bit timer with 6-bit prescaler
  • Timer 5: 8-bit timer with 6-bit prescaler
  • Timer 6: 8-bit timer with 6-bit prescaler (with toggle output)
  • Timer 7: 8-bit timer with 6-bit prescaler (with toggle output)
  • Base Timer (1) The clock signal can be selected from any of the following: Sub-clock (32.768kHz crystal oscillator / Slow RC oscillation), system clock, and prescaler output from timer 0. (2) Interrupts of five different time intervals are possible.

No.A1840-3/29 High-speed Clock Counter (1) Can count clocks with a maximum clock rate of 8MHz (at a main clock of 4MHz). (2) Can generate output real-time. Serial-interface

  • SIO 0: 8 bit synchronous serial interface (1) Synchronous 8-bit serial I/O (2- or 3-wire system, clock rates of (4/3) to (512/3) tCYC) (2) Continuous data transmission/reception (Variable length data transmission in bit units from 1 to 256 bits, clock rates of (4/3) to (512/3) tCYC) (3) Bi-phase modulation (Manchester, Bi-phase-Space) data transmission (4) LSB first / MSB first is selectable (5) SPI_function: serial interface that can release HOLD/X’tal HOLD mode after receiving 1-byte (8-bit clock).
  • SIO 1: 8 bit asynchronous / synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2–512 tCYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8–2048 tCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2–512 tCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) UART
  • Full duplex
  • 7/8/9 bit data bits selectable
  • 1 stop bit (2-bit in continuous data transmission)
  • Built-in baudrate generator
  • Operating mode: Programmable transfer mode, fixed-rate transfer mode
  • Transmission data conversion: Normal (NRZ), Manchester encoding AD converter: 12 bits/8 bits × 7 channels
  • 12 bits/8 bits AD converter resolution selectable Remote Control Receiver Circuit (Connected to P73 / INT3 / T0IN terminal)
  • Noise rejection function (Noise rejection filter’s time constant can be selected from 1 / 32 / 128 tCYC) Watchdog Timer
  • Watchdog timer can produce interrupt or system reset.
  • Watchdog timer has two types. (1) Use an external RC circuit (2) Use the microcontroller’s basetimer
  • Watchdog timer that used basetimer can select only one period (1 / 2 / 4 / 8 s) by the user option. Buzzer Output
  • The buzzer output can transmitted from P17 by using basetimer. Real Time Clock (RTC) (1) Used with a basetimer, it can be used as a century + year + month + day + hour + minute + second counter. (2) Calendar counts up to December 31, 2799 with automatic leap-year calculation. (3) Gregorian calendar capable of keeping GMT (Greenwich Mean Time). Internal Reset Function
  • Power-On-Reset (POR) function − POR resets the system when the power supply voltage is applied.

No.A1840-4/29 Interrupts: 21 sources, 10 vectors (1) Three priority (Low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is postponed. (2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L 4 0001BH H or L INT3/Base timer/RTC 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1-receive 8 0003BH H or L SIO1/UART-send 9 00043H H or L ADC/T6/T7/SPI 10 0004BH H or L Port 0/T4/T5

  • Priority levels X > H > L
  • For equal priority levels, vector with lowest address takes precedence Subroutine Stack Levels: 256 levels max. Stack is located in RAM. High-speed Multiplication/Division Instructions
  • 16 bits × 8 bits (5 tCYC execution time)
  • 24 bits × 16 bits (12 tCYC execution time)
  • 16 bits ÷ 8 bits (8 tCYC execution time)
  • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits
  • On-chip fast RC oscillation (Typical: 500kHz) for system clock use.
  • On-chip slow RC oscillation (Typical: 50kHz) for system clock use.
  • CF oscillation (4MHz) for system clock use. (Rf built in, Rd external)
  • Crystal oscillation (32.768kHz) low speed system clock use. (Rf built in)
  • Frequency variable RC oscillation circuit (internal): For system clock. (1) Adjustable in ±4% (typ.) step from a selected center frequency. (2) Measures oscillation clock using a input signal from XT1 as a reference. System Clock Divider
  • Low power consumption operation is available.
  • Minimum instruction cycle time (750ns, 1.5μs, 3.0μs, 6.0μs, 12μs, 24μs, 48μs, 96μs, 192μs can be switched by program. (when using 4MHz main clock) System Clock Output
  • The system clock output can transmitted from P04.

No.A1840-5/29 Standby Function

  • HALT mode HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but peripheral circuits keep operating (Some parts of serial transfer operation stop.) (1) Oscillation circuits are not stopped automatically. (2) Released by the system reset or interrupts.
  • HOLD mode HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped. (1) CF, RC and crystal oscillation circuits stop automatically. (2) Released by any of the following conditions. 1) Low level input to the reset pin 2) Watchdog timer interrupt 3) Specified level input to one of INT0, INT1, INT2 4) Port 0 interrupt 5) SPI interrupt by receiving 1-byte (8-bit clock)
  • X’tal HOLD mode X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. (1) CF and RC oscillation circuits stop automatically. (2) Crystal oscillator operation is kept in its state at HOLD mode inception. (3) Released by any of the following conditions. 1) Low level input to the reset pin 2) Watchdog timer interrupt 3) Specified level input to one of INT0, INT1, INT2 4) Port 0 interrupt 5) Base-timer interrupt 6) RTC interrupt 7) SPI interrupt by receiving 1-byte (8-bit clock) Shipping Form
  • QIP64E (14×14) (Lead-/Halogen-free type)
  • TQFP64J (7×7) (Lead-/Halogen-free type)
  • SQFP64 (10×10) (Lead-/Halogen-free type)
  • CHIP Development Tools
  • On-chip debugger: TCB87 TypeB+LC87F7932B

No.A1840-6/29 Package Dimensions Package Dimensions unit : mm (typ) unit : mm (typ) 3159A 3289 Package Dimensions unit : mm (typ) 3190A 10.0 10.0 12.0 12.0 0.15 0.5 (1.5)0.1 1.7max 0.180.5 (1.25) 11 6 3348 SANYO : SQFP64(10X10) SANYO : QIP64E(14X14) 14.0 17.2 14.0 17.2 0.150.35 0.8 (2.7) 3.0max 0.1 0.8 (1.0) 11 6 3348 SANYO : TQFP64J(7X7) 7.0 9.0 7.0 9.0 0.125 0.5 0.160.4 (0.5)(1.0) 1.2max 0.1 1 16 3348 1764 3249

No.A1840-7/29 Pin Assignment QIP64E (14×14) Lead-/Halogen-free type” TQFP64J (7×7) Lead-/Halogen-free type” SQFP64 (10×10) Lead-/Halogen-free type” Chip Size: 2.25mm×2.23mm Pad Size/Pitch: LC877917A Top view RES XT1 XT2 VSS1 CF1 CF2 VDD1 P00/UTX1/AN0 P01/RTX1/AN1 P02/AN2 P03/AN3 P04/CKO/AN4 P05 P06/T6O P07/T7O P30 S07/LPA7 S06/LPA6 S05/LPA5 S04/LPA4 S03/LPA3 S02/LPA2 S01/LPA1 S00/LPA0 COM3/LPL3 COM2/LPL2 COM1/LPL1 COM0/LPL0 VDC P70/INT0/T0LCP/AN5 P71/INT1/T0HCP/AN6 P72/INT2/T0IN/NKIN P73/INT3/T0IN VDD2 VSS2 P10/SO0/S24 P11/SI0/SB0/S25 P12/SCK0/S26 P13/SO1/S27 P14/SI1/SB1/S28 P15/SCK1/S29 P16/T1PWML/S30 P17/T1PWMH/BUZ/S31 CUP1 CUP2 S23/LPC7 S22/LPC6 S21/LPC5 S20/LPC4 S19/LPC3 S18/LPC2 S17/LPC1 S16/LPC0 S15/LPB7 S14/LPB6 S13/LPB5 S12/LPB4 S11/LPB3 S10/LPB2 S09/LPB1 S08/LPB0 Jacket Open 63μm Pad Metal 79μm 80μm 96μm 84μm 84μm

No.A1840-8/29 PIN No. NAME PIN NO. NAME

1 P70/INT0/T0LCP/AN5 33 S08/LPB0

2 P71/INT1/T0HCP/AN6 34 S09/LPB1

3 P72/INT2/T0IN/NKIN 35 S10/LPB2

4 P73/INT3/T0IN 36 S11/LPB3

5 V DD2 37 S12/LPB4

6 V SS2 38 S13/LPB5

7 P10/SO0/S24 39 S14/LPB6

8 P11/SI0/SB0/S25 40 S15/LPB7

9 P12/SCK0/S26 41 S16/LPC0

10 P13/SO1/S27 42 S17/LPC1

11 P14/SI1/SB1/S28 43 S18/LPC2

12 P15/SCK1/S29 44 S19/LPC3

13 P16/T1PWML/S30 45 S20/LPC4

14 P17/T1PWMH/BUZ/S31 46 S21/LPC5

15 CUP1 47 S22/LPC6

16 CUP2 48 S23/LPC7

17 VDC 49 RES

18 V1 50 XT1

19 V2 51 XT2

20 V3 52 V SS1

21 COM0/LPL0 53 CF1

22 COM1/LPL1 54 CF2

23 COM2/LPL2 55 V DD1

24 COM3/LPL3 56 P00/UTX1/AN0

25 S00/LPA0 57 P01/RTX1/AN1

26 S01/LPA1 58 P02/AN2

27 S02/LPA2 59 P03/AN3

28 S03/LPA3 60 P04/CKO/AN4

29 S04/LPA4 61 P05

30 S05/LPA5 62 P06/T6O

31 S06/LPA6 63 P07/T7O

32 S07/LPA7 64 P30

No.A1840-9/29 System Block Diagram RES X’tal Interrupt Control Stand-by Control IR PLA ROM PC Bus Interface Port 0 Port 1 SIO0 SIO1 Base Timer LCD Controller INT0 - 3 Noise Rejection Filter Port 3 ACC B Register C Register PSW RAR RAM Stack Pointer Watch Dog Timer ALU Timer 4 Timer 5 Timer 6 Timer 7 Timer 0 Timer 1 CF Fast RC Slow RC UART1 Port 7 Reset circuit (POR) WDT Reset control VMRC Clock Generator RTC ADC

No.A1840-10/29 Pin Assignment Pin name I/O Function Option VSS1, VSS2 - • Power supply (-) No VDD1, VDD2, V2 - • Power supply (+) No VDC - • Internal voltage No CUP1, CUP2 - • Capacitor connecting terminals for step-up/step-down No PORT0 P00 to P07 I/O • 8bit input/output port

  • Data direction programmable for each bit
  • Use of pull-up resistor can be specified for each bit individually
  • Input for HOLD release
  • Input for port 0 interrupt
  • Other pin functions P00: UART1-send P01: UART1-receive P04: System clock output (CKO) P06: Timer6 toggle output P07: Timer7 toggle output AD converter input ports: AN0 (P00) – AN4 (P04) Yes PORT1 P10/S24 to P17/S31 I/O • 8bit input/output port
  • Data direction programmable for each bit
  • Use of pull-up resistor can be specified for each bit individually
  • Other pin functions P10: SIO0 data output P11: SIO0 data input or bus input/output P12: SIO0 clock input/output P13: SIO1 data output P14: SIO1 data input or bus input/output P15: SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output Segment output for LCD: S24 (P10) – S31 (S17) Yes PORT3 P30 I/O • 1bit Input/output port
  • Data direction programmable
  • Use of pull-up resistor can be specified Yes PORT7 P70 to P73 I/O • 4bit Input/output port
  • Data direction can be specified for each bit
  • Use of pull-up resistor can be specified for each bit individually
  • Other functions P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input/NKIN P73: INT3 input (noise rejection filter attached)/timer 0 event input/Timer0H capture input AD converter input ports: AN5 (P70), AN6 (P71)
  • Interrupt detection selection No Rising Falling Rising and falling H level L level INT0 INT1 INT2 INT3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable Continued on next page.

No.A1840-11/29 Continued from preceding page. Pin name I/O Function description Option S00/LPA0 to S07/LPA7 I/O • Segment output for LCD

  • Can be used as general purpose input/output port (LPA) No S08/LPB0 to S15/LPB7 I/O • Segment output for LCD
  • Can be used as general purpose input/output port (LPB) No S16/LPC0 to S23/LPC7 I/O • Segment output for LCD
  • Can be used as general purpose input/output port (LPC) No COM0/LPL0 to COM3/LPL3 I/O • Common output for LCD
  • Can be used as general purpose input/output port (LPL) No V1 to V3 I/O • LCD output bias power supply No RES I • Reset terminal No XT1 I/O • Input for 32.768kHz crystal oscillation
  • When not in use, connect to VDD1 No XT2 I/O • Output for 32.768kHz crystal oscillation
  • When not in use, set to oscillation mode and leave open No CF1 I • Input terminal for ceramic oscillator
  • When not in use, connect to VDD1 No CF2 O • Output terminal for ceramic oscillator
  • When not in use, leave open No Port Configuration Port form and pull-up resistor options are shown in the following table. Port status can be read even when port is set to output mode. Terminal Option applies to: Options Output Form Pull-up resistor P00 to P07 each bit 1 CMOS Programmable

2 Nch-open drain Programmable

P10/S24 to P17/S31 each bit 1 CMOS Programmable P70 - None Nch-open drain Programmable P71 to P73 - None CMOS Programmable S00(LPA0) to S23(LPC7) - None CMOS None P-ch Open Drain N-ch Open Drain COM0(LPL0) to COM3(LPL3) - None CMOS None P-ch Open Drain N-ch Open Drain XT1 - None Input only None XT2 - None 32.768kHz crystal oscillator output None Nch-open drain when selected as normal port

No.A1840-12/29 User Option Table Option Name Option to be Applied on Mask-ROM Version*1 Flash-ROM Version Option Selected in Units of Option Selection Port output type P00 to P07   1 bit CMOS Nch-open drain P10 to P17   1 bit CMOS Nch-open drain P30   1 bit CMOS Nch-open drain Basetimer watchdog timer Watchdog timer period   - Program start address - *2  - 00000h 07E00h *1: Mask option selection-No change possible after mask is completed. *2: Program start address of the mask version is 00000h. *Note 1: Connect as follows to reduce noise on VDD. VSS1 and VSS2 must be connected together and grounded. *Note 2: The power supply for the internal memory is V2. VDD1, VDD2 and V2 are used as the power supply for ports. When VDD1 and VDD2 are not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore, when VDD1 and VDD2 are not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD1 and VDD2 are not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is prevented. VDD1 VDD2 VSS2VSS1 VDC CUP1 CUP2 LSI Power supply Back up capacitors

No.A1840-13/29 Circuit Example (1)1/3bias, 1/4duty X'tal Crystal oscillation CGX Trimmer capacitor CDX Capacitor for X’tal CF Ceramic oscillation CGC Capacitor for CF CDC Capacitor for CF C1 to C5 Capacitor (0.1 μF is recommended) CDEN Electrolytic capacitor RRES Resistor for RES CRES Capacitor for RES LCD panel 24SEG×4COM LC877917A CUP1 CUP2 I/O VDD1 VDD2 VSS1 VSS2 *1: Crystal oscillator *2: Internal RC oscillation *3: Ceramic oscillator 2.4V to 3.6V CDEN CRES *1*2 P00 P01 P02 P03 P04 P05 P06 P07 S00 S23 CF2 CF1 XT2 XT1 X'talCF CGXCDX CGCCDC RES P10 P11 P12 P13 P14 P15 P16 P17 COM0 COM3 P30 P70 P71 P72 P73 I/O I/O I/O RRES VDC

No.A1840-14/29 (2)1/2bias, 1/3duty X'tal Crystal oscillation CGX Trimmer capacitor CDX Capacitor for X’tal CF Ceramic oscillation CGC Capacitor for CF CDC Capacitor for CF C1 to C4 Capacitor (0.1 μF is recommended) CDEN Electrolytic capacitor RRES Resistor for RES CRES Capacitor for RES LCD panel 24SEG×3COM LC877917A CUP1 CUP2 C2I/O VDD1 VDD2 VSS1 VSS2 2.4V to 3.6V CDEN CRES P00 P01 P02 P03 P04 P05 P06 P07 S00 S23 CF2 CF1 XT2 XT1 X'talCF CGXCDX CGCCDC P10 P11 P12 P13 P14 P15 P16 P17 COM0 COM2 P30 P70 P71 P72 P73 I/O I/O I/O RRES *1*2 RES VDC *1: Crystal oscillator *2: Internal RC oscillation *3: Ceramic oscillator

No.A1840-15/29 Parameter Symbol Pins Conditions Specification VDD[V] min typ max unit Supply voltage V DD max V DD1, VDD2, V2 V DD1=VDD2=2V -0.3 +4.3 V Supply voltage For LCD VLCD V1 -0.3 1/2V DD V2 -0.3 V DD V3 -0.3 2/3V DD Input voltage V I XT1, CF1, RES -0.3 V DD+0.3 Input/Output voltage VIO(1) • Port0, 1, 3, 7

  • LPA, LPB, LPC
  • LPL, XT2 -0.3 V DD+0.3 High level output current Peak output current IOPH(1) Port 0, 1 • CMOS output selected
  • Current at each pin -10 mA IOPH(2) Port 3 • CMOS output selected -20 IOPH(3) LPA, LPB, LPC LPL
  • CMOS output selected
  • Current at each pin IOPH(4) Port71 to P73 • Current at each pin -5 Total output current IOAH(1) Port 0 Total of all pins -20 IOAH(2) Port 3, 7 Total of all pins -30 IOAH(3) Port 1 Total of all pins -20 IOAH(4) Port 1, 3, 7 Total of all pins -45 IOAH(5) LPA, LPB, LPC, LPL Total of all pins -30 Low level output current Peak output current IOPL(1) Port 0, 1 Current at each pin 20 IOPL(2) Port 3 Current at each pin 30 IOPL(3) Port 7 Current at each pin 10 IOPL(4) LPA, LPB, LPC, LPL Current at each pin 6 Total output current ΣIOAL(1) Port 0 Total of all pins 40 ΣIOAL(2) Port 3, 7 Total of all pins 50 ΣIOAL(3) Port 1 Total of all pins 40 ΣIOAL(4) Port 1, 3, 7 Total of all pins 65 ΣIOAL(5) LPA, LPB, LPC, LPL Total of all pins 60 Maximum power consumption Pd max QIP64E (14×14) Ta = -40 to +85°C 267 mWTQFP64J (7×7) 124 SQFP64 (10×10) 192 Operating temperature range Topr -40 85 Storage temperature range Tstg -55 125 Note 1-1: The mean output current is a mean value measured over 100ms. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Oper ating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No.A1840-16/29 Allowable Operating Conditions at Ta=-40 to +85°C, VSS1=VSS2=0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Operating supply voltage (Note 2-1) VDD(1) V DD1=VDD2=V2 0.75 μs≤tCYC≤200μs Normal mode 2.4 3.6 V 4.28μs≤tCYC≤200μs Power save mode 2.4 3.6 Memory sustaining supply voltage VHD V DD1=VDD2=V2 RAM and register contents sustained in HOLD mode. 2.2 3.6 High level input voltage VIH(1) Port 0, 3 LPA, LPB, LPC, LPL Output disabled 2.4 to 3.6 0.3VDD +0.7 V DD VIH(2) Port 1 Port 71 to 73 P70 port input / interrupt side

  • Output disabled
  • When INT1VTSL=0 (P71 only) 2.4 to 3.6 0.3VDD +0.7 V DD VIH(3) P71 interrupt side • Output disabled
  • When INT1VTSL=1 2.4 to 3.6 0.85V DD V DD VIH(4) P70 watchdog timer Side Output disabled 2.4 to 3.6 0.9V DD V DD VIH(5) XT1, XT2, CF1, RES 2.4 to 3.6 0.75V DD V DD Low level input voltage VIL(1) Port 0, 3 LPA, LPB, LPC, LPL Output disabled 2.4 to 3.6 V SS 0.2V DD VIL(2) Port 1 Port 71 to 73 P70 port input / interrupt side
  • Output disabled
  • When INT1VTSL=0 (P71 only) 2.4 to 3.6 V SS 0.2V DD VIL(3) P71 interrupt side • Output disabled
  • When INT1VTSL=1 2.4 to 3.6 V SS 0.45V DD VIL(4) P70 watchdog timer side Output disabled 2.4 to 3.6 V SS 0.8VDD -1.0 VIL(5) XT1, XT2, CF1, RES 2.4 to 3.6 V SS 0.25V DD Instruction cycle time (Note 2-2) tCYC 2.4 to 3.6 200 μs External system clock frequency FEXCF(1) CF1 • CF2 pin open
  • System clock frequency division ratio = 1/1
  • External system clock duty = 50±5% 2.4 to 3.6 0.1 4 MHz
  • CF2 pin open
  • System clock frequency division ratio = 1/2 2.4 to 3.6 0.2 8 Oscillation frequency range (Note 2-3) FmCF(1) CF1, CF2 • 4MHz ceramic oscillation
  • See Fig. 1. 2.4 to 3.6 4 MHz FmRC(1) Internal Fast RC oscillation 2.4 to 3.6 350 500 650 kHz FsRC(1) Internal Slow RC oscillation 2.4 to 3.6 25 50 75 FsX’tal XT1, XT2 • 32.768kHz crystal oscillation
  • See Fig. 2. 2.4 to 3.6 32.768 Frequency variable RC oscillation usable range OpVMRC(1) When VMSL4M=0 (Note 2-4) 3.0 to 3.6 8 10 12 MHz OpVMRC(2) When VMSL4M=1 2.4 to 3.6 3.5 4 4.5 Frequency variable RC oscillation adjustment range VmADJ(1) Each step of VMRAJn (Wide range) 2.4 to 3.6 8 24 64 VmADJ(2) Each step of VMFAJn (Small range) 2.4 to 3.6 1 4 8 Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants. Note 2-4: Normal Power mode only.

No.A1840-17/29 Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit High level input current IIH(1) Port 0, 1, 3, 7 LPA, LPB, LPC LPL

  • Output disabled
  • Pull-up resistor off
  • VIN=VDD (Including output Tr's off leakage current) 2.4 to 3.6 1 μA IIH(2) RES V IN=VDD 2.4 to 3.6 1 IIH(3) XT1, XT2 • For input port specification
  • VIN=VDD 2.4 to 3.6 1 IIH(4) CF1 V IN=VDD 2.4 to 3.6 15 Low level input current IIL(1) Port 0, 1, 3, 7 LPA, LPB, LPC LPL
  • Output disabled
  • Pull-up resistor off
  • VIN=VSS (Including output Tr's off leakage current) 2.4 to 3.6 -1 IIL(2) RES V IN=VSS 2.4 to 3.6 -1 IIL(3) XT1, XT2 • For input port specification
  • VIN=VSS 2.4 to 3.6 -1 IIL(4) CF1 V IN=VSS 2.4 to 3.6 -15 High level output voltage VOH(1) Port 0, 1 I OH=-0.4mA 3.0 to 3.6 V DD-0.4 V VOH(2) I OH=-0.2mA 2.4 to 3.6 V DD-0.4 VOH(3) Port 3 I OH=-1.6mA 3.0 to 3.6 V DD-0.4 VOH(4) I OH=-1mA 2.4 to 3.6 V DD-0.4 VOH(5) Port 71 to 73 I OH=-0.4mA 3.0 to 3.6 V DD-0.4 VOH(6) I OH=-0.2mA 2.4 to 3.6 V DD-0.4 VOH(7) LPA, LPB, LPC LPL IOH=-0.1mA 2.4 to 3.6 V DD-0.4 Low level output voltage VOL(1) Port 0, 1 IOL=1.6mA 3.0 to 3.6 0.4 VOL(2) I OL=1mA 2.4 to 3.6 0.4 VOL(3) Port 3 IOL=5mA 3.0 to 3.6 0.4 VOL(4) I OL=2.5mA 2.4 to 3.6 0.4 VOL(5) Port 7 XT2 IOL=1.6mA 3.0 to 3.6 0.4 VOL(6) I OL=1mA 2.4 to 3.6 0.4 VOL(7) LPA, LPB, LPC LPL IOL=0.1mA 2.4 to 3.6 0.4 LCD output voltage regulation VODLS S00 to S31 • I O=0mA
  • V1, V2, V3 LCD level output 2.4 to 3.6 0 ±0.2 VODLC COM0 to COM3 • I O=0mA
  • V1, V2, V3 LCD level output 2.4 to 3.6 0 ±0.2 Resistance of pull- up MOS Tr. Rpu(1) Port 0, 1, 3, 7 VOH=0.9VDD 2.4 to 3.6 18 50 150 k Ω Hysterisis voltage VHYS(1) Port 1, 7 RES 2.4 to 3.6 0.1V DD V Pin capacitance CP All pins • For pins other than that under test: VIN=VSS
  • f=1MHz
  • Ta=25°C 2.4 to 3.6 10 pF

No.A1840-18/29 Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(1) SCK0(P12) See Fig. 6. 2.4 to 3.6 tCYC Low level pulse width tSCKL(1) 1 High level pulse width tSCKH(1) 1 tSCKHA(1) • Continuous data transmission/reception mode

  • See Fig. 6.
  • (Note 4-1-2) Output clock Frequency tSCK(2) SCK0(P12) • CMOS output selected
  • See Fig. 6. 2.4 to 3.6 Low level pulse width tSCKL(2) tSCK High level pulse width tSCKH(2) tSCKHA(2) • Continuous data transmission/reception mode
  • CMOS output selected
  • See Fig. 6. tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tCYC Serial input Data setup time tsDI(1) SB0(P11), SI0(P11)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 6. 2.4 to 3.6 0.03 μs Data hold time thDI(1) 2.4 to 3.6 0.03 Serial output Input clock Output delay time tdD0(1) SO0(P10), SB0(P11)
  • Continuous data transmission/reception mode
  • (Note 4-1-3) 2.4 to 3.6 (1/3)tCYC +0.05 tdD0(2) • Synchronous 8-bit mode
  • (Note 4-1-3) 2.4 to 3.6 1tCYC +0.05 Output clock tdD0(3) (Note 4-1-3) 2.4 to 3.6 (1/3)tCYC +0.15 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.

No.A1840-19/29 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Serial clock Input clock Frequency tSCK(3) SCK1(P15) See Fig. 6. 2.4 to 3.6 tCYC Low level pulse width tSCKL(3) 1 High level pulse width tSCKH(3) 1 Output clock Frequency tSCK(4) SCK1(P15) • CMOS output selected

  • See Fig. 6. 2.4 to 3.6 Low level pulse width tSCKL(4) 1/2 tSCK High level pulse width tSCKH(4) 1/2 Serial input Data setup time tsDI(2) SB1(P14), SI1(P14)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig. 6. 2.4 to 3.6 0.03 μs Data hold time thDI(2) 2.4 to 3.6 0.03 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
  • Must be specified with respect to falling edge of SIOCLK.
  • Must be specified as the time to the beginning of output state change in open drain output mode.
  • See Fig. 6. 2.4 to 3.6 (1/3)tCYC +0.05 Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit High/low level pulse width tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72)
  • Interrupt source flag can be set.
  • Event inputs for timer 0 or 1 are enabled. 2.4 to 3.6 1 tCYC tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is 1/1
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.4 to 3.6 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is 1/32
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.4 to 3.6 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is 1/128
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.4 to 3.6 256 tPIL(5) RES Resetting is enabled. 2.4 to 3.6 200 μs Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter Symbol Pin/Remarks Conditions Specification Option selected voltage min typ max unit POR release voltage PORR - 1.79 V Detection voltage unknown state POUKS • See Fig. 8. Note 6-1: POR is in an unknown state before transistors start operation.

No.A1840-20/29 AD Converter Characteristics at VSS1 = VSS2 = 0V <12bits AD Converter Mode at Ta=-40 to +85°C> <Normal power mode only> Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Resolution N AN0(P00) to AN4(P04), AN5(P70) to AN6(P71) 3.0 to 3.6 12 bit Absolute accuracy ET (Note 7-1) 3.0 to 3.6 ±16 LSB Conversion time TCAD • See Conversion time calculation formulas. (Note 7-2) 3.0 to 3.6 64 115 μs Analog input voltage range VAIN 3.0 to 3.6 V SS V DD V Analog port input current IAINH VAIN=V DD 3.0 to 3.6 1 μA IAINL VAIN=V SS 3.0 to 3.6 -1 <8bits AD Converter Mode at Ta=-40 to +85°C> <Normal power mode only> Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max Unit Resolution N AN0(P00) to AN4(P04), AN5(P70) to AN6(P71) 3.0 to 3.6 8 bit Absolute accuracy ET (Note 7-1) 3.0 to 3.6 ±1.5 LSB Conversion time TCAD • See Conversion time calculation formulas. (Note 7-2) 3.0 to 3.6 40 90 μs Analog input voltage range VAIN 3.0 to 3.6 V SS V DD V Analog port input current IAINH VAIN=V DD 3.0 to 3.6 1 μA IAINL VAIN=V SS 3.0 to 3.6 -1 Conversion Time Calculation Formulas: 12bits AD Converter Mode : TCAD(Conversion time) = ((52/(division ratio))+2)×(1/3)×tCYC 8bits AD Converter Mode : TCAD(Conversion time) = ((32/(division ratio))+2)×(1/3)×tCYC External oscillation (FmCF) Operating supply voltage range (VDD) System division ratio (SYSDIV) Cycle time (tCYC) AD division ratio (ADDIV) AD conversion time (TCAD) 12bit AD 8bit AD CF-4MHz 3.0V to 3.6V 1/1 750ns 1/8 104.5 μs 64.5 μs Note 7-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 7-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when:

  • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
  • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.

No.A1840-21/29 Current Consumption Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter Symbol Pin Conditions Specification VDD[V] min typ max unit Current consumption during normal operation (Note 8-1) IDDOP(1) V DD1= VDD2=V2

  • FmCF=4MHz Ceramic resonator oscillation
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: CF 4MHz oscillation
  • Internal RC oscillation stopped.
  • Divider: 1/1
  • Normal power mode 2.4 to 3.6 1.2 2.8 mA IDDOP(2) • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: Fast RC oscillation
  • Divider: 1/1
  • Normal power mode 2.4 to 3.6 135 400 μA IDDOP(3) • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: Fast RC oscillation
  • Divider: 1/1
  • Power save mode 2.4 to 3.6 43 150 IDDOP(4) • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: Slow RC oscillation
  • Divider :1/1
  • Normal power mode 2.4 to 3.6 23 105 IDDOP(5) • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: Slow RC oscillation
  • Divider: 1/1
  • Power save mode 2.4 to 3.6 14 80 IDDOP(6) • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal Oscillation (Normal operation)
  • Internal RC oscillation stopped.
  • System clock: VMRC oscillation (4MHz)
  • Divider: 1/1
  • Normal power mode 2.4 to 3.6 1.2 2.8 mA IDDOP(7) • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: 32.768kHz
  • Internal RC oscillation stopped.
  • Divider: 1/1
  • Normal XT Amp mode
  • Normal power mode 2.4 to 3.6 14 73 μA Note 8-1: The currents through the output transistors and the pull-up MOS transistors are ignored. Continued on next page.

No.A1840-22/29 Continued from preceding page. Parameter Symbol Pin Conditions Specification VDD[V] min typ max unit Current consumption during normal operation (Note 8-1) IDDOP(8) V DD1= VDD2=V2

  • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: 32.768kHz
  • Internal RC oscillation stopped.
  • Divider: 1/1
  • Normal XT amp mode
  • Power save mode 2.4 to 3.6 8 55 μA IDDOP(9) • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Low amp operation)
  • System clock: 32.768kHz
  • Internal RC oscillation stopped.
  • Divider: 1/1
  • Low XT amp mode
  • Normal power mode 2.4 to 3.6 8.5 43 IDDOP(10) • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Low amp operation)
  • System clock: 32.768kHz
  • Internal RC oscillation stopped.
  • Divider: 1/1
  • Low XT Amp mode
  • Power save mode 2.4 to 3.6 2.3 12 Note 8-1: The currents through the output transistors and the pull-up MOS transistors are ignored. Continued on next page.

No.A1840-23/29 Continued from preceding page. Parameter Symbol Pin Conditions Specification VDD[V] min typ max unit Current consumption during HALT mode (Note 8-1) IDDHALT(1) V DD1= VDD2=V2 HALT mode

  • FmCF=4MHz Ceramic resonator oscillation
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: CF 4MHz oscillation
  • Internal RC oscillation stopped
  • Divider: 1/1
  • Normal power mode 2.4 to 3.6 510 1370 μA IDDHALT(2) HALT mode
  • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: Fast RC oscillation
  • Divider: 1/1
  • Normal power mode 2.4 to 3.6 52 185 IDDHALT(3) HALT mode
  • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: Fast RC oscillation
  • Divider: 1/1
  • Power save mode 2.4 to 3.6 24 110 IDDHALT(4) HALT mode
  • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: Slow RC oscillation
  • Divider: 1/1
  • Normal power mode 2.4 to 3.6 15 85 IDDHALT(5) HALT mode
  • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: Slow RC oscillation
  • Divider: 1/1
  • Power save mode 2.4 to 3.6 12 76 IDDHALT(6) HALT mode
  • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • Internal RC oscillation stopped.
  • System clock: VMRC oscillation (4MHz)
  • Divider: 1/1
  • Normal power mode 2.4 to 3.6 350 995 IDDHALT(7) HALT mode
  • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: 32.768kHz
  • Internal RC oscillation stopped.
  • Divider: 1/1
  • Normall XT Amp mode
  • Normal power mode 2.4 to 3.6 8.1 61 Note 8-1: The currents through the output transistors and the pull-up MOS transistors are ignored. Continued on next page.

No.A1840-24/29 Continued from preceding page. Parameter Symbol Pin Conditions Specification VDD[V] min typ max unit Current consumption during HALT mode (Note 8-1) IDDHALT(8) V DD1= VDD2=V2 HALT mode

  • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Normal operation)
  • System clock: 32.768kHz
  • Internal RC oscillation stopped.
  • Divider: 1/1
  • Normal XT Amp mode
  • Power save mode 2.4 to 3.6 6.2 53 μA IDDHALT(9) HALT mode
  • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Low amp operation)
  • System clock: 32.768kHz
  • Internal RC oscillation stopped.
  • Divider: 1/1
  • Low XT Amp mode
  • Normal power mode 2.4 to 3.6 3.0 30 IDDHALT(10) HALT mode
  • FmCF=0Hz (No oscillation)
  • FsX’tal=32.768kHz crystal oscillation (Low amp operation)
  • System clock: 32.768kHz
  • Internal RC oscillation stopped.
  • Divider: 1/1
  • Low XT Amp mode
  • Power save mode 2.4 to 3.6 1.0 9.2 Current consumption during HOLD mode IDDHOLD(1) HOLD mode
  • CF1=VDD or open (when using external clock) 2.4 to 3.6 0.05 26 Current consumption during Date/time clock HOLD mode IDDHOLD(2) Date/time clock HOLD mode
  • CF1=VDD or open (when using external clock)
  • FmX’tal=32.768kHz crystal oscillation
  • Divider: 1/1
  • LCD display off
  • Normal XT Amp mode 2.4 to 3.6 5.7 56 IDDHOLD(3) Date/time clock HOLD mode
  • CF1=VDD or open (when using external clock)
  • FmX’tal=32.768kHz crystal oscillation
  • Divider: 1/1
  • LCD display off
  • Low XT Amp mode 2.4 to 3.6 0.47 25 IDDHOLD(4) Date/time clock HOLD mode
  • CF1=VDD or open (when using external clock)
  • FmX’tal=Slow RC oscillation
  • Divider: 1/1
  • LCD display off 2.4 to 3.6 11 75 Note 8-1: The currents through the output transistors and the pull-up MOS transistors are ignored.

No.A1840-25/29 UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V Parameter Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit Transfer rate UBR UTX(P00), URX(P01) 2.4 to 3.6 16/3 8192/3 tCYC Data length: 7/8/9 bits (LSB first) Stop bits : 1 bit (2-bit in continuous data transmission) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Example of 8-bit Data Reception Mode Processing (Receive Data=55H) Transmit data (LSB first) Start of transmission End of transmission UBR Start bit Stop bit Receive data (LSB first) UBR Start of reception End of reception Stop bit Start bit

No.A1840-27/29 Reset Time and Oscillation Stabilizing Time HOLD Release Signal and Oscillation Stable Time Note: External oscillation circuit is selected. Figure 4 Oscillation Stabilization Times Without HOLD Release Internal RC Resonator oscillation CF1, CF2 XT1, XT2 Operation mode HOLD reset signal VALID tmsCF tmsX’tal HOLD HALT HOLD reset signal VDD limit Power supply RES Internal RC Resonator oscillation CF1, CF2 XT1, XT2 Operating mode Reset time tmsCF tmsX’tal Unfixed Reset Instruction execution mode VDD Execute oscillation enable command

No.A1840-29/29 Figure 8 Waveform observed when POR is used (RESET pin: Pull-up resistor RRES only)

  • The POR function generates a reset only when power is turned on starting at the VSS level.
  • No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a).
  • A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 1000μs or longer. PS POR release voltage (PORRL) VDD RES Unknown-state (POUKS) (a) (b) Reset period Reset period 1000μs or longer ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s techn ical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC productsfor any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, anddistributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture oft h e part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.