LC823455 ONSEMI | Alldatasheet
Document overview
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- PDF pages: 109
Technical content
Features
- Ultra Low Power Consumption
- Arm® Cortex®−M3 Dual Core
- Proprietary 32−bit DSP Core (LPDSP32)
- Internal Large−Scale Size SRAM : 4316 KB (4MB + 220 KB)
- High−Resolution 32−bit & 192 kHz Audio Processing Capability
- Several DSP Codes Available for Audio Functions
- Hard−Wired Audio Functions Built−In: MP3 decoder, MP3 encoder, 6 band Equalizer Synchronous SRC, Asynchronous SRC, etc.
- Analog Blocks Built−in: System PLL, Audio PLL, 16−bit DAC, Class−D amp, etc.
- USB On−The−Go(OTG) that supports USB2.0 Device and Host Functions with an Integrated PHY , eMMC and SD Card I/F, Serial Flash I/F(Quad) with Cache Memory, SPI, UART, I2C, etc. Typical Applications
- Wearable Earbuds
- Wearable Headphone
- Wireless Speaker
- IC Recorder www.onsemi.com See detailed ordering and shipping information on page 107 of this data sheet.
ORDERING INFORMATION
WLCSP120, 4.086x4.086x0.62 CASE 567WG LFBGA240, 11.0x11.0 CASE 566EY LFBGA136, 11.0x11.0 CASE 566GB NOTE: LC823455RAH−2H and LC823455RB−2H are under planning. LC823455RAH−2H : Package Code = RA LC823455RB−2H : Package Code = RB
www.onsemi.com Table of Contents
www.onsemi.com ABSTRACT
- Cortex−M3 Dual Core, AMBA® (AHB/APB) system ♦ Internal SRAM (4 M-byte) ♦ Internal ROM (256 k-byte). Boot code, Standard Functions ♦ SDRAM Controller (1 * CS) 64M to 256Mbit SDRAM / Mobile SDRAM ♦ External Memory Controller (2 * CS) NOR FLASH, SRAM, ROM supported, 8/16 bit I/F LCD controller supported Internal ROM boot and External memory device boot available ♦ DMA Controller (8 ch) ♦ Interrupt Controller (External 90 ch, Internal 83 ch) ♦ SPI (2 ch) ♦ Pseudo SRAM I/F (1 ch) ♦ Serial Flash I/F (1 ch) ♦ Quad SPI, cache memory (16 k-byte, 4way set associative, 128 line) function available ♦ UART (3ch) UART1, UART2: w/flow control (CTS, RTS) UART0: w/o flow control ♦ I2C (2ch) Single Master, Full/Standard ♦ GPIO (90 ch) ♦ Pin multiplex function (I2C:2 ch, SPI:2 ch, UART:3 ch, MTM:2 ch, DMIC:2 ch x 2) ♦ Plain Timer w/ Watch Dog Timer (1 ch×3) ♦ Multiple Timer (2 ch×4) ♦ 12 bit ADC (8 ch) ♦ SD Card I/F (3 ch) eSD/eMMC, UHS−I, w/o CPRM −S D 0: eSD/eMMC boot supported (Internal ROM Boot function) − SD1: 1.8 V/3.3 V dedicated power supply − SD2 : ♦ USB2.0 Device (HS/FS) Controller, Host (HS/FS/LS) Controller with OTG Controller, Integrated PHY . Xtal (XT1) is required for USB function, 12, 19.2, 24 MHz for device and host with OTG function. Host and Device share an integrated PHY . ♦ Real Time Clock 2 modes below are available − General RTC mode : RTC w/o key input − KeyInt RTC mode : RTC w/ key input which enables power on function ♦ SWD (Serial Wire Debug) is supported as the debug interface SWV (Serial Wire Viewer) is supported as the trace interfaceOnly one of Cortex−M3 Dual Core can be traced Availability of features explained here depends on products.
- MP3 hard wired encoder/decoder ♦ MP3 MPEG1, MPEG2, MPEG2.5 − Sampling rate: 8 kHz,11.025 kHz,12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz − Bit rate: 8 Kbps to 320 Kbps (Decoder−VBR supported)
- LPDSP32 system ♦ Internal SRAM (220 kbyte) ♦ Audio codec − MP3 − WMA − AAC − SBC − FLAC, etc. ♦ Audio function − Active Noise Canceller − 1−mic/2−mic Noise Canceller for Recorder − 2−mic Noise Canceller for Hands Free − Echo Canceller − Variable Speed Control playback etc. ♦ JTAG ICE 1 MPEG Layer− 3 audio coding technology licensed from Fraunhofer IIS and Thomson. Supply of this product does not convey license nor imply any right to distribute content created with this product in revenue− generating broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming applications (via Internet, intranets and/or networks), other content distribution systems (pay− au- dio or audio− on− demand applications and the like) or on physical media (compact discs, digital versatile discs, semiconductor chips, hard drives, memory cards and the like). For details, please visit http://mp3licensing.com/ Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer Gesellschaft nor imply any right to use this product in any finished end user or ready− to− use final product. An independent license for such use is required. For details, please visit http://mp3licensing.com/ 2 This product contain technology of Microsoft company ownership, and you cannot distribute or use without getting license from Microsoft Licensing Company.
www.onsemi.com
- Bluetooth Protocol Stack available
- Audio ♦ MP3 hard wired encoder/decoder, MP3 MPEG1, MPEG2, MPEG2.5 − Sampling rate: 8 kHz,11.025 kHz,12 kHz,16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48kHz − Bit rate :8 Kbps to 320 Kbps (Decoder−VBR supported) ♦ Other audio functions available − 6 band Equalizer (EQ3) − Hardware Mixer − V olume, Mute − Level Meter − Audio Timer w/ interrupt generation − 16/24/32 bit 192 kHz PCM I/F (2ch ×2). Master/slave, I2S − SSRC (Synchronous Sampling Rate Converter) 0.25 to 64 conversion capable − ASRC (Asynchronous Sampling Rate Converter) Jitter reducing function supporting USB audio class and Bluetooth streaming − Beep generator − Digital Microphone I/F (2ch x2), Sampling rate : up to 48 kHz, Support up to 4 PDM Digital Microphones − 16 bit Audio DAC (2 ch) w/ Class−D Amplifier for Head Phone (2 ch). Requires external LC LPF
- Audio clock generation ♦ Dedicated PLL for audio ♦ Selectable PLL reference clock XT1 (12, 19.2, 24 MHz Main xtal) XTRTC (32.768 kHz RTC xtal) PCM I/F MCLK0 (/MCLK1), BCK0, BCK1
- Power supply ♦ Typical voltage − LOGIC(Vdd1),XT1(VddXT1), PLL1(A VddPLL1), PLL2(A VddPLL2) = 1.0 V − RTC(VddRTC) = 1.0 V − I/O(Vdd2) = 1.8 V or 3.3 V − SD1(VddSD1) = 1.8 V or 3.3 V − ADC(A VddADC) = 1.8V − USB PHY(DVddUSBPHY1) = 1.0 V , (A VddUSBPHY2) = 3.3 V, (A VddUSBPHY18) = 1.8 V − Class−D Amplifier (A VddDAMPL,A VddDAMPR) = 1.5 V 3 The product name for which Bluetooth Protocol Stack is available is determined. Please contact our representative for license fee for the Stack. Copyright 1999− 2014 OpenSynergy GmbH All rights reserved. All unpublished rights reserved.
The products with Package Code = “RA” and “RB” are under planning. Table 1. FUNCTIONAL DIFFERENCES
Figure 1. Top−Level Block Diagram
Figure 2. Bus Matrix
Figure 3. Audio
1 Digtal
32 Bit conv
256 KB SRAM divided into
Figure 4. Clock Hierarchy refer to the appropriate documents. refer to the SSRC and ASRC Programmer’s Model documents. while FS is Sampling Frequency of MPEG1 mode of MP3. while FS is Sampling Frequency of MPEG1 mode of MP3. switch enabled by the execution of a dedicated operation.
Figure 5. All Areas (Cortex−M3)
Table 2. CODE AREA (CORTEX−M3) − UNREMAPPED (AFTER RESET)
256 KB Internal ROM /C0100 /C0100
220 KB Internal SRAM
32 KB Internal SRAM
1536 KB Internal SRAM
256 KB Internal SRAM
256 KB Internal ROM
Table 3. CODE AREA (CORTEX−M3) − REMAPPED (REMAP[1:0]=2’B01)
0000 Reserved
0000 External memory 1 /C0100 /C0100
0000 External memory 0 /C0100 /C0100
7000 Reserved
Table 4. CODE AREA (CORTEX−M3) − REMAPPED (REMAP[1:0]=2’B11)
Table 5. SRAM AREA (CORTEX−M3)
Table 6. OTHER AREAs (CORTEX−M3)
Table 6. OTHER AREAs (CORTEX−M3) (continued)
- Access from internal peripheral bus(AHB/APB)
Table 7. LPDSP32 − DMA Table 8. LPDSP32 – DMB
Table 9. LPDSP32 − DMIO
Table 10. LPDSP32 − PM
256 KB (seg 7−A)
384 KB (seg 5−A)
128 KB (seg 0−A) /C0100
- PM of LPDSP32 cannot access internal SRAM seg5, 6, and 7 .
XA: Package Code = “XA”, RA: Package Code = “RA”, RB: Package Code = “RB”, (RA and RB are under planning). Table 11. TERMINAL FUNCTIONS
Table 11. TERMINAL FUNCTIONS (continued)
Bonding “00” internally for XA.
12 BIT ADC
- Set according to the General RTC mode or KeyInt RTC mode.
- S−Flash I/F / SD I/F Ch0 includes SFQSCS / SDCMD0 in Timer.
- SDRAM address bit is 13 bit including SDRADDR [12:11].
- This function is not available.
Table 12. PIN MULTIPLEX FUNCTIONS
0 I2C0 SCL0 I2C ch0 Clock GPIO00 to 0F
1 SDA0 I2C ch0 Data
2 I2C1 SCL1 I2C ch1 Clock
3 SDA1 I2C ch1 Data
4 SPI0 SCK0 Serial I/F Ch0 Clock
5 SDI0 Serial I/F Ch0 Data Input
6 SDO0 Serial I/F Ch0 Data Output
7 SPI1 SCK1 Serial I/F Ch1 Clock
8 SDI1 Serial I/F Ch1 Data Input
9 SDO1 Serial I/F Ch1 Data Output
10 MTM0 TCLKA0 MTM0 external Clock A
11 TCLKB0 MTM0 external Clock B
12 TIOCA00 MTM0 Ch0A
13 TIOCA01 MTM0 Ch1A
14 TIOCB00 MTM0 Ch0B
15 TIOCB01 MTM0 Ch1B
16 MTM1 TCLKA1 MTM1 external Clock A
17 TCLKB1 MTM1 external Clock B
18 TIOCA10 MTM1 Ch0A
19 TIOCA11 MTM1 Ch1A
20 TIOCB10 MTM1 Ch0B
21 TIOCB11 MTM1 Ch1B
22 UART0 RXD0 UART Ch0 receive Data
23 TXD0 UART Ch0 transmit Data
24 UART1 RXD1 UART Ch1 receive Data
25 TXD1 UART Ch1 transmit Data
26 CTS1 UART Ch1 clear to send
27 RTS1 UART Ch1 request to send
28 UART2 RXD2 UART Ch2 receive Data
29 TXD2 UART Ch2 transmit Data
30 CTS2 UART Ch2 clear to send
31 RTS2 UART Ch2 request to send
32 DMIC0 DMCKO0 Digital Mic Ch0 Clock Output
33 DMDIN0 Digital Mic Ch0 Data Input
34 DMIC1 DMCKO1 Digital Mic Ch1 Clock Output
35 DMDIN1 Digital Mic Ch1 Data Input
36 OSC WICPOWERDOWN Power control for WIC Sleep
37 Reserved Reserved Reserved
Table 13. BOOT MODE IPL2 is transferred to boot partition1 area of eMMC via USB from PC. from boot partition1 area of eMMC connected to SDCH0 and is executed. XT1 must be connected in this mode to boot the ROM. The connection of XTRTC is arbitrary. IPL2 is transferred to boot partition1 area of eMMC from SDCH1. from boot partition1 area of eMMC connected to SDCH0 and is executed. Either XT1 or XTRTC is required to boot the ROM. IPL2 is transferred to user area of eMMC via USB from PC. XT1 must be connected in this mode to boot the ROM. The connection of XTRTC is arbitrary. IPL2 is transferred to user area of eMMC from SDCH1. Either XT1 or XTRTC is required to boot the ROM. IPL2 is transferred to user area of S−FLASH via USB from PC. XT1 must be connected in this mode to boot the ROM. The connection of XTRTC is arbitrary. IPL2 is transferred to user area of S−FLASH from SDCH1. Either XT1 or XTRTC is required to boot the ROM. The IPL supports the direct write of the program using the DD command from USB. In this mode, the CPU fetches Serial Flash connected to S/Flash IF directly. XT1 must be connected in this mode to boot the ROM. The connection of XTRTC is arbitrary.
Table 13. BOOT MODE (continued) IPL2 is transferred to S−FLASH from SDCH1. In this mode, the CPU fetches from Serial Flash connected to S/Flash IF directly. Either XT1 or XTRTC is required to boot the ROM. It comes to be able to write IPL2 again at User Area Boot. Either XT1 or XTRTC is necessary to boot the ROM. It comes to be able to write IPL2 again at eMMC Physical Boot. Either XT1 or XTRTC is necessary to boot the ROM. All of Serial Flash is deleted. Please select it when you use Serial Flash with SPI. Either XT1 or XTRTC is required to boot the ROM. eMMC corresponds to Trim, Trim is done. Either XT1 or XTRTC is required to boot the ROM. All of Serial Flash is deleted. Please use it when you use Serial Flash in the fetch mode of QSPI. Either XT1 or XTRTC is required to boot the ROM. controller of External0 directly. Either XT1 or XTRTC is required to boot the ROM. Either XT1 or XTRTC is required to boot the ROM.
The ports used while booting are described below.
- There is no dedicated SDCH0 pin in the WLP package. Therefore, when booting from eMMC, the terminals SFCK, SFQSCS, SFDO, SFDI, SFWP, and SFHOLD must be switched to SDCLK0, SDCMD0, SDAT00, SDAT01, SDAT02, and SDAT03. The target is Physical Boot USB · Physical Boot SD · User Area Boot USB · User Area Boot SD · User Area Delete, Partition Delete, SDCH 0 All Erase
- SD Card SDCH1 uses only CMD, DATA, and CLK. The terminals CD and WP are not used. These three terminals are controlled only when writing IPL2 from SDCH1
- SPI Boot / SPI All Erase uses only SFCK, SFDO, SFDI and SFQSCS switched from TIOCB01. SFHOLD and SFWP (The function is different according to the device) are not used
- QSPI Boot / QSPI All Erase uses SFCK, SFDO, SFDI, SFHOLD, SFWP and SFQSCS switched from TIOCB01
- External ROM boot uses NCS0 and other terminals required by the external memory controller. It is available to packages in which the terminals of external memory controller are assigned.
Table 14. GPIOs USED DURING IPL
Table 14. GPIOs USED DURING IPL (continued) HI−z SDCLK0 is set to the Hi−z input.
- In this table, “Pxx” means “GPIOxx”. For example “P2F” means “GPIO2F”.
with High/Low of the terminal. through a sequence of Low/High.
Table 15. PIN ASSIGNMENT XA: Package Code = “XA”, RA: Package Code = “RA”, RB: Package Code = “RB”, (RA and RB are under planning).
1 M13 − − − − Vdd2 P
2 N14 − − − − Vss2 G
5 L13 − − − − EXA11/
6 L14 − − − − EXA12/
7 K11 − − − − EXA13/
8 K13 − − − − EXA14/
9 R15 1 R15 1 L10 Vdd1 P
10 R16 2 R16 2 H8 NRD/
11 P15 3 P15 3 K9 SWDIO/
12 P16 4 P16 4 G7 NLBEXA0/
13 K14 − − − − EXD2/
14 J10 − − − − EXA2/
15 N15 5 N15 5 L9 Vss2 G
16 J11 − − − − EXA6/
17 J13 − − − − EXA7/
18 J14 − − − − SDRADDR12/
Table 16. (continued)
19 N16 6 N16 6 J8 TDI/
20 M15 7 M15 7 K8 TDO/
21 M16 8 M16 8 L8 VddSD1 P
22 L15 9 L15 9 H7 SDCMD1/
23 L16 10 L16 10 J7 SDAT10/
24 K12 11 K12 11 K7 SDAT11/
25 J15 12 J15 12 L7 Vss2 G
26 K16 13 K16 13 F5 SDAT12/
27 J12 14 J12 14 G6 SDAT13/
28 K15 15 K15 15 H6 SDCLK1/
29 J16 16 J16 16 L6 Vss1 G
30 H12 17 H12 − − RTCMODE I CMOS − − − VddRTC 1IC
31 H15 18 H15 17 K6 VddRTC P
32 H16 19 H16 18 J5 XIN32K I X − − − VddRTC X
33 G15 20 G15 19 K5 VssRTC G
34 G16 21 G16 20 L5 XOUT32K O − X − − VddRTC X
35 H13 − − − − Keyint2 I CMOS − − PD VddRTC 1ICD
36 F15 22 F15 − − BACKUPB I CMOS − − − VddRTC 1IC
37 F16 23 F16 21 J6 VDET I CMOS − − − VddRTC 1IC
38 E16 24 E16 22 H5 RTCINT (Note
39 G12 25 G12 23 G5 Keyint0 I CMOS − − PD VddRTC 1ICD
40 E15 26 E15 24 H4 TEST I CMOS − − − VddRTC 1IC
41 F12 27 F12 25 L4 Keyint1 I CMOS − − PD VddRTC 1ICD
42 D15 28 D15 26 K4 AVddPLL1 P
43 D14 − − − − VCNT1 O − 1A − − AVddPLL1 1A
44 D16 29 D16 27 J4 AVssPLL1 G
45 C15 30 C15 28 K3 AVddPLL2 P
46 C14 − − − − VCNT2 O − 1A − − AVddPLL2 1A
47 C16 31 C16 29 L3 AVssPLL2 G
48 E13 − − − − Vss1 G
49 E14 − − − − Vdd2 P
50 D13 − − − − Vss2 G
51 H10 − − − − EXD4/
52 H11 − − − − EXD5/
53 B15 32 B15 30 L2 Vdd1 P
54 H14 − − − − EXD6/
55 G10 − − − − EXA19/
56 G11 − − − − EXA20/
57 G13 − − − − EXD7/
58 G14 − − − − EXD8/
59 B14 33 B14 31 L1 Vss1 G
60 F14 − − − − EXD11/
61 F13 − − − − EXD12/
62 D12 − − − − EXD13/
63 F11 − − − − EXD14/
64 C13 − − − − Vss2 G
65 A16 34 A16 32 K2 DOUT1/
66 D11 − − − − EXD9/
67 F10 − − − − EXD10/
68 B16 35 B16 33 K1 Vdd2 P
69 D10 − − − − EXD15/
70 A15 36 A15 34 J3 BCK1/
71 A14 37 A14 35 G4 MCLK0/
72 A13 38 A13 36 J2 LRCK1/
73 B13 39 B13 37 J1 Vss2 G
74 C11 − − − − Vdd2 P
75 B12 40 B12 38 H3 BCK0/
76 A12 41 A12 39 G3 LRCK0/
77 B11 42 B11 40 H2 DIN0/
78 C12 − − − − Vss2 G
79 G9 − − − − XTALINFO1 B Schmitt 3−State 2/4/8 mA PU Vdd2 3ISU/3T2
80 C10 − − − − Vdd2 P
81 A11 43 A11 41 H1 DOUT0/
82 A10 44 A10 42 F4 BMODE0 B Schmitt 3−State 2 mA PU/PD Vdd2 3ISUD/3T2
83 B10 45 B10 43 F3 BMODE1 B Schmitt 3−State 2 mA PU/PD Vdd2 3ISUD/3T2
84 F9 − − − − SDRADDR1 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
86 C9 − − − − SDRADDR0 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
87 B9 46 B9 44 G1 NRES I Schmitt − − − Vdd2 3IS
88 A9 47 A9 45 G2 AVssDAMPR G
89 A8 48 A8 46 F1 ROUT/
90 A7 49 A7 47 F2 AVddDAMPR P
91 A6 50 A6 48 E2 AVddDAMPL P
92 A5 51 A5 49 E1 LOUT/
93 A4 52 A4 50 D2 AVssDAMPL G
94 B8 53 B8 51 D1 Vss1 G
95 G8 − − − − SDRADDR2 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
96 D8 − − − − SDRADDR3 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
97 E12 54 E12 52 E3 SCL1/
98 E11 55 E11 53 E4 SDA1/
99 E10 56 E10 54 D3 SDRADDR11/
100 C8 − − − − SDRDATA0 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
101 B7 57 B7 55 C1 Vdd1 P
102 C7 − − − − SDRDATA1 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
103 E9 58 E9 56 C2 TCLKA0/
104 E8 59 E8 57 D4 TCLKB0/
105 E7 60 E7 58 C3 NHBNWRH/
106 C6 − − − − Vdd2 P
107 B5 61 B5 59 B1 Vss2 G
108 D7 − − − − PSM_DAT2 B CMOS 3−State 2/4/8/10 mA PU/PD Vdd2 3ICUD/3T2
110 D5 − − − − PSM_DAT3 B CMOS 3−State 2/4/8/10 mA PU/PD Vdd2 3ICUD/3T2
111 C5 − − − − SDRADDR4 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
112 C4 − − − − SDRDATA4 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
113 C3 − − − − SDRDATA14 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
114 B6 62 B6 60 A1 Vdd2 P
115 D4 − − − − Vdd2 P
116 D3 − − − − SDRDATA2 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
117 E4 − − − − SDRDATA3 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
118 E3 − − − − SDRDATA15 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
120 F6 − − − − PSM_CS O CMOS 3−State 2/4/8/10mA PU/PD Vdd2 3ICUD/3T2
121 F8 − − − − PSM_SCK O CMOS 3−State 2/4/8/10 mA PU/PD Vdd2 3ICUD/3T2
122 F4 − − − − SDRADDR7 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
123 F3 − − − − SDRDATA5 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
124 G7 − − − − SDRDATA13 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
125 B4 63 B4 61 A2 Vss2 G
126 A2 64 A2 62 B2 EXTINT2E/GP
127 A1 65 A1 63 B3 NCS1/
128 G6 − − − − SDRDATA12 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
129 G4 − − − − SDRDATA6 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
130 G3 − − − − SDRDATA7 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
131 B3 66 B3 64 A3 Vss1 G
132 H7 − − − − SDRDATA8 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
133 B2 67 B2 65 C4 EXTINT2F/
134 B1 68 B1 66 B4 TCK/
135 H6 − − − − SDRDATA9 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
136 A3 69 A3 67 A4 Vdd2 P
137 H4 − − − − SDRDATA11 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
138 H3 − − − − SDRDATA10 B CMOS 3−State 2/4/8 mA PD Vdd2 3ICD/3T2
139 C2 70 C2 68 D5 TIOCA01/
140 C1 71 C1 69 C5 TXD1/
141 D2 72 D2 70 B5 RXD1/
142 J7 − − − − Vss2 G
143 D1 73 D1 71 A5 Vdd1 P
144 E6 74 E6 72 E5 CTS1/
145 E5 75 E5 73 C6 RTS1/
146 E2 76 E2 74 B6 TIOCA00/
147 J6 − − − − SDRADDR5 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
148 J4 − − − − SDRADDR6 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
149 J3 − − − − SDRADDR9 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
150 H9 77 H9 75 A6 Vdd2 P
151 E1 78 E1 76 D6 TMS/
152 F5 79 F5 77 E6 TXD2/
153 F2 80 F2 78 D7 RXD2/
154 K6 − − − − SDRBA1 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
155 K4 − − − − SDRBA0 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
156 F1 81 F1 79 A7 Vss2 G
157 K3 − − − − SDRADDR10 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
158 G5 82 G5 80 B7 SFCK/
159 G2 83 G2 81 C7 TIOCB01/
160 G1 84 G1 82 E7 SFDO(QIO1)/
161 L4 − − − − SDRRAS O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
162 H8 85 H8 83 A8 Vdd2 P
163 H5 86 H5 84 B8 SFDI(QIO0)/
164 H2 87 H2 85 C8 SFWP(QIO2)/
165 H1 88 H1 86 D8 SFHOLD(QIO
166 L2 89 L2 87 A9 Vss1 G
167 L3 − − − − SDRWE O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
168 M5 − − − − SDRCKE O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
169 J5 90 J5 88 B9 TIOCB00/
170 M4 − − − − SDRCLK O − 3−State 2/4/8/10 mA − Vdd2 3T2(4)(8)(10)
171 M3 − − − − SDRCS O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
172 M2 91 M2 89 A10 IO18V I 1A − − − Vdd1 1A
173 N3 − − − − Vss1 G
174 J2 92 J2 − − SDAT02 B CMOS 3−State 2/4/8/10 mA PU/PD Vdd2 3ICUD/3T2
175 J1 93 J1 − − SDAT03 B CMOS 3−State 2/4/8/10 mA PU/PD Vdd2 3ICUD/3T2
176 K5 94 K5 − − SDAT01 B CMOS 3−State 2/4/8/10 mA PU/PD Vdd2 3ICUD/3T2
177 K2 95 K2 − − Vdd2 P
178 L1 96 L1 − − Vss2 G
179 M1 97 M1 90 A11 Vdd1 P
180 M6 − − − − SDRDQM1 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
181 K1 98 K1 − − SDAT00 B CMOS 3−State 2/4/8/10 mA PU/PD Vdd2 3ICUD/3T2
182 L6 99 L6 − − SDCLK0 O − 3−State 2/4/8/10 mA − Vdd2 3T2(4)(8)(10)
183 L5 100 L5 − − SDCMD0 B CMOS 3−State 2/4/8/10 mA PU/PD Vdd2 3ICUD/3T2
184 K7 − − − − SDRADDR8 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
185 M7 − − − − SDRCAS O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
186 N5 − − − − Vdd2 P
187 N4 − − − − Vss2 G
188 N1 101 N1 91 B11 SIN0 I 3A − − − AvddADC 3A
189 P1 102 P1 92 B10 SIN1 I 3A − − − AvddADC 3A
190 R1 103 R1 93 C9 SIN2 I 3A − − − AvddADC 3A
191 N2 104 N2 94 C11 AVddADC P
192 P2 105 P2 − − SIN3 I 3A − − − AvddADC 3A
193 R2 106 R2 − − SIN4 I 3A − − − AvddADC 3A
194 P3 107 P3 − − SIN5 I 3A − − − AvddADC 3A
195 R3 108 R3 − − SIN6 I 3A − − − AvddADC 3A
196 P4 109 P4 − − SIN7 I 3A − − − AvddADC 3A
197 R4 110 R4 95 C10 AVssADC G
198 P5 111 P5 96 E8 AVssUSBPHY G
199 R5 112 R5 97 D11 USBEXT0
200 P6 113 P6 98 D9 AVddUSBPHY
201 R6 114 R6 99 D10 USBDM B 3A 3A − − AVddUSBPHY
202 P7 115 P7 100 E9 AVssUSBPHY G
203 R7 116 R7 101 E10 USBDP B 3A 3A − − AVddUSBPHY
204 P8 117 P8 102 F8 DVddUSBPHY
205 R8 118 R8 103 F9 USBVBUS I − − −
206 P9 119 P9 104 F10 AVddUSBPHY
207 R9 120 R9 105 F11 USBID B 3A 3A − − AVddUSBPHY
208 R10 121 R10 106 G8 VddXT1 P
209 R11 122 R11 107 G9 XIN1 I X − − − VddXT1 X
210 P10 123 P10 108 G10 VssXT1 G
211 P11 124 P11 109 G11 XOUT1 O − X − − VddXT1 X
212 N10 − − − − Vss1 G
213 N9 − − − − Vdd1 P
214 N12 − − − − Vdd2 P
215 N6 − − − − XTALINFO0 B Schmitt 3−State 2/4/8 mA PU Vdd2 3ISU/3T2
216 N11 − − − − Vss2 G
217 L7 125 L7 110 F7 SDO0/
218 L8 126 L8 111 F6 SCK0/
219 N7 − − − − SDRDQM0 O − 3−State 2/4/8 mA − Vdd2 3T2(4)(8)
220 J8 − − − − EXA15/
221 R12 127 R12 112 H11 Vdd1 P
222 K8 − − − − EXA10/
223 L12 128 L12 − − EXA3/
224 M8 − − − − EXA17/
225 N8 − − − − EXD3/
226 J9 − − − − EXA16/
227 K9 − − − − EXA18/
228 P12 129 P12 113 J11 Vss2 G
229 L9 130 L9 114 H10 SCL0/
230 L10 131 L10 115 J10 SDI0/
231 L11 132 L11 116 H9 SDA0/
232 M9 − − − − EXA9/
233 K10 − − − − NCS0/
234 R13 133 R13 117 K11 Vdd2 P
235 M10 − − − − EXD1/
236 M11 − − − − EXA5/
237 N13 − − − − EXA8/
238 P14 134 P14 118 J9 NWRENWRL/
239 R14 135 R14 119 K10 SWDCLK/
240 P13 136 P13 120 L11 Vss1 G
- RTCINT (open drain Output) 3.6 V tolerant.
Figure 6. Input/Output Circuit
Figure 6. Input/Output Circuit (continued)
- Vdd2, VddSD1 (IO Pwr Grp of Pin Assignment).
10.DRVcnt: 2/4/8 mA, 2/4/8/10 mA, etc. Drivability switch control signal.
XA: Package Code = “XA”, RA: Package Code = “RA”, RB: Package Code = “RB”, (RA and RB are under planning). Table 17. TERMINAL STATE TABLE
Table 17. TERMINAL STATE TABLE (continued)
*“/C0068” Means a port is available for each package. “PD” means pull down.
- Default function is port function set by NRES = Low.
12.NRES = High(ii) occurs just after NRES = Low(i). 13.This terminal is configured as an output terminal with PU disabled, and used as QSCS for the SPI I/F chip select during serial flash boot mode. 14.This terminal is configured as an output terminal and used as the boot monitor port during Internal ROM boot.
**Table 18. MAXIMUM RATINGS (*VSS* = 0V)** should not be assumed, damage may occur and reliability may be affected.
Table 19. RECOMMENDATION OPERATING CONDITIONS (TA = −20/C0053C to +65/C0053C) the Recommended Operating Ranges limits may affect device reliability. 16.APB clock needs 57.5 MHz or less. any voltage over the 1.8 V voltage range to Vdd2. short period, don’t supply not only the 3.3 V voltage range but also any voltage over the 1.8 V voltage range to VddSD1. 19.While USB is used (including USB suspend mode). 21.While used as GPO (general purpose output) the output of which can be controlled by registers. The power domains of Vdd1, DVddUSBPHY1, AVddPLL1, AVddPLL2, VddXT1 are divided, and different voltages can be supplied. If power is supplied to one of the power supply pins above, all the other power supply pins should also be supplied. addition, VddRTC can be supplied if BACKUPB is set to low, while other power supply pins are not supplied.
Table 20. RECOMMENDED OPERATING CONDITIONS 22.Audio blocks run on a clock of 256 * Fs(sampling frequency). However, Class−D AMP, etc. run at 384 * Fs(sampling frequency). These clocks are generated from 768 * Fs(Base Clock) divided by 3 and 2 respectively. 23.MP3 Decoder runs on a clock of 384 * Fs(sampling frequency of MPEG1 mode). 24.MP3 Encoder runs on a clock of 192 * Fs(sampling frequency of MPEG1 mode). 26.It is a reference level in Ta = 25/C0095C. Adjustment is necessary by the situation of the set.
Table 21. DC CHARACTERISTICS
Table 21. DC CHARACTERISTICS (continued) Table 22. DC CHARACTERISTICS
Table 22. DC CHARACTERISTICS (continued) performance may not be indicated by the Electrical Characteristics if operated under different conditions.
27.Set DAMPCTL register as below. This DC characteristics can be applied while Class−D AMP used as GPO. Table 23. PLL1 (SYSTEM) 28.Power up and power down timing of AVddPLL1 and Vdd1 should be as close as possible. 29.Electrical specifications are based on simulation results. 30.PLL lock time and appropriate LPF circuit depend on phase comparison frequency (Fref). Table 24. PLL1 SETTING FOR XT1 OSCILLATION
Table 25. LOOP FILTER FOR PLL1 external loop filter use, the loop filter parameters need to be attached externally. 32.Each value must be supplied by external resistor and capacitor. Refer to PLL1 (System) in Application.
Table 26. AUDIO PLL 33.Power up and power down timing of AVddPLL2 and Vdd1 should be as close as possible. 34.Electrical specifications are based on simulation results. 35.PLL lock time and appropriate LPF circuit depend on phase comparison frequency (Fref). Table 27. PLL2 SETTING FOR XT1 OSCILLATION
16 KHz
32 KHz
64 KHz
128 KHz
22.05 KHz
44.1 KHz
88.2 KHz
176.4 KHZ
24 KHZ
48 KHz
96 KHz
192 KHz
Table 27. PLL2 SETTING FOR XT1 OSCILLATION (continued)
Table 28. PLL2 SETTING FOR BCLK
Table 28. PLL2 SETTING FOR BCLK (continued)
Table 29. LOOP FILTER FOR PLL2
12 MHz
19.2 MHz
24 MHz
use, the loop filter parameters need to be attached externally. 39.Each value need to be supplied by external resistor and capacitor. Refer to PLL2 (Audio) in Application. External loop filter depends on XT1 frequency regardless of whether BCLK = 32 Fs, 48Fs, or 64 Fs is used in PLL2. Table 30. CLASS−D AMP 40.Set 0x3ff00 to Drivability set register DZINP in “DAMPCTL” described in the “Audio Functions User’s Manual”.
Table 31. XTAL CHARACTERISTICS be used with this product depends on the following table. Table 32. XT1 FREQUENCY internally based on the XTALINFO[1:0] terminal input during ROM boot. Table 33. 12BIT ADC CONVERTER CHARACTERISTIC 43.Electrical specifications are based on simulation results. 44.Speed control bit in “ADC” described in the “System Functions User’s Manual ”. The USB−PHY supports the following standards.
- Universal Serial Bus Specification, Revision 2.0
- Battery Charging Specification, Revision 1.2 (ACA is not supported)
- On−The−Go and Embedded Host Supplement to the USB Revision 2.0 Specification, Revision 2.0 (ADP is not supported) XA and RB are available to Device only.
- [Condition] External load 15 pF to 40 pF
Figure 9. AC Characteristic − I2C
- [Applied Pin] − Clock: SCK1 − Output: SDI1, SDO1, SWP1, SHOLD1, QSCS − Input: SDI1, SDO1, SWP1, SHOLD1 Table 38. I/O Voltage (Vdd2) 2.7 V to 3.6 V 1.7 V to 1.95 V Unit External Load / I/O Drivability 12 pF to 26 pF / 10 mA 6 pF to 12 pF / 8 mA 23 pF to 30 pF / 8 mA 10 pF to 23 pF / 4 mA Item Symbol Min Max Min Max SFIFSEL2 = 0 (Note 48) Clock frequency fclk − 40 − 40 MHz Input setup time tISU 4.5 − 4.5 − ns Input hold time tIH 6.0 − 6.0 − ns Output Delay time tODLY 1.0 5.5 1.0 5.5 ns SFIFSEL2 = 1 (Note 48) Clock frequency fclk − 42.5 − 42.5 MHz Input setup time tISU 4.8 − 4.8 − ns Input hold time tIH 7.0 − 7.0 − ns Output Delay time tODLY 1.0 6.8 1.0 6.8 ns 48.SFIFSEL2 is the value of S−Flash I/F select register (SFIFSEL) bit2 described in “System Controller” described in the “System Functions User’s Manual”. XMC External Memory Bus Timing (For RA only)
- [Condition] Vdd1 = 0.95 V to 1.155 V , Vdd2 = 2.7 V to 3.6 V , TA = −20°C to +65°C External load 15 pF to 40 pF External Memory Bus Read
Figure 12. AC Characteristics − External Memory Bus Read Timing
Figure 13. AC Characteristics − External Memory Bus Write Timing 49.T: BASIC clock rate (frequency = Farm). Regarding Tacs, Tcos, Tpgwt, Tcoh, refer to the “XMC” chapter in the “System Functions User’s Manual”. In write operation, even when Tpgwt (programmable wait register) = 0 or 1, equivalent to Tpgwt = 2.
- [Condition] External load 5 to 15 pF
Figure 14. AC Characteristics − SDRAM Interface
- [Applied Pin] − Clock: SDRCLK − Output: SDRCKE, SDRCS, SDRWE, SDRCAS, SDRRAS, SDRDQM[1:0], SDRADDR[10:0], SDRBA[1:0], SDRDA TA[15:0] − Input: SDRDATA[15:0] Table 40. I/O Voltage (Vdd2) 2.7 V to 3.6 V 1.7 V to 1.95 V Unit External Load 5 pF to 15 pF I/O Drivability 8 mA 8 mA Item Symbol Min Max Min Max Clock frequency fclk − 52 − 58 MHz Input set−up time tISU 2.8 − 2.8 − ns Input hold−up time tIH 1.8 − 1.8 − ns Output Delay time tODLY 1.6 3.4 1.6 3.4 ns 50.Address becomes valid 1 cycle before the timing when CS becomes active. Address is stable while CS is active.
- [Condition] External load 6 to 30 pF Clock (from SOoC) Input (to SoC) Output (from SoC) tODLY(max) tODLY(min) tISU tIH
Figure 15. AC Characteristics − PSRAM Interface
- [Applied Pin] − Clock: PSM_SCK − Output: PSM_SDI, PSM_SDO, PSM_DAT2, PSM_DAT3, PSM_CS − Input: PSM_SDI, PSM_SDO, PSM_DAT2, PSM_DAT3 Table 41. I/O voltage (Vdd2) 2.7V to 3.6V 1.7V to 1.95V Unit External load / I/O drivability 12pF to 26pF / 10mA 6pF to 12pF / 8mA 23pF to 30pF / 8mA 10pF to 23pF / 4mA Item Symbol Min Max Min Max Clock frequency fclk − 52 − 100 MHz Input setup time tISU 4.12 − 3 − ns Input hold time tIH 1.5 − 1.5 − ns Output Delay time tODLY 2 7 2 7 ns
- [Condition] External load 5 pF to 15 pF Master Mode
Figure 16. Master Mode
- [Applied Pin] − Clock: BCK0, BCK1 − Output: LRCK0, LRCK1, DOUT0, DOUT1 − Input: DIN0, DIN1 Table 42. I/O Voltage (Vdd2) 2.7 V to 3.6 V 1.7 V to 1.95 V Unit External Load / I/O Drivability 8 pF to 15 pF / 8 mA 5 pF to 8 pF / 4 mA 8 pF to 15 pF / 8 mA 5 pF to 8 pF / 4 mA Item Symbol Min Max Min Mix BCKI Low period tBCKIL 38.0 − 38.0 − ns BCKI High period tBCKIH 38.0 − 38.0 − ns DIN setup time tDINS 8.0 − 8.0 − ns DIN hold time tDINH 9.0 − 8.0 − ns LRCK delay time tLRCKO −13.0 13.0 −11.5 11.5 ns DOUT delay time tDOUT −13.0 13.0 −11.5 11.5 ns
Figure 17. Slave Mode
- [Applied Pin] − Clock: BCK0, BCK1 − Output: DOUT0, DOUT1 − Input: LRCK0, LRCK1, DIN0, DIN1 Table 43. I/O Voltage (Vdd2) 2.7 V to 3.6 V 1.7 V to 1.95 V Unit External Load / I/O Drivability 8 pF to 15 pF / 8 mA 5 pF to 8 pF / 4 mA 8 pF to 15 pF / 8 mA 5 pF to 8 pF / 4 mA Item Symbol Min Max Min Max BCKI Low period tBCKIL 30.0 − 30.0 − ns BCKI High period tBCKIH 30.0 − 30.0 − ns DIN setup time tDINS 8.0 − 8.0 − ns DIN hold time tDINH 8.0 − 8.0 − ns LRCK setup time tLRCKIS 8.0 − 8.0 − ns LRCK hold time tLRCKIH 8.0 − 8.0 − ns DOUT delay time tDOUT −13.0 13.0 −11.5 11.5 ns
- [Condition] External load 6 to 40 pF Normal (Default) Mode
Figure 18. Normal (Default) Mode
- [Applied Pin] − Clock: SDCLK0, SDCLK1, SDCLK2 − Output: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] − Input: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] Table 44. I/O Voltage (Vdd2, VddSD1) 2.7 V to 3.6 V Unit External Load / I/O Drivability 12 pF to 40 pF / 10 mA 6 pF to 12 pF / 8 mA Item Symbol Min Max Clock Frequency fPP 0 25 MHz Clock low time tWL 10 − ns Clock high time tWH 10 − ns Clock rise time tTLH − 10 ns Clock fall time tTHL − 10 ns Input set−up time (from SD to SoC) tISU 5.9 − ns Input hold−up time (from SD to SoC) tIH 0 − ns Output Delay time during Data Transfer Mode (from SoC to SD) tODLY 5.1 14.0 ns
Figure 19. High−Speed Mode
- [Applied Pin] − Clock: SDCLK0, SDCLK1, SDCLK2 − Output: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] − Input: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] Table 45. I/O Voltage (Vdd2, VddSD1) 2.7 V to 3.6 V Unit External Load / I/O Drivability 12 pF to 40 pF / 10 mA 6 pF to 12 pF / 8 mA Item Symbol Min Max Clock Frequency fPP 0 50 MHz Clock low time tWL 7 − ns Clock high time tWH 7 − ns Clock rise time tTLH − 3 ns Clock fall time tTHL − 3 ns Input set−up time (from SD to SoC) tISU 5.9 − ns Input hold−up time (from SD to SoC) tIH 2.5 − ns Output Delay time (from SoC to SD) tODLY 14.0 2.0 ns
Figure 20. SDR25 Mode
- [Applied Pin] − Clock: SDCLK0, SDCLK1, SDCLK2 − Output: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] − Input: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] Table 46. I/O Voltage (Vdd2, VddSD1) 1.7 V to 1.95 V Unit External Load / I/O Drivability 23 pF to 30 pF / 8 mA 15 pF to 23 pF / 4 mA 10 pF to 15 pF / 2 mA Item Symbol Min Max Clock Frequency fPP 0 50 MHz Clock rise time tTLH − 2.9 ns Clock fall time tTHL − 2.9 ns Input set−up time (from SD to SoC) tISU 5.9 − ns Input hold−up time (from SD to SoC) tIH 1.5 − ns Output Delay time (from SoC to SD) tODLY 0.9 17.0 ns
Figure 21. SDR50 Mode
- [Applied Pin] − Clock: SDCLK0, SDCLK1, SDCLK2 − Output: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] − Input: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] Table 47. I/O Voltage (Vdd2, VddSD1) 1.7 V to 1.95 V Unit External Load / I/O Drivability 23 pF to 30 pF / 8 mA 15 pF to 23 pF / 4 mA 10 pF to 15 pF / 2 mA Item Symbol Min Max Clock Frequency fPP 0 57 MHz Clock rise time tTLH − 2.9 ns Clock fall time tTHL − 2.9 ns Input set−up time (from SD to SoC) tISU 8.0 − ns Input hold−up time (from SD to SoC) tIH 1.4 − ns Output Delay time (from SoC to SD) tODLY 0.9 14.6 ns
Figure 22. DDR50 Mode
- [Applied Pin] − Clock: SDCLK0, SDCLK1, SDCLK2 − Output: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] − Input: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] Table 48. I/O Voltage (Vdd2, VddSD1) 1.7 V to 1.95 V Unit External Load / I/O Drivability 23 pF to 30 pF / 8 mA 15 pF to 23 pF / 4 mA 10 pF to 15 pF / 2 mA Item Symbol Min Max Clock Frequency fPP 0 40 MHz Clock rise time tTLH − 2.9 ns Clock fall time tTHL − 2.9 ns Input set−up time (from SD to SoC) tISU 5.0 − ns Input hold−up time (from SD to SoC) tIH 1.4 − ns Output Delay time (from SoCI to SD) tODLY 0.9 9.5 ns
- [Condition] External load 6 to 40 pF Normal (Default) Mode
Figure 23. Normal (Default) Mode
- [Applied Pin] − Clock: SDCLK0, SDCLK1, SDCLK2 − Output: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] − Input: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] Table 49. I/O Voltage (Vdd2, VddSD1) 2.7 V to 3.6 V 1.7 V to 1.95 V Unit External Load / I/O Drivability 12 pF to 40 pF / 10 mA 6 pF to 12 pF / 8 mA 23 pF to 30 pF / 8 mA 15 pF to 23 pF / 4 mA 10 pF to 15 pF / 2 mA Item Symbol Min Max Min Max Clock Frequency fPP 0 26 0 26 MHz Clock low time tWL 10 − 10 − ns Clock high time tWH 10 − 10 − ns Clock rise time tTLH − 3 − 3 ns Clock fall time tTHL − 3 − 3 ns Input set−up time (from SD to SoC) tISU 11.5 − 11.5 − ns Input hold−up time (from SD to SoC) tIH 9.0 − 9.0 − ns Output Delay time (from SoC to SD) tODLY 10.0 27.5 10.0 27.5 ns
Figure 24. High−Speed SDR Mode
- [Applied Pin] − Clock: SDCLK0, SDCLK1, SDCLK2 − Output: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] − Input: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] Table 50. I/O Voltage (Vdd2, VddSD1) 2.7 V to 3.6 V 1.7 V to 1.95 V Unit External Load / I/O Drivability 12 pF to 40 pF / 10 mA 6 pF to 12 pF / 8 mA 23 pF to 30 pF / 8 mA 15 pF to 23 pF / 4 mA 10 pF to 15 pF / 2 mA Item Symbol Min Max Min Max Clock Frequency fPP 0 52 0 52 MHz Clock low time tWL 7 − 7 − ns Clock high time tWH 7 − 7 − ns Clock rise time tTLH − 3 − 3 ns Clock fall time tTHL − 3 − 3 ns Input set−up time (from SD to SoC) tISU 5.4 − 5.4 − ns Input hold−up time (from SD to SoC) tIH 3.0 − 3.0 − ns Output Delay time (from SoC to SD) tODLY 3.0 16.1 3.0 16.1 ns
Figure 25. High−Speed DDR Mode
- [Applied Pin] − Clock: SDCLK0, SDCLK1, SDCLK2 − Output: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] − Input: SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] Table 51. I/O Voltage (Vdd2, VddSD1) 2.7 V to 3.6 V 1.7 V to 1.95 V Unit External Load / I/O Drivability 12 pF to 40 pF / 10 mA 6 pF to 12 pF / 8 mA 23 pF to 30 pF / 8 mA 15 pF to 23 pF / 4 mA 10 pF to 15 pF / 2 mA Item Symbol Min Max Min Max Clock Frequency fPP 0 30 0 33 MHz Clock rise time tTLH − 3 − 3 ns Clock fall time tTHL − 3 − 3 ns INPUT CMD Input set−up time (from SD to SoC) tISU 19.5 − 16.4 − ns Input hold−up time (from SD to SoC) tIH 2.4 − 2.4 − ns OUTPUT CMD Output Delay time (from SoC to SD) tODLY 3.0 29.0 3.0 26.0 ns INPUT DAT Input set−up time (from SD to SoC) tISU 9.6 − 8.1 − ns Input hold−up time (from SD to SoC) tIH 1.4 − 1.4 − ns OUTPUT DAT Output Delay time (from SoC to SD) tODLY 2.5 14.1 2.5 12.6 ns
- [Applied Pin] − Input: CTS1 − Output: TXD1 Table 53. Item Condition Symbol Min Max Unit Delay time Completing preparation to transmit the current TXD data by setting registers at CTS1 = high From the negative edge Tdlycts − 6T+20 ns CTS Setup time (not to transmit the next TXD data) From end of the last StopBit Tsetupcts 3T+20 − ns 52.T: UART functional clock rate 53.In using hardware flow control by CTS/RTS, if the CTS setup time above is NOT met, the next TXD data will be transmitted at the time of having prepared it regardless of the CTS level. RTS Timing
Figure 28. RTS Timing
- [Applied Pin] − Input: RXD1 − Output: RTS1 Table 54. Item Condition Symbol Min Max Unit Delay Time Receiving the current RXD data with 15 bytes of data existing in the Reception FIFO or Receiving the current RXD data without using Reception FIFO From 1.5 bits before the end of the last StopBit Tdlyrts − 4T+20 ns 54.T: UART functional clock rate
The configuration of the PLL2 circuit is shown below. power supply lines to eliminate noise. VCNT2 must be open in this case. Figure 33. PLL2(Audio) for Internal Loop Filter Figure 34. PLL2(Audio) for External Loop Filter 60.The part values are for reference only. Adjustments may be required depending on the specific setup.
The configuration of the ADC circuit is shown below. 62.Unused input pins of SIN[0−7] should be directly connected to AVssADC. Figure 35. 12bit AD Converter
www.onsemi.com LCR Filter Example L (/C0109H) C (/C0109F) Rd (/C0087) Type A 220 0.22 0 − 10 Type B 47 1 5 − 10 63.Rd doesn’t include parasitic resistance of L. 64.Add a bypass condenser (0.1 μF) between AVddDAMPL and AVssDAMPL, AVddDAMPR and AVssDAMPR as close as possible to the terminals 65.Add a large electrolyte capacitor (220μF or more recommended) to AVddDAMPL, AVddDAMPR terminal for Single−End form to reject the noise and reduce the pumping phenomenon of Class−D AMP. 66.Check the voltage level of AVddDAMPL, AVddDAMPR and make sure not to exceed 1.65 V (recommended operating voltage) by using playback of 20 Hz, 0db (full scale) sine wave 67.Resistor Rd reduces the output level of Class−D AMP, and is related to the values of L and C used. Please choose a resistance value (Rd) to fit the actual system. Please note that Rd value must be determined based on the parasitic resistance of the inductor L. 68.While the Class−D AMP outputs LOUT and ROUT are used as GPO, the maximum supply voltage to AVddDAMPL and AVddDAMPR is 1.95 V. In this case, the LC filter cannot be connected to LOUT and ROUT to avoid damage from overvoltage via the pumping phenomenon. Power Supply Class−D AMP power supply to (A VddDAMPL, A VddDAMPR) must use a transient response and good power supply. When using a power supply where the transient response is bad and the capacity of the capacitor is small, a peculiar pumping phenomenon to the Class−D AMP is generated. The power supply voltage must not exceed the recommended operating range when the pumping phenomenon occurs. The Class−D AMP output is PWM. The power supply noise affects the output of the Class−D AMP. Power sources which have large internal impedance such as dry cell should not be directly connected to the power supply of the Class−D AMP, and those which have large switching noise such as switching regulator are not suitable and need to be taken care of.
Figure 40. Digital Mic Configuration
The configuration of the I2C circuit is shown below. Figure 41. I2C Configuration
Figure 42. S−Flash I/F Circuit
Figure 45. JTAG Interface for LPDSP32 bugger and the SoC is not mandatory. abled before the reset release of LPDSP 32.
Figure 46. SWD Interface for Cortex−M3
The configuration of the BMODE circuit is shown below. Figure 47. BMODE Configuration pins, and avoid long wiring patterns on the board. els to be assigned on BMODE.
- Don’t raise power supply steeply.
- Place bypass capacitors at each point closest to each power supply terminal, and place a power circuit at the point closest to the power supply terminals which it can supply.
- This SoC has circuits to protect from electrostatic discharge. The rush current flows in accordance with the steepness of rising curve of power supply.
www.onsemi.com 102 INTERNAL POWER DOMAIN CONTROL This SoC has fifteen power isolated region of internal core for leakage current reduction, these can be power supply OFF separately. Power isolated region PD−X (X means one of the fifteen region PD 1 to J) described in the table below. Power ON / OFF for each power domain is controlled by the appropriate bit of System Controller of the power control register (LSISTBY). However, when controlling the power control register (LSISTBY), you must also control the ISOLATION control register (ISOCNT) as required. Please refer to the “System Controller” chapter in the “System Functions User’s Manual” for details. Each power domain and its contents, along with the corresponding flags in the power control register (LSISTBY) and ISOLATION control register (ISOCNT) is as follows. Table 57. Name Content LSISTBY ISOCNT PD−1 Internal ROM Bit17 STBY1 Bit17 ISOCNT1 PD-2 Internal SRAM(seg 0B) Bit18 STBY2 Bit18 ISOCNT2 PD-3 Internal SRAM(seg 1) Bit19 STBY3 Bit19 ISOCNT3 PD-4 Internal SRAM(seg 2) Bit20 STBY4 Bit20 ISOCNT4 PD-5 Internal SRAM(seg 3/4) Bit21 STBY5 Bit21 ISOCNT5 PD-6 Internal SRAM(seg 5A) Bit22 STBY6 Bit22 ISOCNT6 PD-7 Internal SRAM(seg 5B) Bit23 STBY7 Bit23 ISOCNT7 PD-8 Internal SRAM(seg 6) Bit24 STBY8 Bit24 ISOCNT8 PD-9 Internal SRAM(seg 7B) Bit25 STBY9 Bit25 ISOCNT9 PD-10 Internal SRAM(seg 7A/8/9) Bit26 STBY10 Bit26 ISOCNT10 PD−A Audio Block Bit0 STBYA Bit0 ISOCNTA PD−E USB 2.0 Controller SRAM Bit4 STBYE Bit4 ISOCNTE PD−G Cache for S−Flash I/F Bit6 STBYG Bit6 ISOCNTG PD−H SD Card I/F Bit7 STBYH Bit7 ISOCNTH PD−J USB 2.0 PHY Bit9 STBYJ Bit9 ISOCNTJ
www.onsemi.com 103 POWER SUPPLY SEQUENCE To ensure system stability, the power supply lines must be powered on/off in a specific sequence, based on the power supply group they are in, as described in this section. Power Supply Groups The power supply lines of the SoC can be grouped as follows: 1. Vdd*(Internal) – Internal core, analog power supply (1 V power supply) Vdd1, VddXT1, A VddPLL1, A VddPLL2, DVddUSBPHY1 2. Vdd*(IO) – External IO power supply (1.8 V / 3 V power supply) Vdd2, VddSD1, A VddUSBPHY2, A VddUSBPHY18, A VddADC, A VddDAMPL, A VddDAMPR 3. VddRTC – The RTC power supply (This is a dedicated power supply line whose on/off sequence is described separately in the next section) Recommendation The recommended basic sequence for powering on/off of the power supply lines is as follows. (Simultaneous power on/off is acceptable)
- Power on: ♦ Vdd*(Internal) −> Vdd*(IO) −> Vsig(Signal)
- Power off: ♦ Vsig(Signal) −> Vdd*(IO) −> Vdd*(Internal) NOTE: During power on, the sequence of Vdd*(Internal) −> Vdd*(IO) causes a SoC hard reset which prevents IO glitches. Powering on the Vdd*(IO) lines while the Vdd*(Internal) lines are powered off may generate glitches on the IO signals and the flow of through current. It is recommended that you follow the sequence above in order to avoid this. In addition, Vsig(Signal) means voltage appearance of IO signals. In the Vdd*(IO) group, the power on sequence for the USB PHY must occur in the order A VddUSBPHY18 −> A VddUSBPHY2, while the power off sequence must occur in the order AVddUSBPHY2 −> A VddUSBPHY18. RTC has its own dedicated power supply and power on/off sequence which is described in the following section.
sequence of RTC are described as follows. Figure 48. Timing Sequence for General RTC Mode
Figure 49. Internal Control Logic for Isolation
signal can generate the power on sequence. to Low. (The RTC operation stops). Figure 50. Timing Sequence for Keyint RTC Mode
www.onsemi.com 107 Device Package Shipping (Qty / Packing)† LC823455XATBG WLCSP120, 4.086x4.086 (Pb−Free / Halogen Free) 1000 / Tape & Reel LC823455RAH−2H (Under planning) LFBGA240, 11.0x11.0 (Pb−Free / Halogen Free) 880 / Tray JEDEC LC823455RB−2H (Under planning) LFBGA136, 11.0x11.0 (Pb−Free / Halogen Free) 880 / Tray JEDEC †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Arm, the Arm logo, AMBA, and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. Bluetooth is a registered trademark of Bluetooth SIG.
WLCSP120, 4.086x4.086x0.62 CASE 567WG ISSUE O DATE 16 APR 2018 XXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week /C0071= Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ /C0071”, may or may not be present. Some products may not follow the Generic Marking. GENERIC MARKING DIAGRAM* XXXXXXXXXXXX AWLYYWW /C0071 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON87275GDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1WLCSP120, 4.086x4.086x0.62 © Semiconductor Components Industries, LLC, 2018 www.onsemi.com
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