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Technical content
Features
32bit LPDSP32 - SRAM (246KB) PM 75KB (40KB + 35KB : ISOLATED) DMA 170KB (16KB + 154KB : ISOLATED) DMB 1KB (ISOLATED) ISOLATED area : Power ON/OFF control is available by register. - ROM (264.5KB) PM 227.5KB (ISOLATED) DMA 34KB (ISOLATED) DMB 3KB (ISOLATED) ISOLATED area : Power ON/OFF control is available by the register. - SIO (Clock Serial IO 2ch) SIO0 : Ch0 eSIO (Clock speed = Sysclk/1 (max)) program load and execute is possible using Serial Flash (after internal ROM Boot) SIO1 : Ch1 SIO (Clock speed = Sysclk/8 (max)) - UART (1ch) - I 2C (1ch Single Master, Full/Standard) - Plain Timer (2ch) Timer0 : w/ Watch Dog Timer Timer1 : w/o Watch Dog Timer and XT1 operation - Multiple Timer (2ch) PWM output (1ch) - RTC (Real Time Clock) Operating voltage is independent of internal core operating voltage. Only RTC power supply can be active during all others inactive (ISOLATED). - SD card IF (2ch) (w/o CPRM) eSD/eMMC can be connected. SD ch0 : program load and execute using eSD/eMMC (after internal ROM Boot) is possible. SD ch1 : SD card - USB2.0 (480Mbps/12Mbps) Device IF. built-in PHY - 10bit A/D converter (3ch) - GPIO (31ch) (GPIOs share the terminals with other functions. Refer to the terminal list in detail). LCD controller, LCD Driver. 18SEG * 8COM, 1/8Duty, 1/4Bias - Internal ROM Boot is possible. Continued on next page. CMOS LSI Audio Processing System LSI for MP3 Record and Playback Devices
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of this data sheet. * I2C Bus is a trademark of Philips Corporation. TQFP128L(14X14)
No.A2171-2/20 Continued from preceding page. - Firmware writing function. The firmware reading from SD ch1 and writing to the following devices: Serial Flash connected SIO0. eMMC/eSD connected SD ch0. - JTAG (for debugger) Audio Functions - Record and Playback Compression method : MP3 1 (MPEG1/2/2.5 Layer3). Stereo/Mono compatible. Sampling frequences : 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, and 48kHz Bitrate : 8kbps (*1) to 320kbps (for Decoder-VBR) (*1) Encoder supports only Mono (one channel) for 8Kbps. - Adjusting the playback speed Fast playback : 1.0 times to 2.0 times 10 steps. Slow playback : 0.5 times to 1.0 times 10 steps. - Multipurpose filter - Audio data automatic transfer function The audio buffer executes the data transfer between internal SRAM (DMA) and the audio block. Wait cycle(s) is inserted to the LPDSP32 access to the SRAM while the audio buffer accesses to internal SRAM(DMA). - Digital volume, digital mute, BEEP, and level meter The interrupt generation function at the operation completion (e.g. interrupt at mute completion). - Audio timer LR clock count and the interrupt generation function. - Flexible PCM audio interface (two interfaces) Master/Slave Mode Selectable Data Formats : I2S mode etc. - Sample Rate Converters 0.5times to 64 times conversion range. - Digital microphone IF (2ch) Analog function - Microphone amplifier 0/18/24/30dB (2ch) - PGA with ALC -12dB to 35.25dB in 0.75dB steps (2ch) - 16 bit ΔΣADC (2ch) - Digital filter for 16 bits ΔΣDAC (2ch) - AB class amplifier The power supply only to AB class amplifier is possible (ISOLATED). Thermal shutdown circuit built-in Speaker amplifier (1ch BTL) 1dB to 4.5dB in 0.5dB steps Maximum output 300mW @3.0V, Speaker = 8[], 1dB Headphone amplifier (2ch) 0dB to 3dB in 1dB steps (Only same gain setting to 2ch is possible) Maximum output 5mW @3.0V, HeadPhone = 16[], Rd (Series) = 33[], 1dB Continued on next page. 1 MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and Thomson. Supply of this product does not convey license nor imply any right to distribute content created with this product in revenue-generating broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming applications (via Internet, intranets and/or networks), other content distribution systems (pay-audio or audio-on-demand applications and the like) or on physical media (compact discs, digital versatile discs, semiconductor chips, hard drives, memory cards and the like). Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An independent license for such use is required. For details, please visit http://mp3licensing.com/
No.A2171-3/20 Continued from preceding page. Clock - RCOSC : Internal RC oscillation. 1MHz (TYP.) - XT1 : Main XTAL. 32.768kHz. Used as an original oscillation of the system clock and the audio clock, and a RTC clock. - XT2 : Optional XTAL. 12MHz (TYP) etc. - PLL1 : For system clock generation (LPDSP32 is included). - PLL2 : For audio clock generation Specification Supply voltage : 1.3V (core, etc), 3.15V (Audio, USB, etc) Maximum operation frequency : 42MHz (DSP@1.3V) Package : 128pin TQFP Application IC Recorder, Audio Player Radio Recorder, Home Audio (Mini compo)
No.A2171-4/20 Specifications Absolute Maximum Ratings at VSS = 0V Parameter Symbol Domain of applicability Ratings Unit Supply voltage V DD1 VDDRTC AVDDPLL1 AVDDPHY1 0.3 to +1.8 V VDD2 VDDLCD AVDDPLL2 AVDDADC AVDDAADC AVDDADAC AVDDSPAMP AVDDPHY2 0.3 to +3.96 V Input voltage V I 0.3 to *VDD*+0.3 (Max 3.96) V Operating temperature Topr 20 to +75 C Storage temperature Tstg 55 to +125 C Recommended Operating Conditions at Ta = 20C to +75C Parameter Symbol Test Conditions min typ max Unit Supply voltage V DD1 1.15 1.3 1.65 V VDDRTC 0.9 1.5 1.65 V AVDDPLL1 1.15 1.3 1.65 V VDD2 2.7 3.15 3.3 V VDDLCD 2.7 3.15 3.3 V AVDDPLL2 2.7 3.15 3.3 V AVDDADC 2.7 3.15 3.3 V AVDDAADC 2.7 2.8 3.3 V AVDDADAC 2.7 2.8 3.3 V AVDDSPAMP 1.8 3.15 3.8 V AVDDPHY1 1.35 1.5 1.65 V AVDDPHY2 3.0 3.15 3.6 V Input voltage V IN 0 * V DD*V VIN3 (RTC) 0 3 . 6 V VIN_ADC (AN0-AN2). I_AN 300A 0 3 . 3 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Oper ating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A2171-5/20 DC Characteristics at Ta = 20C to +75C, VDD1 = 1.15V to 1.65V, VDD2 = 2.7V to 3.3V, VDDRTC = 0.9V to 1.65V Parameter Symbol Application Test Conditions min typ max Unit Input high voltage V IH 3ICUD 0.7 VDD2 V 3IS, 3ISUD Schmitt 0.75 VDD2 V 1IC 0.7 VDDRTC V 1IS Schmitt 0.7 VDDRTC V Input low voltage V IL 3ICUD 0.3 VDD2V 3IS, 3ISUD Schmitt 0.25 VDD2V 1IC 0.2 VDDRTC V 1IS Schmitt 0.2 VDDRTC V Input high leakage current I IH 3ICUD, 3IS, 3ISUD VIN = VDD2 10 A 1IC, 1IS V IN = 3.3V 10 A Input low leakage current I IL 3IS, 3ISUD V IN = VSS 10 A 1IC, 1IS V IN = VSSRTC 10 A Output high voltage V OH 3T2 I OH = 2mA V DD20.4 V 3T4 I OH = 4mA V DD20.4 V 3T4(8) I OH = 4mA (IOH = 8mA) VDD20.4 V 3T6(12) I OH = 6mA (IOH = 12mA) VDD20.4 V Output low voltage V OL 3T2 I OL = 2mA 0.4 V 3T4 I OL = 4mA 0.4 V 3T4(8) I OL = 4mA (IOL = 8mA) 0.4 V 3T6(12) I OL = 6mA (IOL = 12mA) 0.4 V OD3 I OL = 0.3mA 0.3 V Output leakage current I OZ 3T2, 3T4, 3T4(8), 3T6(12) When it outputs Hi-Z 10 10 A Pull-up resistor Rup 3ICUD, 3ISUD 30 80 190 k Pull-down resistor Rdn 3ICUD, 3ISUD 30 80 190 k
No.A2171-6/20 Package Dimensions unit : mm TQFP128 14x14 / TQFP128L CASE 932BA ISSUE O
No.A2171-7/20 Pin Assignment (Bonding Option) Direction Attribute I Input pin 3IS 3V Schmitt i nput 1IS 1V Schmitt input. (3V tolerant correspondence) O Output pin 3ICUD 3V CMOS inpu t pull-up/down 1IC 1V CMOS input (3V tolerant correspondence) B Bidirectional pin 3ISUD 3V Schmitt input pull-up/down OD3 1V 0.3mA open drain output (3V tolerant correspondence) P Power supply pin 3T2 3V 2mA tristate output 3T4 3V 4mA tristate ou tput X Oscillation amplifier 3T4(8) Tristate output with 3V 4mA/8mA switch function 3A 3V analog through 3T6(12) Tristate output with 3V 6mA/12mA switch function 1A 1V analog through TQFP128L Pin No. Name Direction Attribute
1 AV SSSPAMP P
2 AV DDSPAMP P
3 AVREFSP O 3A
4 HPINL/SPKINM I 3A
5 HPINR I 3A
6 AV SSADAC P
7 OUTMR O 3A
8 OUTML/OUTM O 3A
9 AV DDADAC P
10 AV SSAADC P
11 AVREF O 3A
12 AV DDAADC P
13 AINL I 3A
14 AINR I 3A
15 AV DDADC P
16 AN0 I 3A
17 AN1 I 3A
18 AN2 I 3A
19 V SS P
20 V DD2 P
21 V DD1 P
22 TIOCA0/P10 B/B 3ISUD/3T2
23 BMODE0 I 3IS
24 BMODE1 I 3IS
25 BMODE2 I 3IS
26 NRES I 3IS
27 SDCLK1/MCLK1/P00 O/B/B 3ISUD/3T6(12)
28 SDCMD1/LRCK1/P02 B/ O/B 3ISUD/3T4(8)
29 SDAT10/BCK1/P03 B/B/B 3ISUD/3T4(8)
30 SDAT11/DIN1/P04 B/I/B 3ICUD/3T4(8)
31 SDAT12/DOUT1/P05 B/O/B 3ICUD/3T4(8)
32 SDAT13/SDO1/P06 B/O/B 3ICUD/3T4(8)
33 SDWP1/SDI1/P01 I/I/B 3ISUD/3T2
34 SDCD1/SCK1/P0A I/B/B 3ISUD/3T2
35 SDCLK0/P14 O/B 3ICUD/3T6(12)
36 V DD2 P
37 V SS P
38 SDCMD0/P15 B/B 3ICUD/3T4(8)
Continued on next page.
No.A2171-8/20 Continued from preceding page. TQFP128L Pin No. Name Direction Attribute
39 SDAT03/P16 B/B 3ICUD/3T4(8)
40 SDAT02/P17/SYSCLK B/B/O 3ICUD/3T4(8)
41 SDAT01/P18/AUD0CLK B/B/O 3ICUD/3T4(8)
42 SDAT00/P19/AUD1CLK B/B/O 3ICUD/3T4(8)
43 V SS P
44 XIN2 I X
45 XOUT2 O X
46 AV DDPHY1(+VDD1) P
47 AV SSPHY1 P
48 AV SSPHY1 P
49 RREF B 3A
50 AV SSPHY2 P
51 AV DDPHY2 P
52 AV DDPHY2 P
53 AV SSPHY2 P
54 AV SSPHY2 P
55 AV SSPHY2 P
56 AV DDPHY2 P
57 DP B 3A
58 DM B 3A
59 AV SSPHY2 P
60 AV DDPHY2 P
61 COM0 O 3A
62 COM1 O 3A
63 COM2 O 3A
64 COM3 O 3A
65 V DDLCD P
66 VLCD1 O 3A
67 VLCD2 O 3A
68 VLCD3 O 3A
69 V SS P
70 V DD1 P
71 SEG0 O 3A
72 SEG1 O 3A
73 SEG2 O 3A
74 SEG3 O 3A
75 SEG4 O 3A
76 SEG5 O 3A
77 SEG6 O 3A
78 SEG7 O 3A
79 SEG8 O 3A
80 SEG9 O 3A
81 SEG10 O 3A
82 SEG11 O 3A
83 SEG12 O 3A
84 SEG13 O 3A
85 SEG14 O 3A
86 SEG15 O 3A
87 SEG16 O 3A
88 SEG17 O 3A
89 COM4 O 3A
90 COM5 O 3A
Continued on next page.
No.A2171-9/20 Continued from preceding page. TQFP128L Pin No. Name Direction Attribute
91 COM6 O 3A
92 COM7 O 3A
93 HPDET/SDI1/SCL/P1A I/I/O/B 3ISUD/3T2
94 HPMUTE/SDO1/SDA/P1 B O/O/B/B 3ISUD/3T2
95 JTDO/P1C O/B 3ICUD/3T2
96 JTDI/P1D I/B 3ICUD/3T2
97 JTMS/P1E I/B 3ICUD/3T2
98 JTCK/P1F I/B 3ICUD/3T2
99 V DD1 P
100 V DD2 P
(Internal Signal) I 3IS
101 V SS P
102 TXD/SCL/P12 O/ O/B 3ISUD/3T2
103 RXD/SDA/P13 I/B/B 3ISUD/3T2
104 SCK0/P07 B/B 3ISUD/3T4
105 SDO0/P08 O/B 3ISUD/3T4
106 SDI0/P09 I/B 3ISUD/3T2
107 MCLK0/DMCKO/SCK1/P0B B/O/B/B 3ISUD/3T2
108 DIN0/DMDIN/P0F I/I/B 3ISUD/3T2
109 DOUT0/P0E/NCS O/B/O 3ISUD/3T2
110 BCK0/P0C B/B 3ISUD/3T2
111 LRCK0/P0D O/B 3ISUD/3T2
112 VDET I 1IC
113 RTCINT O OD3
114 BACKUPB I 1IS
115 XOUT32K O X
116 XIN32K I X
117 V DDRTC P
(Internal Signal) I 1IS
118 V SSRTC P
119 AV DDPLL1 P
120 VCNT1 O 1A
121 V SS P
122 AV DDPLL2 P
123 VCNT2 O 3A
124 AV SSPLL2 P
125 HPOUTR O 3A
126 HPOUTL O 3A
127 SPOUTP O 3A
128 SPOUTN O 3A
No.A2171-10/20 Block Diagram PLL1 XT1 32.768kHz Sanyo 32bit DSP LPDSP32 Audio Buffer (Write To, Read From DMA) PLL2 ROM (3KB) Plain Timer0 Multiple Timer SD I/F eSIO (SIO1) UART 10bit A/D RTC 16bit A/D 16bit D/A (2ch/BTL) LPF AUDIO functions (SRC, VOLUME, etc) GPIO eSD eMMC LCD IRQ 15ch Audio Clock0 JTAG PWM PWM XT2 PGA(ALC) -12 to 35.25dB VDD1 VDD2 AVDDADC AVDDSPAMP VDDLCD Logic I/O 10bit A/D LCDCTL VDDRTC AVDDPLL1 AVDDPLL2 PLL1 PLL2 Firmware DL etc Ch0 Ch1 PRGDMIO SRAM (35KB) (40KB) MIC I2C Note - Refer to the pin assignment for port share - ISOLATED SRAMs and ROMs described in this figure can be power off by a register, in addition to the tiny SRAMs (not described in th is figure) in the SD I/F, USB2.0, SRC, 16bit D/A, DF. Digital MIC IF S/PPCM0 IN P/SPCM0 OUT S/PPCM1 IN P/SPCM1 OUT PDM LPF “Lch” or “+” “Rch” Speaker HeadPhone “-” “+” ROM (227.5KB) SRAM (154KB) (16KB) SRAM (1KB) ROM (34KB) PM DMA DMB Plain Timer1 LCD CTL LCD 18seg × 8com or 36seg × 4com(TBD) FUNCCLK1 FUNCCLK1 eSIO (SIO0) S-Flash Boot etc SIO Ch0 SIO Ch1 eMMC/eSD Boot XT1 RCOSC XT2 System Clock Boot monitor etc Arbiter “Lch” “Rch” AVDDADAC AVDDAADC USB2.0 HS Device USB2.0 PHY XT2 or XT2/2 AVDDPHY1 AVDDPHY2 DMBDMA Peripheral1Peripheral2Peripheral0 ISOLATED ISOLATED ISOLATED ISOLATED ISOLATED 0/18/24/30dB MIC AMP -12 to 35.25dB MIC 0/18/24/30dB MIC AMP 16bit A/D MUX DF + ALC PGA(ALC) Dig MIC ISOLATED ISOLATED 1 to 4.5dB 0 to 3dB(Lch, Rch common) OSCCON (System) OSCCON (Audio) Peripheral0 Clock Peripheral1 Clock Peripheral2 Clock FUNCCLK1 OSCCON (FUNC) FUNCCLK0 Audio Clock1 MCLK0, MCLK1 BCK0, BCK1 XT1 XT2 System Clock XT1 XT2 System Clock ON Semiconductor 32bit DSP LPDSP32
No.A2171-11/20 Pin Functions JTAG Pin name Pol. Type Description Num. JTDO/ P1C B JTAG test data output/ General purpose port 1 JTDI/ P1D B JTAG test data input/ General purpose port. The input level of the terminal JTDI is taken by rising edge of the terminal NRES. The value can be read as a register, and can be used as the operation mode setting. JTMS/ P1E B JTAG test mode selection/ General purpose port The input level of the terminal JTMS is taken by rising edge of the terminal NRES. The value can be read as a register, and can be used as the operation mode setting. JTCK/ P1F Pos/ B JTAG test clock/ General purpose port 1 Total 4 RTC Pin name Pol. Type Description Num. XIN32K Pos I 32.768kHz oscillation amplifier input (XT1) 1 XOUT32K - O 32.768kHz oscillation amplifier output (XT1) 1 VDET (RTCRSTB) Neg Neg I I Power supply watch comparison input There is an optional bonding as RTC reset input. RTCINT (PWRON) Neg O O RTC interrupt output (Normal: Hi-z, the interrupt generation: Low output). There is an optional bonding as main power supply ON/OFF control. BACKUPB (LINEFIXB) Neg Neg I I RTC operation mode selection There is an optional bonding as RTC isolator cutting and the connection. VDDRTC - P RTC block power supply. 1 VSSRTC - P RTC ground pin. 1 Total 7
No.A2171-12/20 SIO (synchronous serial) interface Ch0 (eSIO)/Timer PWM output/General purpose port Pin name Pol. Type Description Num. SCK0/ P07 Pos/ B Serial I/F Ch0 clock/ General purpose port (It is possible to use it as an external interrupt input.) SDO0/ P08 (SDO0(SIO0)) -(-) B O(B) Serial I/F Ch0 data output/ General purpose port (It is possible to use it as an external interrupt input). There is an optional bonding as serial I/F Ch0 data output (Data I/O 0 when at high speed operating). SDI0/ P09 (SDI0(SIO3)) -(-) B I(B) Serial I/F Ch0 data input/ General purpose port (It is possible to use it as an external interrupt input). There is an optional bonding as serial I/F Ch0 data input (Data I/O 3 when at high speed operating). TIOCA0/ P10 (VSS) B P MTM Ch0 A input capture and output capture/ General purpose port There is an optional bonding as VSS. Total 4 UART (asynchronization serial) interface/I2C interface/General purpose port Pin name Pol. Type Description Num. TXD/ SCL/ P12 B UART transmitted serial data output/ I2C clock output (open drain output)/ General purpose port (It is possible to use it as an external interrupt input). RXD/ SDA/ P13 B UART received serial data input/ I 2C data (open drain output)/ General purpose port (It is possible to use it as an external interrupt input). Total 2 Headphone control/SIO (synchronous serial) interface Ch1 (SDI, SDO)/I2C interface/General purpose port Pin name Pol. Type Description Num. HPDET/ SDI1/ SCL/ P1A Pos/ B Headphone insertion detection/ Serial I/F Ch1 data input/ I 2C clock output (open drain output)/ General purpose port (It is possible to use it as an external interrupt input). HPMUTE/ SDO1/ SDA/ P1B Pos/ B Headphone mute/ Serial I/F Ch1 data output/ I 2C data (open drain output)/ General purpose port Total 2
No.A2171-13/20 PCM interface Ch0/Digital mic interface/ SIO (synchronous serial) interface Ch1 (SCK)/General purpose port/RTC (KeyInt RTC model) Pin name Pol. Type Description Num. MCLK0/ DMCKO/ SCK1/ P0B Pos/ B PCM Ch0 master clock/ Digital mic clock output/ Serial I/F Ch1 clock/ General purpose port (It is possible to use it as an external interrupt input). BCK0/ P0C (NHOLD(SIO1)) (KEYINT1) B O(B) I PCM Ch0 bit clock/ General purpose port There is an optional bonding as serial I/F Ch0 hold output (Data I/O 1 when at high speed operating). There is an optional bonding as KEY interrupt1 (Notes: Operate in VDDRTC and the VSSRTC power supply). LRCK0/ P0D (NWP(SIO2)) (KEYINT0) B O(B) I PCM Ch0 LR clock/ General purpose port (It is possible to use it as an external interrupt input). There is an optional bonding as serial I/F Ch0 write protect output (Data I/O 2 when high speed operating). There is an optional bonding as KEY interrupt0 (Notes: Operate in VDDRTC and the VSSRTC power supply). DIN0/ DMDIN/ P0F B PCM Ch0 data input/ Digital mic data input/ General purpose port (It is possible to use it as an external interrupt input). DOUT0/ P0E/ NCS (NCS) Neg Neg O O PCM Ch0 data output/ General purpose port (It is possible to use it as an external interrupt input)/ CS for serial I/F Ch0 (When it boots from internal ROM and the program from SerialFlash connected to serial I/F Ch0 is loaded, it is used as CS control terminal of SerialFlash). There is an optional bonding as CS for serial I/F Ch0. Total 5
No.A2171-14/20 SD interface Ch0/General purpose port Pin name Pol. Type Description Num. SDCLK0/ P14 Pos/ B SD card I/F Ch0 clock output/ General purpose port 1 SDCMD0/ P15 B SD card I/F Ch0 command line/ General purpose port 1 SDAT03/ P16 B SD card I/F Ch0 data 3/ General purpose port 1 SDAT02/ P17/ SYSCLK O SD card I/F Ch0 data 2/ General purpose port/ System Clock output (for evaluation) SDAT01/ P18/ AUD0CLK O SD card I/F Ch0 data 1/ General purpose port/ Audio0 Clock output (for evaluation) SDAT00/ P19/ AUD1CLK O SD card I/F Ch0 data 0/ General purpose port/ Audio1 Clock output (for evaluation) Total 6 SD interface Ch1/PCM interface Ch1/SIO (synchronous serial) interface Ch1/General purpose port Pin name Pol. Type Description Num. SDCLK1/ MCLK1/ P00 Pos/ Pos/ B SD card I/F Ch1 clock output/ PCM Ch1 master clock/ General purpose port SDCMD1/ LRCK1/ P02 B SD card I/F Ch1 command line/ PCM Ch1 LR clock/ General purpose port SDAT13/ SDO1/ P06 B SD card I/F Ch1 data 3/ Serial I/F Ch1 data output/ General purpose port SDAT12/ DOUT1/ P05 B SD card I/F Ch1 data 2/ PCM Ch1 data output/ General purpose port SDAT11/ DIN1/ P04 B SD card I/F Ch1 data 1/ PCM Ch1 data input/ General purpose port SDAT10/ BCK1/ P03 B SD card I/F Ch1 data 0/ PCM Ch1 bit clock/ General purpose port SDWP1/ SDI1/ P01 B SD card I/F Ch1 write protect/ Serial I/F Ch1 data input/ General purpose port (It is possible to use it as an external interrupt input). SDCD1/ SCK1/ P0A B SD card I/F Ch1 card detect/ Serial I/F Ch1 clock/ General purpose port (It is possible to use it as an external interrupt input). Total 8
No.A2171-15/20 Oscillation amplifier and PLL Pin name Pol. Type Description Num. XIN2 Pos I Oscillation amplifier input for audio (XT2) 1 XOUT2 - O Oscillation amplifier output for audio (XT2) 1 VCNT1 - O VCO control for PLL1 1 AVDDPLL1 - P Analog power supply for PLL1 1 AVSSPLL1 - P Analog ground for PLL1 1 VCNT2 - O VCO control for PLL2 1 AVDDPLL2 - P Analog power supply for PLL2 1 AVSSPLL2 - P Analog ground for PLL2 1 Total 8 10bitA/D Pin name Pol. Type Description Num. AN[2:0] - I ADC input 3 AVDDADC - P Power supply for ADC 1 VSS (AVSSADC) P Ground for ADC. It connects VSS in LSI (terminal sharing). There is an optional bonding as dedicated ground AVSSADC . Total 5 Audio CODEC Pin name Pol. Type Description Num. AINL - I Analog voice input Lch (stereo) Analog voice input (monaural). 1 AINR - I Analog voice input Rch (stereo) 1 AVREF - O Audio ADC reference output 1 AVDDAADC - P Power supply for audio ADC 1 AVSSAADC - P Ground for audio ADC 1 OUTML/ OUTM O Audio DAC PWM output (Lch for HP)/ Audio DAC PWM output (monaural for speaker) 1 OUTMR - O Audio DAC PWM output (Rch for HP) 1 AVDDADAC - P Power supply for audio DAC 1 AVSSADAC - P Ground for audio DAC 1 HPINL/ SPKINM - I/ I Headphone amplifier input (Lch) / Speaker amplifier input (monaural) 1 HPINR - I Headphone amplifier input (Rch) 1 SPOUTP - O AB class speaker amplifier output (+) 1 SPOUTN - O AB class speaker amplifier output (-) 1 HPOUTL - O Headphone amplifier output (Lch) 1 HPOUTR - O Headphone amplifier output (Rch) 1 AVREFSP - O AB class amplifier reference output 1 AVDDSPAMP - P Analog power supply for AB class amplifier 1 AVSSSPAMP - P Analog ground for AB class amplifier 1 Total 18
No.A2171-16/20 LCD Driver (4COM/8COM bonding switch) Pin name Pol. Type Description Num. SEG[17:0] - O Segment output for LCD 18 COM[7:4] (SEG[21:18]) O O COM [7:4], Common driver output for LCD (when 8COM is used). There is an optional bonding as segment outputs, SEG[21:18], for the LCD(when 4COM is used). COM[3:0] - O Common driver output for LCD.
- Both 8COM and 4COM ··· COM[3:0]. 4 VLCD1 - O LCD drive voltage output 1
- When 1/3bias is used ··· 2 * VDDLCD /3.
- When 1/4bias is used ··· 3 * VDDLCD /4. VLCD2 - O LCD drive voltage output 2
- When 1/3bias is used ··· 1 * VDDLCD /3.
- When 1/4bias is used ··· 2 * VDDLCD /4. VLCD3 - O LCD drive voltage output 3
- When 1/3bias is used ··· 1 * VDDLCD /3.
- When 1/4bias is used ··· 1 * VDDLCD /4. VDDLCD - P 3V power supply for LCD driver 1 Total 30
No.A2171-17/20 USB 2.0 HS Device/LCD Driver (bonding switch when 4COM is used) Pin name Pol. Type Description Num. DP (SEG32) B O USB D+ (Device) There is an optional bonding as segment output 32 for LCD. DM (SEG33) B O USB D- (Device) There is an optional bonding as segment output 33 for LCD. RREF (SEG24) B O Reference resistance for USB PHY. There is an optional bonding as segment output 24 for LCD. AVDDPHY1 - P Analog 1.5V power supply for USB PHY. It connects VDD1 in LSI (terminal sharing). 1 AVSSPHY1 (SEG22) P O Analog ground for USB PHY. There is an optional bonding as segment output 22 for LCD. AVSSPHY1 (SEG23) P O Analog ground for USB PHY. There is an optional bonding as segment output 23 for LCD. AVDDPHY2 (SEG26) P O Analog 3.3V power supply for USB PHY. There is an optional bonding as segment output 26 for LCD. AVDDPHY2 (SEG27) P O Analog 3.3V power supply for USB PHY. There is an optional bonding as segment output 27 for LCD. AVDDPHY2 (SEG31) P O Analog 3.3V power supply for USB PHY. There is an optional bonding as segment output 31 for LCD. AVDDPHY2 (SEG35) P O Analog 3.3V power supply for USB PHY. There is an optional bonding as segment output 35 for LCD. AVSSPHY2 (SEG25) P O Analog ground for USB PHY. There is an optional bonding as segment output 25 for LCD. AVSSPHY2 (SEG28) P O Analog ground for USB PHY. There is an optional bonding as segment output 28 for LCD. AVSSPHY2 (SEG29) P O Analog ground for USB PHY. There is an optional bonding as segment output 29 for LCD. AVSSPHY2 (SEG30) P O Analog ground for USB PHY. There is an optional bonding as segment output 30 for LCD. AVSSPHY2 (SEG34) P O Analog ground for USB PHY. There is an optional bonding as segment output 34 for LCD. Total 15
No.A2171-18/20 Power supply etc. Pin name Pol. Type Description Num. BMODE[2:0] - I Operation mode selection 3 NRES Neg I External reset and GPIO•LCD driver output force input
- When it is active (L input), the state of the GPIO•LCD driver is forced, and LED lighting and the LCD display is controlled until reset depends on LSI. When Low is input : GPIO = Hiz, LCD = Low Fixed (PIOFIXB).
- The state of JTDI and JTMS of JTAG is taken into the internal register by rising edge of NRES (for operation mode setting). VDD1 - P Digital internal power supply There is one VDD1 which is also connected with AVDDPHY1. 3 VDD2 - P Digital IO power supply 3 VSS - P Digital ground There is one VSS which is also connected with AVSSADC. 4 Total 14 Total 128 Notes: Do not open an unused digital input terminal or a digital bidirectional terminal of input state, and set Pull-up/Pull-down register in ON (only terminals with this function) or connect to digital IO power supply or digital ground. Left open AINL, AINR, HPINL/SPKINM, and HPINR terminals if they are not used (do not fix to L or H). Operational mode Various boot modes etc. can be selected by switching BMODE[2:0] terminal. BMODE2 BMODE1 BMODE0 Operational mode 0 0 0 Internal ROM boot (eMMC Physical Boot - SD interface Ch0) 0 0 1 Internal ROM boot (IPL Boot - SD interface Ch0) 0 1 0 Internal ROM boot (Partition Boot - SD interface Ch0) 0 1 1 Internal ROM boot (External Serial Flash Boot - SIO (synchronous serial) interface Ch0) 1 0 0 Liberation of the terminal for SD interface Ch0 and SIO Ch0 (SDCLK0, SDCMD0, SDAT03, SDAT02, SDAT01, SDAT00, SCK0, SDO0, SDI0, and DOUT0 (NCS) are output Hiz). 1 0 1 Internal ROM boot (Deletion Partition area and IPL user area – SD interface Ch0 and SIO external Serial Flash Ch0) 1 1 0 LSI test mode (Do not set to this mode when working actually). 1 1 1 LSI test mode (Do not set to this mode when working actually).
No.A2171-19/20 Pin Type 3ICUD/ 3T2 EN3 = 0: PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal 3ISUD/ 3T2 3ISUD/ 3T4 EN3 = 0: PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal 3ICUD/ 3T4(8) 3ICUD/ 3T6(12) CTI current ability switch terminal 0: 4mA 1: 8mA/ 0: 6mA 1: 12mA EN3 = 0:PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal 3ISUD/ 3T4(8) 3ISUD/ 3T6(12) CTI current ability switch terminal 0: 4mA 1: 8mA/ 0: 6mA 1: 12mA EN3 = 0: PAD is configured as input & Pull_up OFF, Pull_down OFF, EN3 = 1 normal Continued on next page. PAD EN A Y CTU CTD EN3 PAD EN A Y CTU CTD EN3 PAD EN A Y CTU CTD CTI EN3 PAD EN A Y CTU CTD CTI EN3
PS No.A2171-20/20 Continued from preceding page. 1IC 1IS 3IS OD3 Device Package Shipping (Qty / Packing) LC823430TA-2H TQFP128L(14X14) (Pb-Free / Halogen Free) 3 / Tray JEDEC ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use a s components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and dis tributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture oft h e part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PAD Y PAD Y PAD EN