DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 24
Technical content
1 Publication Order Number :
www.onsemi.com © Semiconductor Components Industries, LLC, 2015 January 2015 - Rev. 1
ORDERING INFORMATION
See detailed ordering and shipping information on page 24 of this data sheet. LC78615E Overview The LC78615E integrates RF signal processor for CD-DA/R/RW, servo control, EFM signal processing and playback controller (Sequencer : 8-bit CPU). It is possible to make CD player system using with micro controller and driver IC’s with less components. Function RF signal processing for CD-DA/R/RW, servo control and EFM signal processing. Outputs CDDA, CDROM data Outputs CD-TEXT decoded data using the serial interface or Serial communication line with external main controller. CD playback system is realized with simple macro commands by the external controller because of the internal Sequencer (8-bit CPU). Operating Voltage : 3.3V Typical Operating Temperature : 40C to +85C Package : QIP64E(1414) CMOS LSI Compact Disc Player IC PQFP64 14x14 / QIP64E
www.onsemi.com Detail of Functions [CD-DSP functions] < Playback functions> Playback mode : CLV playback / Jitter free playback (VCEC) Playback speed : Normal speed, double speed, quadruple speed (CLV playback / Jitter free playback) <RF processing block> RF system : AGC, CD-R and CD-R/W playback support, peak hold, bottom hold Error system : TE signal generation, FE signal generation Detection : Track count signal, Jitter, Defect (black, mirror) LASER power controller (APC) DC offset voltage cancellation <Servo control block> All servo systems as tracking, focus, sled and spindle are implemented with digital processing. Automatic adjustment functions : focus gain, focus bias, focus offset, tracking gain, tracking offset and tracking balance Shock detection / Interruption detection <CD signal processing block> EFM signal synchronization detection, protection and interpolation Error detection, correction (C1=double, C2=quadruple/double) Jitter margin ±19 frames <CD-TEXT processing block> Buffers CD-TEXT decoded data to the buffer memory. Starts buffering of CD-TEXT decoded data from desired ID3/ID4. [CD data processing functions] <CDDA data processing block> Interpolation Mute function(12dB, ∞) Digital attenuator De-emphasis filter <CDROM data processing block > CLV playback : Fixed normal speed or double speed Jitter free playback (VCEC) : Fr ee speed within quadruple speed <Outputs format > Digital 3 lines output (LRCK, BCK, DATA) Supports various external audio data output format IIS (48fs), MSB First, Right-Justified, Left-Justified (32fs/48fs), 16 bit data length Slave mode Output DATA synchronized to external Clock input (LRCK/BCK) Digital output (S/PDIF, only CLV playback mode) [Internal Microcontroller functions] <Sequencer control> CD playback control Servo control, CD-TEXT processing, Digital data output control, etc. <Communication control between main controller> The SIO interface using CE,CL,DI,DO and BUSYB pins is available as communication format. External main controller can control this IC directly such as “stop oscillation” or “restart oscillation” or so on at the internal register open mode (REG_READY high condition). Even while the clock is stopped, some of general port can be controlled by host controller. <Peripheral interface block> GPIO port 15 ports maximum(Shared with other functionslerate.) <Program memory block> Mask-ROM type ROM Collect function is built in for the partial change of the program and Host controller can use this. <Others> Watch Dog Timer Notifies to outside from a pin or resets internally. Power management (Two kinds of sleep mode) (1) Only the clock for CPU core is operating and clocks for other blocks are stopping. (2) All clocks are stopping. [Others] <Internal power supply> 1.5V regulator for internal blocks
www.onsemi.com Specifications Parameter Symbol Conditions Ratings unit Maximum supply voltage V DD max DVDD, AVDD, XVDD, VVDD1 0.3 to +3.95 V Input voltage 1 V IN1 0.3 to DVDD+0.3 V Output voltage V OUT 0.3 to DVDD +0.3 V Allowable power dissipation Pd max Ta ≤ 85°C Mounted reference PCB (*) 300 mW Operating temperature Topr 40 to +85 °C Storage temperature Tstg 40 to +125 °C (*) Reference PCB : 114.3mm×76.1mm×1.6mm, glass epoxy resin Recommended Operating Conditions at Ta=40 to 85°C, DVSS=A VSS=XVSS=VVSS1=0V Parameter Symbol Pin Name Type Conditions Ratings unit min typ max Supply voltage V DD DVDD, AVDD, XVDD, VVDD1 3.00 3.60 V High-level input voltage VIH XIN, RESB, MODE,CE, CL, DI, DO CONT00, CONT01, CONT02, CONT03, CONT04, CONT05, CONT06, CONT07, CONT08, CONT09, CONT10, CONT11, CONT12, CONT13, CONT14, Schmitt
2.00 VDD V
XIN, RESB, TEST,CE, CL, DI, DO CONT00, CONT01, CONT02, CONT03, CONT04, CONT05, CONT06, CONT07, CONT08, CONT09, CONT10, CONT11, CONT12, CONT13, CONT14, Schmitt 0.00 0.80 V Crystal Oscillator Frequency FX XIN, XOUT Oscillator circuit
16.9344 MHz
16.9344 18.0 MHz Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recomme nded Operating Ranges limits mayaffect device reliability.
www.onsemi.com Parameter Symbol Pin Name Type Conditions Ratings unit min typ max Current drain I DD1 DVDD, AVDD, XVDD, VVDD1 40 60 mA High-level input current IIH RESB, MODE,CE, CL, DI, DO CONT00, CONT01, CONT02, CONT03, CONT04, CONT05, CONT06, CONT07, CONT08, CONT09, CONT10, CONT11, CONT12, CONT13, CONT14, Schmitt VIN=VDD Built-in Pull-down /Pull-up resistor OFF 10.00 μA Low-level input current IIL RESB, TEST,CE, CL, DI, DO CONT00, CONT01, CONT02, CONT03, CONT04, CONT05, CONT06, CONT07, CONT08, CONT09, CONT10, CONT11, CONT12, CONT13, CONT14 Schmitt VIN=0.0V Built-in Pull-down /Pull-up resistor OFF 10.00 High-level output voltage VOH(1) DO, BUSYB, CONT00,CONT01, CONT02, CONT03,CONT04, CONT05, CONT06,CONT07, CONT09,CONT10, CONT11, CONT12,CONT13, CONT14 CMOS I OH=2mA VDD0.6 V VOH(2) CONT08 CMOS IOH=4mA Low-level output voltage VOL(1) DO, BUSYB, CONT00,CONT01, CONT02, CONT03,CONT04, CONT05, CONT06,CONT07, CONT09,CONT10, CONT11, CONT12,CONT13, CONT14 CMOS I OL=2mA 0.40 VOL(2) CONT08 CMOS I OL=4mA Output off-leakage current IOFF(1) PDOUT0,PDOUT1 Hi-Z Out 10.00 10.00 μA IOFF(2) DO Hi-Z Out 10.00 10.00 Built-in Pull-down resistor RPD CONT01,CONT02, CONT03, CONT04,CONT05, CONT06, CONT07,CONT08, CONT09, CONT10,CONT11, CONT12, CONT13,CONT14 50 100 200 k Ω Built-in Pull-up resistor RPU CONT00 50 100 200 k Ω Charge pump output current IPDOH PDOUT1,PDOUT0 PCKIST=100kΩ Current value setting:1x 35 50 65 μA IPDOL PDOUT1,PDOUT0 65 50 35 (Notes) Connect and use the pull-up or the pull-down resister with the outside when you use serial communications because the terminal DO is 3- State output (initial state). Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per formance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com Package Dimensions unit : mm PQFP64 14x14 / QIP64E CASE 122BP ISSUE A XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data GENERIC MARKING DIAGRAM* *This information is generic. Please refer to device data sheet for actual part marking. may or may not be present. XXXXXXXX YMDDD 14.0±0.1 0.8 (1.0) 0.15 14.0±0.1 17.2±0.2 17.2±0.2 0.35 0.10
3.0 MAX
(2.7)0.1±0.1 0 to 10° 0.15 0.8±0.2 (Unit: mm) 16.30 16.30 0.500.80 1.30 SOLDERING FOOTPRINT* NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com Pin Assignment SLCO XVDD XIN XOUT XVSS DVDD DVDD15 MODE CONT14 CONT13 CONT12 CONT11 CONT10 CONT09 CONT08 BUSYB LC78615 6DXX RESB DO DI CL CE CONT07 CONT06 CONT05 CONT04 CONT03 CONT02 CONT01 CONT00 TEST DVSS DVDD EFMIN RFOUT LPF PHLPF AIN CIN BIN DIN SLCISET RFMON VREF JITTC EIN FIN TE TEIN
www.onsemi.com Pin Description Pin No. Pin name I/O State when “Reset” Function
1 EFMIN AI Input RF signal input
2 RFOUT AO Undefined RF signal output
3 LPF AO Undefined RF signal DC level detec tion low-pass filter capacitor connection
4 PHLPF AO Undefined Defect detecti on low-pass filter capacitor connection
5 AIN AI Input A signal input
6 CIN AI Input C signal input
7 BIN AI Input B signal input
8 DIN AI Input D signal input
9 SLCISET AI Input SLCO output current setting resistor connection
10 RFMON AO Undefined IC in ternal analog signal monitor
11 VREF AO AVDD/2 Reference voltage output for RF
12 JITTC AO Undefined Jitter detection capacitor connection
13 EIN AI Input E signal input
14 FIN AI Input F signal input
15 TE AO Undefined TE signal output
16 TEIN AI Input TE signal input used for TES signal generation
17 AVSS Analog system ground. This pin must be connected to the 0V level.
18 AVDD Analog system power supply
19 LDD AO Undefined Laser power control signal output
20 LDS AI Input Laser power detection signal input
21 FDO AO AVDD/2 Focus control signal output
22 TDO AO AVDD/2 Tracking control signal output
23 SLDO AO AVDD/2 Sled control signal output
24 SPDO AO AVDD/2 Spindle control signal output
25 VVSS1 EFMPLL ground. This pin must be connected to the 0V level.
26 PDOUT1 AO Undefined EFMPLL charge pump output 1
27 PDOUT0 AO Undefined EFMPLL charge pump output 0
28 PCKIST AI Input EFMPLL charge pump current setting resistor connection pin
29 VVDD1 EFMPLL power supply
30 NC NC Pin (Open)
31 NC NC Pin (Open)
32 DVDD15 AO High Capacitor connect ion pin for internal regulator
33 DVDD Digital system power supply
34 DVSS Digital system ground. This pin must be connected to the 0V level. 35 TEST I Input Test input. This pin must be connected to the 0V level.
36 CONT00 I/O Input(High) General purpose I/O port with pull up resistor
SBCK clock input for CD subcode data (exclusive with CONT07 and CONT11)
37 CONT01 I/O Input(Low) General purpose I/O port with pull down resistor
Block synchronization signal (SBSY) output for CD subcode
38 CONT02 I/O Input(Low) General purpose I/O port with pull down resistor
Frame synchronization signal (SFSY) output for CD subcode
39 CONT03 I/O Input(Low)
General purpose I/O port with pull down resistor PW data output in CD subcode Watch Dog Timer state monitor output
40 CONT04 I/O Input(Low)
General purpose I/O port with pull down resistor LR clock output for CD data LR clock input for CD data (exclusive with CONT09 and CONT12) Block synchronization signal (SBSY) output for CD subcode Data request signal input for CD-TEXT interface (exclusive with CONT08, CONT09 and CONT12)
www.onsemi.com Pin No. Pin name I/O State when “Reset” Function
41 CONT05 I/O Input(Low)
General purpose I/O port with pull down resistor Bit clock output for CD data Bit clock input for CD data (exclusive with CONT10 and CONT13) Frame synchronization signal (SFSY) output for CD subcode Clock input/output for CD-TEXT interface (exclusive with CONT10 and CONT13)
42 CONT06 I/O Input(Low)
General purpose I/O port with pull down resistor Serial data output for CD data PW data output in CD subcode Serial data output for CD-TEXT interface
43 CONT07 I/O Input(Low)
General purpose I/O port with pull down resistor C2 error flag output for CD data Digital audio output<S/PDIF> SBCK clock input for CD subcode data (exclusive with CONT00 and CONT11) Watch Dog Timer state monitor output
44 CE I Input Host I/F
Enable signal input for serial communication
45 CL I Input Host I/F
Data transfer clock input for serial communication
46 DI I Input Host I/F
Data input for serial communication
47 DO O Low Host I/F
Data output for serial communication 48 RESB I Input IC reset input.(Low active) This pin must be set low once after power is first applied.
49 BUSYB O Low Host I/F
BUSYB output(High : Communication available)
50 CONT08 I/O Input(Low)
General purpose I/O port with pull down resistor LR clock output for CD data Digital audio output<S/PDIF> FS384 clock input/output for Audio DAC Data request signal input for CD-TEXT interface (exclusive with CONT04, CONT09 and CONT12)
51 CONT09 I/O Input(Low)
General purpose I/O port with pull down resistor LR clock output for CD data LR clock input for CD data (exclusive with CONT04 and CONT12) Frame synchronization signal (SFSY) output for CD subcode Data request signal input for CD-TEXT interface (exclusive with CONT04, CONT08 and CONT12)
52 CONT10 I/O Input(Low)
General purpose I/O port with pull down resistor Bit clock output for CD data Bit clock input for CD data(exclusive with CONT05 and CONT13) PW data output in CD subcode Clock input/output for CD-TEXT interface (exclusive with CONT05 and CONT13)
53 CONT11 I/O Input(Low)
General purpose I/O port with pull down resistor Serial data output for CD data Digital audio output<S/PDIF> SBCK clock input for CD subcode data (exclusive with CONT00 and CONT07) Serial data output for CD-TEXT interface
www.onsemi.com Pin No. Pin name I/O State when “Reset” Function
54 CONT12 I/O Input(Low)
General purpose I/O port with pull down resistor LR clock input for CD data (exclusive with CONT04 and CONT09) C2 error flag output for CD data Block synchronization signal (SBSY) output for CD subcode Data request signal input for CD-TEXT interface (exclusive with CONT04, CONT08 and CONT09)
55 CONT13 I/O Input(Low)
General purpose I/O port with pull down resistor Bit clock output for CD data Bit clock input for CD data(exclusive with CONT05 and CONT10) Frame synchronization signal (SFSY) output for CD subcode Clock input/output for CD-TEXT interface (exclusive with CONT05 and CONT10)
56 CONT14 I/O Input(Low)
General purpose I/O port with pull down resistor Serial data output for CD data PW data output in CD subcode Serial data output for CD-TEXT interface Watch Dog Timer state monitor output 57 MODE I Input LSI mode set input. This pin must be connected to the DV DD level.
58 DVDD15 AO High Capacitor connect ion pin for internal regulator
59 DVDD Digital system power supply
60 XVSS Oscillator ground. This pin must be connected to the 0V level. 61 XOUT O Oscillation 16. 9344MHz oscillator connection 62 XIN I Oscillation 16.9344MHz oscillator connection
63 XVDD Oscillator power supply
64 SLCO AO Undefined Slice Level Control output
<Notes> (1) For Unused pins : The unused input pins must be connected to the GND(0V) level if there is no individual note in the above table. The unused output pins must be left open(No connection) if there is no individual note in the above table. The unused input/output pins must be connected to the GND(0V) or power supply pin for I/O block with internal pull down/up resistor OFF or be left open with internal pull down/up resistor ON when input pin mode or must be left open(No connection ) when output pin mode if there is no individual note in the above table. When you connect an I/O pin which is an input pin without internal pull-down/up resistor at reset mode to the GND or power supply level, we recommend you to use pull-down resistor or pull-up resistor individually as fail-safe. (2) For Power supply pins : Same voltage level must be supplied to DVDD, A VDD, XVDD and VVDD1 power supply pins. (3) For “Reset” condition : This IC is not reset only by making the RESB pin “Low”. Refer to “4. Power on and Reset control” for detail of “Reset” condition.
www.onsemi.com Block Diagram CD RF Signal Processor AD/DA CD Servo Controller CD PLL CD EFM/ECC Decoder CD-TEXT Decoder DATA Trans 8bit-CPU Core BUFRAM I/F PORT Control WatchDog Timer Program ROM Work RAM Host-I/F (SIO) Interrupt Regulator 1.5V 3.3V Data Output Control CDROM Data CDDA Data DeEMPHASIS/ MUTE/ATT DOUT(S/PDIF) X'tal (16.9344MHz) Buffer RAM
www.onsemi.com Power on and Reset control Attention when power on The RESB pin must be set to “Low” level when power is fi rst supplied. At that time, it is necessary to input a stable clock to the XIN pin. You may input the voltage of VDD or less to each input terminal when the power supply is off. Parameter Symbol Min Typ Max unit Reset time(Power on) tRESW1 20 ms Reset time(Normal) (*1) tRESW2 1 ms *1 : The oscillation must be stable during tRESW2. When the XIN clock has been stopped by the command etc. , the specification of tRESW2 could be larger than the value shown above, because it takes time that the XIN oscillator becomes stable. 3.3V Power supply RESB Power ON stage During normal operation (Oscillation clock is valid) tRESW1 tRESW2
www.onsemi.com Host interface The four wires serial interface is available as the data transmission protocol between this LSI and Host controller. It is able to know whether the internal sequencer could receive the command or not by the BUSYB pin. BUSYB Command Acceptance situation Low All address command access disable High All address command access disable except A0h to A7h addresses BUSYB becomes Low if the A5h address command is transmitted. All address command except A0h to A7h addresses will be ignored. By setting REG_READY command to High, internal register open mode is available. In this mode, Host controller can access to the all address command (internal sequencer can’t control the CDDSP block). When the A5h address command is transmitted, REG_READY command and BUSYB pin is set to Low, and internal register open mode become finish. Command Transfer Timing 1 : (Normal mode: BUSYB = "H" → "L") Command Transfer Timing 2 : (Internal register open mode: BUSYB = "H") CE CL DI BUSYB Twh Trdyoff Tcsu Twl Twsu Twhd Tchd Trdyon Trsu CE CL DI BUSYB Twh Tcsu Twl Twsu Twhd Tchd Tce Trsu
www.onsemi.com Command Receive Timing 1 : (Normal mode : BUSYB = "H" ) *1. High level must be supplied to the DI pin during Read Access Cycle. Command Receive Timing 2 : (Internal register open mode: BUSYB = "H") *1. High level must be supplied to the DI pin during Read Access Cycle. Parameter Symbol Pin Names Min Typ Max unit Setup time for READY Trsu CE, BUSYB 60 ns Setup time for CE Tcsu CE, CL 400 Hold time for CE Tchd CE, CL 200 Setup time for DI Twsu DI, CL 100 Hold time for DI Twhd DI, CL 100 High level clock pulse width Twh CL 200 Low level clock pulse width Twl CL 200 Access time for read data Trac CL, DO 0 100 Hold time for read data Trhd CL, DO 120 Turn On Time for DO Ton CE, DO 150 Turn Off Time for DO Toff CE, DO 0 300 Command transfer time Tce CE 1 μs Turn Off Time for READY Trdyoff CE, BUSYB 0 200 ns Turn On Time for READY(*1) Trdyon CE, BUSYB 0.175 50000 μs *1. Never communicate in this period. CE CL DI DO BUSYB TcsuTce Twh Twl Tchd Toff Trac TrhdTon Read Setting Cycle (Write Timing) Read Access Cycle (*1) CE CL DI DO BUSYB TcsuTce Twh Twl Tchd Toff Trac TrhdTon Read Setting Cycle (Write Timing) Read Access Cycle (*1)
www.onsemi.com CD data output function Two modes can be available for CD data output. (1) Normal mode In this mode, output signals are LRCK, BCK and DATA. CLV or Jitter-Free(VCEC) playback is supported. When CDDA playback, depending on the specification of Audio DAC, FS384 clock output is also available . (2) Slave mode In ths mode, output signal is DATA, and input signals are LRCK, BCK. The DATA output is synchronized to input clocks (LRCK,BCK). It is enable to output CD data synchronized to Audio DAC without connecting FS384clock. This mode is only available for CD normal playback, and LRCK frequency must be 44.1kHz. 1. Normal mode Available format Mode : IIS, MSB First Right-Justif ied, MSB First Left-Justified Slot Length : 32fs, 48fs Data Length : 16-bit Used Pin LRCKO : CONT04, CONT08, CONT09 BCKO : CONT05, CONT10, CONT13 DATAO : CONT06, CONT11, CONT14 Note When CDDA Playback, FS384 can be optionally output from CONT08. The signal input from XIN pin is output as FS384 signal. CD Data output timing Parameter Symbol Pin Names Min Typ Max unit Bit clock Frequency fABCKO BCKO 10.5 MHz Bit clock "H" level width tABKOH BCKO 47.5 ns Bit clock "L" level width tABKOL BCKO 47.5 ns Setup time for LRCK (based on BCK negedge) tBLP BCKO,LRCKO 0 15 ns Hold time for LRCK (based on BCK negedge) tBLA BCKO,LRCKO 0 15 ns Setup time for DATA output tBDS BCKO,DATAO 30 ns Hold time for DATA output tBDH BCKO,DATAO 30 ns * In case of quadruple speed playback, and setting the output format as 48fs slot length. LRCKO BCKO DATAO tABK tABK tBLP tBDS 1/fABCKtBLA tBDH
www.onsemi.com 2. Slave mode In this mode, LRCK (Fs=44.1kHz) and BCK are input from external device, and output data is synchronized with input clocks. So, it is possible to play CDDA without FS384 or SRC (Sampling Rate Converter). Available format Mode : IIS, MSB First Right-Justif ied, MSB First Left-Justified Slot Length : 32fs, 48fs, 64fs Data Length : 16-bit Used Pin LRCKI : CONT04, CONT09, CONT12 BCKI : CONT05, CONT10, CONT13 DATAO : CONT06, CONT11, CONT14 Slave mode data timing Parameter Symbol Pin Names Min Typ Max unit LRCK frequency fLRCKI LRCKI 44.1 48.5 kHz LRCK "H" level width tLRIH LRCKI 10.3 11.34 s LRCK "L" level width tLRIL LRCKI 10.3 11.34 s Bit clock frequency fABCKI BCKI 2.1168
3.10 MHz
Bit clock "H" level width tABKIH BCKI 160 236.2 ns Bit clock "L" level width tABKIL BCKI 160 236.2 ns Setup time for LRCK input tBRIS LRCKI,BCKI 50 ns Hold time for LRCK input tBLIH LRCKI,BCKI 50 ns Setup time for DATA output tDOS DATAO,BCKI 50 ns Hold time for DATA output tDOH DATAO,BCKI 50 ns *1: In case of setting the output format as 48fs slot length. tDOS tDOH LRCKI (In) BCKI (In) DATAO (Out) tLRIH tLRIL tABKI tABKI 1/fABCK 1/fLRCKI tBLIH tBLIS
www.onsemi.com CD Subcode Data Output function It is possible to output the subcode data (PW data) according to the terminal setting when CD playback mode. The PW data are output at the rising edge of SBCK signal when the SBCK clock signal is input. <Note> The CD-TEXT function and the CD Subcode data output function are exclusive functions. It is impossible to use those two functions simultaneously. Used pins SBSY (Subcode Block Synchronous signal) : CONT01, CONT04, CONT12 SFSY (Subcode Frame Synchronous signal) : CONT02, CONT05, CONT09, CONT13 PW (Subcode PW data) : CONT03, CONT06, CONT10, CONT14 SBCK (Subcode data read clock) : CONT00, CONT07, CONT11 Subcode Data Output timing Subcode Block Synchronous Signal Output timing Parameter Symbol Pin Names Min Typ Max unit Subcode Read Cycle time tSBFC SFSY 136 Subcode Read Enable time tSBE SFSY , SBCK 400 ns SBCK clock "H" level width tSBCKH SBCK 250 ns SBCK clock "L" level width tSBCKL SBCK 250 ns PW data output Delay time tSBRDL SBCK, PW 0 100 ns SBSY output Cycle time tSBBC SBSY 13.3 *2 ms SBSY "H" level width tSBBH SBSY 272 *2 s <Notes> 1. When playback the CD at the normal speed (CLV playback). This value changes depending on the playback speed. 2. When playback the CD at the normal speed (CLV playback). The SBSY signal becomes high level during the first two subcoding symbols (S0 and S1) are asserted. SFSY (Output) SBCK (Input) PW (Output) tSBE P Q R S TU VW "0" P tSBF tSBCK tSBCKL tSBRDL SBSY (Output) tSBBC tSBBH
www.onsemi.com CD-TEXT data output function There are two methods to output CD-TEXT data from the Buffer RAM in this IC. (1) Command Communication output mode Outputs the CD-TEXT data using the command communication protocol between this IC and external host controller. (2) Hand shake output mode using with hardware interface function A. Inputs data request signal and transfer clock then outputs CD-TEXT data The CD-TEXT data(CTDATO) will be output synchronizing with the CTCKI clock when the CTCKI clock is input after the CD-TEXT data request signal is input(CTREQI="H"). B. Inputs data request signal then outputs transfer clock and CD-TEXT data The CTCKO and CTDATO synchronized with CTCKO will be output after the CD-TEXT data request signal is input (CTREQI= "H"). In both operation modes (1) and (2), the data transfer unit bit length is 2 Bytes (16 bits). * The CD-TEXT function and CD subcode data output function are exclusive each other, and then those functions can not be used simultaneously. CD-TEXT data output Timing 1 : CTCK input mode <Supplement> Both modes below are available. A. CTCKI="L" start mode The CTDATO is output synchronized w ith the rising edge of the CTCKI clock. The host controller should latch the CTDATO data at the falling edge of the CTCKI clock. B. CTCKI="H" start mode The CTDATO is output synchronized with the falling edge of the CTCKI clock. The host controller should latch the CTDATO data at the rising edge of the CTCKI clock. * The relationship between the signals in figure 8-1 and the pins is shown below. CTREQI : CONT04, CONT08, CONT09, CONT12 CTCKI : CONT05, CONT10, CONT13 CTDATO : CONT06, CONT11, CONT14 Parameter Symbol Pin Names Min Typ Max unit CTCKI clock Frequency fSCI CTCKI 1.25 MHz CTCKI clock input start time tCTCKIN CTREQI, CTCKI 1000 ns CTCKI clock "H" level width tCTCKH CTCKI 400 ns CTCKI clock "L" level width tCTCKL CTCKI 400 ns CTDATO output Delay time tCTDODL1 CTCKI, CTDATO 250 ns Note : The above figure shows the case of mode A that the clock starts low level (CTCKI="L"). The timings are same when the clock starts high level (CTCKI="H"). CTREQI (Input) CTCKI (Input) CTDATO (Output) tCTDO tCTCK tCTC KL 1/fSCI tCTC
www.onsemi.com CD-TEXT data output Timing 2 : CTCK output mode <Supplement> The CTCKO will be output starting with the high level then the CTDATO will be output synchronized with the falling edge of the CTCKO clock. The host controller should latch the CTDATO data at the rising edge of the CTCKO clock. * The relationship between the signals in figure 8-2 and the pins is shown below. CTREQI : CONT04, CONT08, CONT09, CONT12 CTCKO : CONT05, CONT10, CONT13 CTDATO : CONT06, CONT11, CONT14 Parameter Symbol Pin Names Min Typ Max unit CTCKO clock Frequency fSCO CTCKO 1.05 4.2 MHz CD-TEXT data output start time tCTOAT CTREQI, CTCKO (1/fSCO) ×32 ns CD-TEXT data output stop time tCTOFF CTREQI, CTCKO (1/fSCO) ×32 ns CTCKO clock "H" level width tCTCOH CTCKO 400 100 ns CTCKO clock "L" level width tCTCOL CTCKO 400 100 ns CTDATO output Delay time tCTDODL2 CTDATO, CTCKO 0 50 ns tCTDO CTREQI (Input) CTCKO (Output) CTDATO (Output) tCTCO 1/fSC tCTOA tCTOF tCTCO
www.onsemi.com Internal Voltage Regulator at Ta=40°C to 85°C, DVSS=A VSS=XVSS=VVSS1=0V Parameter Symbol Condition Min Typ Max unit Load current Iope VDD=3.3V 50 mA Example circuit for Regulator A/D, D/A converter Characteristics for servo at Ta=40°C to 85°C, VDD=3.3V, DVSS=A VSS=XVSS=VVSS1=0V Parameter Symbol Min Typ Max unit Resolution Res 8 bit Maximum input/output range Vaio1 4/5VDD V Minimum input/output range Vaio2 1/5VDD V Oscillator Example circuit for Oscillator XIN/XOUT : 16.9344MHz For System clock of internal micro controller, CD control and Audio control Recommended Oscillators Murata Manufacturing Co., Ltd. SMD : CSTCE16M9V53-R0 <Built-in C> : CSTCW16M9X51008-R0 <Built-in C> Lead : CSTLS16M9X53-B0 <Built-in C> <Notes> Because the characteristics of oscillator could be changed according to the circuit board, ask evaluation with the individual original circuit board to the oscillator maker. Concerning about internal circuit for XIN/XOUT, refer to the "Analog Pin Internal Equivalent Circuits" section. The XIN pin can also be supplied from an external clock instead of connecting the oscillator. In this case, XOUT pin must be left open. XVDD XIN XOUT XVSS LC78615 C1 C1 Rd1 DVDD DVSS DVDD15 LC78615 100F * Same circuit need to be mounted both for two regulato r pins. (No.32 and No.58) * C1 is the capacitor to avoid oscillation. This capacitor value must be low ESR and greater than 30F in the range of the operating temperature. Because there is a possibility of the oscillation when the capacity value changes by the temperature change etc. (The recommended value is 100F. )
www.onsemi.com Analog Pin Internal Equivalent Circuits Pin Name (Pin No.) Equivalent Circuit EFMIN (1) AVDD AVSS RFOUT (2) AVDD AVSS AVDD AVSS LPF (3) AVDD AVSS AVDD AVSS PHLPF (4) AVDD AVSS AIN (5) CIN (6) BIN (7) DIN (8) SLCISET (9) AVDD AVSS RFMON (10) AVDD AVSS AVDD AVSS
www.onsemi.com Pin Name (Pin No.) Equivalent Circuit VREF (11) AVDD AVSS AVDD AVSS JITTC (12) AVDD AVSS EIN (13) FIN (14) TE (15) AVDD AVSS AVDD AVSS TEIN (16) AVDD AVSS LDD (19) AVDD AVSS AVDD AVSS AVDD LDS (20) AVDD AVSS
www.onsemi.com Pin Name (Pin No.) Equivalent Circuit FDO (21) TDO (22) SLDO (23) SPDO (24) AVDD AVSS AVDD AVSS PDOUT1 (26) VVDD1 VVSS1 VVDD1 VVSS1 PDOUT0 (27) VVDD1 VVSS1 VVDD1 VVSS1 PCKIST (28) VVDD1 VVSS1 VVSS1 XOUT (61) XIN (62) XVDD XVSS XVSS XVDD XIN XOUT SLCO (64) AVDD AVSS AVDD AVSS
www.onsemi.com Application Circuit Example * This sample circuit is only for CD servo block and each PLL block. The value of each component needs to be adjusted under the target conditions. The circuit for CD servo shown above could be changed depending on the CD mechanism used. * In this sample circuit, CONT00 - CONT14 are used as 3lines outputs (LRCK, BCK, DATA) and CD-Subcode-I/F (SBCK,SBSY ,SFSY ,PW). For CONT00 - CONT14, use the appropriate pin function according to specifications. 16.9344MHz A ( ) B ( ) C ( ) D ( ) Vref (Reference voltage) E ( ) F ( ) LD MD EFMIN RFOUT LPF PHLPF AIN CIN BIN DIN SLCISET RFMON VREF JITTC EIN FIN TE TEIN SLCO XVDD XIN XOUT XVSS DVDD DVDD15 MODE CONT14 CONT13 CONT12 CONT11 CONT10 CONT09 CONT08 BUSYB LC78615 6DXX VREF FDO TDO SLDO SPDO To μ-COM To PICKUP VDD GND RESB DO DI CL CE CONT07 CONT06 CONT05 CONT04 CONT03 CONT02 CONT01 CONT00 TEST DVSS DVDD AVSS AVDD LDD LDS FDO TDO SLDO SPDO VSS1 PDOUT1 PDOUT0 PCKIST VVDD1 NC NC DVDD15 To Driver Data Out (LRCK,BCK,DATA) CD SubCode-I/F
www.onsemi.com ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A lis ting of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended tosupport or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject t oa l l applicable copyright laws and is not for resale in any manner. Device Package Shipping (Qty / Packing) LC78615E-01US-H PQFP64 14x14 / QIP64E (Pb-Free / Halogen Free) 300 / Tray Foam