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Built-in buffer amplifiers minimize the number of external components required. Fabricated in a silicon gate CMOS process to minimize the switching noise generated by internal switches. Built-in reference voltage generation circuit for the analog ground level. All settings are controlled by data input over a serial interface that conforms to the CCB specifications. Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0V Parameter Symbol Conditions Ratings unit Maximum supply voltage VDD max V DD 11 V Input voltage V IN max CE, CL, DI –0.3 to +11.0 V LIN, RIN V SS –0.3 to VDD +0.3 Output voltage VOUT1 OSC –0.3 to V DD +0.3 V VOUT2 S1 to S87, COM1 to COM4, P1 to P8 –0.3 to V LCD +0.3 Allowable power dissipation Pd max Ta ≤ 75°C *1: When mounted on a PCB. 300 mW Operating temperature Topr –30 to +75 C Storage temperature Tstg –40 to +125 C CMOS LSI Two-Channel Electronic Volume Control System CCB is a registered trademark of Semiconductor Components Industries, LLC. CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. SOIC-10 NB
No.7332-2/13 Allowable Operating Ranges at Ta = 30 to +75C, VSS = 0V Parameter Symbol Pin Name Conditions Ratings Unit min typ max Supply voltage VDD V DD 4.5 10 V High-level input voltage V IH CL, DI, CE 2.0 10 V Low-level input voltage V IL CL, DI, CE 7.5 ≤ VDD ≤ 10 VSS 0.8 V CL, DI, CE 4.5 ≤ VDD ≤ 7.5 VSS 0.3 V Input voltage amplitude V IN LIN, RIN VSS V DD Vp-p Input pulse width tøW CL 1 s Setup time tsetup CL, DI, CE 1 s Hold time thold CL, DI, CE 1 s Operating frequency fopg CL 500 kHz Electrical Characterristics at Ta = 25C, VDD = 9V, VSS = 0V Parameter Symbol Pin Name Conditions Ratings Unit min typ max Input resistance Rin LIN, RIN 50 k Overall Characteristics Parameter Symbol Conditions Ratings Unit min typ max Total harmonic distortion THD VIN = 1 Vrms, f = 1 kHz With all settings flat overall 0.002 0.01 % VIN = 1 Vrms, f = 20 kHz With all settings flat overall 0.003 % Crosstalk CT V IN = 1 Vrms, f = 1 kHz, Rg = 1 k With all settings flat overall 90 dB Output noise voltage V N 80 kHz L.P.F, Rg = 1 k With all settings flat overall 6.0 V Maximum attenuation Vomin V IN = 1 Vrms, f = 1 kHz With all settings flat overall 92 dB Current drain I DD V DD – VSS = +9 V 12 mA High-level input current I IH CL, DI, CE: V IN = 10 V, VDD = 10 V 10 A Low-level input current I IL CL, DI, CE: V IN = 0 V, VDD = 10 V 10 A Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recomme nded Operating Ranges limits mayaffect device reliability. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per formance may not be indicated by the Electrical Characteristics if operated under different conditions.
No.7332-3/13 Package Dimensions unit : mm SOIC-10 NB CASE 751BQ ISSUE B SEATING PLANE 610 h X 45 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’ AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15mm PER SIDE. DIMENSIONS D AND E ARE DE- TERMINED AT DATUM F. 5. DIMENSIONS A AND B ARE TO BE DETERM- INED AT DATUM F. 6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. D EH A DIM D MIN MAX 4.80 5.00 MILLIMETERS E 3.80 4.00 A 1.25 1.75 b 0.31 0.51 e 1.00 BSC A1 0.10 0.25 A3 0.17 0.25 L 0.40 0.80 M 0 8 H 5.80 6.20 CM0.25 M XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb−Free Package GENERIC MARKING DIAGRAM* *This information is generic. Please refer to device data sheet for actual part DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* XXXXX ALYWX h 0.37 REF L2 0.25 BSC A TOP VIEW C0.20 2X 5 TIPS A-B D C0.10 A-B C0.10 A-B e C0.10 b10X B C C0.10 10X SIDE VIEW END VIEW DETAIL A 6.50 10X 1.18 10X 0.58 1.00 PITCH RECOMMENDED L F SEATING PLANE C L2 A3 DETAIL A D
No.7332-4/13 Pin Arrangement Equivalent Circuit 679 10 543 2 1 VSS ROUT Vref CE RIN LOUT VDD LIN DI CL LC75344MD Top view CCB INTERFACE LOGIC CIRCUIT RVref LVref CONTROL CIRCUIT CONTROL CIRCUIT PA LIN 1F LOUT 2.2F VDD DI CL 6 VSS Vref CE RIN 1F ROUT 2.2F 22F COM PA -+ + - -++ -
No.7332-5/13 Control System Timing and Data Format The LC75344MD is controlled by inputting the stipulated data serially to the CL, DI, and CE pins. The data consists of a total of 24 bits, of which 8 bits are the address and 16 bits are the data. Address Code (B0 to A3) The data has an 8-bit address field, and conforms to the CCB serial bus specifications. Address code (LSB) B0 B1 B2 B3 A0 A1 A2 A3 (88HEX) 0 0 0 1 0 0 0 1 D9 D10 D11 D12 D13 D14 D15 D0 D5D4D3D2D1A3 A2 A1A0 B3 B2 B1 B0 CL DI CE 1s min 1s ≤ TDEST DI CL CE 1s min 1s min 1s min 1s min
No.7332-6/13 Control Code Allocations V olume control D0 D1 D2 D3 D4 D5 D6 D7 Operation 0 0 0 0 0 0 0 0 0dB 1 0 0 0 0 0 0 0 1dB 0 1 0 0 0 0 0 0 2dB 1 1 0 0 0 0 0 0 3dB 0 0 1 0 0 0 0 0 4dB 1 0 1 0 0 0 0 0 5dB 0 1 1 0 0 0 0 0 6dB 1 1 1 0 0 0 0 0 7dB 0 0 0 1 0 0 0 0 8dB 1 0 0 1 0 0 0 0 9dB 0 1 0 1 0 0 0 0 10dB 1 1 0 1 0 0 0 0 11dB 0 0 1 1 0 0 0 0 12dB 1 0 1 1 0 0 0 0 13dB 0 1 1 1 0 0 0 0 14dB 1 1 1 1 0 0 0 0 15dB 0 0 0 0 1 0 0 0 16dB 1 0 0 0 1 0 0 0 17dB 0 1 0 0 1 0 0 0 18dB 1 1 0 0 1 0 0 0 19dB 0 0 1 0 1 0 0 0 20dB 1 0 1 0 1 0 0 0 21dB 0 1 1 0 1 0 0 0 22dB 1 1 1 0 1 0 0 0 23dB 0 0 0 1 1 0 0 0 24dB 1 0 0 1 1 0 0 0 25dB 0 1 0 1 1 0 0 0 26dB 1 1 0 1 1 0 0 0 27dB 0 0 1 1 1 0 0 0 28dB 1 0 1 1 1 0 0 0 29dB 0 1 1 1 1 0 0 0 30dB 1 1 1 1 1 0 0 0 31dB 0 0 0 0 0 1 0 0 32dB 1 0 0 0 0 1 0 0 33dB 0 1 0 0 0 1 0 0 34dB 1 1 0 0 0 1 0 0 35dB 0 0 1 0 0 1 0 0 36dB 1 0 1 0 0 1 0 0 37dB 0 1 1 0 0 1 0 0 38dB 1 1 1 0 0 1 0 0 39dB 0 0 0 1 0 1 0 0 40dB Continued on next page.
No.7332-7/13 Continued from preceding page. V olume control D0 D1 D2 D3 D4 D5 D6 D7 Operation 1 0 0 1 0 1 0 0 41dB 0 1 0 1 0 1 0 0 42dB 1 1 0 1 0 1 0 0 43dB 0 0 1 1 0 1 0 0 44dB 1 0 1 1 0 1 0 0 45dB 0 1 1 1 0 1 0 0 46dB 1 1 1 1 0 1 0 0 47dB 0 0 0 0 1 1 0 0 48dB 1 0 0 0 1 1 0 0 49dB 0 1 0 0 1 1 0 0 50dB 0 0 1 0 1 1 0 0 52dB 0 1 1 0 1 1 0 0 54dB 0 0 0 1 1 1 0 0 56dB 0 1 0 1 1 1 0 0 58dB 0 0 1 1 1 1 0 0 60dB 0 1 1 1 1 1 0 0 62dB 0 0 0 0 0 0 1 0 64dB 0 1 0 0 0 0 1 0 66dB 0 0 1 0 0 0 1 0 68dB 0 1 1 0 0 0 1 0 70dB 0 0 0 1 0 0 1 0 72dB 0 1 0 1 0 0 1 0 74dB 0 0 1 1 0 0 1 0 76dB 0 1 1 1 0 0 1 0 78dB 0 0 0 0 1 0 1 0 Channel selection D8 D9 Operation 0 0 Normally not used 1 0 RCH 0 1 LCH 1 1 Left and right channels together Test mode D10 D11 D12 D13 D14 D15 Operation 0 0 0 0 0 0 These bits specify the IC test mode. They must be set to zero for normal operation.
No.7332-8/13 Pin Functions Pin name Pin No. Function Notes LIN RIN Volume control inputs LOUT ROUT Volume control outputs Vref 7 VDD 0.5 voltage generator block for the analog ground level. A capacitor with a value a few times 10 μF must be inserted between Vref and AVSS (VSS) to minimize power supply ripple. VSS 8 Ground VDD 3 Power supply CE 6 Chip enable The internal latch data is written and the analog switches operate at the point this pin goes from high to low. Data transfer is enabled when this pin is at the high level. DI CL Serial data and clock inputs for IC control. VDD OUT VDD VRIN VDD VDD Vref
No.7332-9/13 Equivalent Circuit LIN 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB -16dB -17dB -18dB -19dB -20dB -21dB -22dB -23dB -24dB -25dB -26dB -27dB R28=243 R29=216 R30=193 R31=172 R32=153 R33=137 R34=122 R35=108 R36=97 R37=86 R38=77 R39=68 R40=61 R41=54 R42=48 R43=86 R44=77 R45=69 R46=61 R47=55 R48=49 R49=87 R50=77 R51=130 R52=104 R1=5434 R2=4845 R3=4319 R4=3850 R5=3431 R6=3058 R7=2726 R8=2429 R9=2165 R10=1930 R11=1720 R12=1533 R13=1366 R14=1218 R15=1085 R16=967 R17=862 R18=768 R19=685 R20=610 R21=544 R22=485 R23=432 R24=385 R25=343 R26=306 R27=273 R67=796 R66=794 -28dB -29dB -30dB -31dB -32dB -33dB -34dB -35dB -36dB -37dB -38dB -39dB -40dB -41dB -42dB -43dB -44dB -45dB -46dB -47dB -48dB -49dB -50dB -52dB -54dB R53=164 R54=130 R55=104 R56=165 R57=131 R58=104 R59=165 R60=131 R61=104 R62=165 R63=131 R64=104 R65=403 R71=804 R70=802 R69=800 R68=798 LOUT LVref -56dB -58dB -60dB -62dB -64dB -66dB -68dB -70dB -72dB -74dB -76dB -78dB -dB The right channel is identical.
No.7332-10/13 Reference Voltage Generator Equivalent Circuit Test Circuit Total harmonic distortion VREF VDD 20k LVref 20k The right channel is identical. 22F VDD THDin DISTORTION ANALYZER S.G COM LC75344MD 2.2F 2.2F 1F 1F The right channel is identical.
No.7332-11/13 Output noise voltage Crosstalk Usage Notes The states of the internal analog switches are undefined after power is first applied. Muting must be applied externally until the control data has been sent. When performing the initial settings after power is first applied, both the left and right channel initial settings data must be sent before releasing the external mute. Either cover the CL, DI, and CE lines with the ground pattern or use shielded lines to prevent high-frequency digital noise from entering the analog signal system from these lines. 1k Noise METER 22F VDD COM LC75344MD 2.2F 2.2F 1F 1F The right channel is identical. The right channel is identical. 1k Volt METER 22F VDD COM LC75344MD 2.2F 2.2F 1F 1F S.G
No.7332-12/13 ILC05483V olume Step THD vs. Volume Control Step Characteristics Step ILC05482 Level — dB Volume Step Characteristics Total harmonic distortion, THD — %Total harmonic distortion, THD — % Total harmonic distortion, THD — % Total harmonic distortion, THD — % Supply voltage — V ILC05487 THD vs. Input Level Characteristics THD vs. Supply Voltage Characteristics ILC05485 Frequency — Hz Crosstalk Characteristics Level — dB ILC05486 Frequency — Hz THD vs. Frequency Characteristics ILC05484 Input level — dBV –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 VDD=9V VSS=0V f=1kHz VIN=0dBV –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 –20 –10–30 0 10–40 0.0001 0.001 1.0 0.1 0.01 10kHz 1kHz –20 –10–30 0 10–40 0.0001 0.001 1.0 0.1 0.01 10kHz 1kHz 1000 10000100 10000010 23 5 7 23 5 7 23 5 7 23 5 7 1000 10000100 10000010 23 5 7 23 5 7 23 5 7 23 5 7 0.0001 0.001 0.1 0.01 VDD=9V VSS=0V 80kHz LPW All settings flat overall. VDD=9V VSS=0V 80kHz LPW All settings flat overall. VDD=9V VSS=0V 80kHz LPW 0dBV VIN= –10dBV VDD=9V VSS=0V f=1kHz VIN=0dBV(LIN) Vin = 1 kΩ, terminated (RIN) ROUT Measured 91 0871 1 1 26 0.001 0.01 10kHz 1kHz 100Hz VDD=9V VSS=0V 80kHz LPW All settings flat overall.
PS No.7332-13/13
ORDERING INFORMATION
Device Package Shipping (Qty / Packing) LC75344MD-AH SOIC-10 NB (Pb-Free / Halogen Free) 2500 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use a s components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and dis tributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personali n j u r yo r death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture oft h e part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.