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40114HK/30613HKPC 20130208-S00001 No.A2168-1/26 Semiconductor Components Industries, LLC, 2014 April, 2014 http://onsemi.com LC75055PE Overview LC75055PE is a Digital Sound Processor which integrates audio signal processor, A/D, D/A, and volume into a single chip which are the prerequisites for car audio DSP. Programs are downloaded from internal Flash ROM into DSP RAM. (Caution) On-board programming to the Flash ROM of LC75055PE is not available. (Data is programmable only before delivery by Our company.) Hardware overview specification Parameter Note Analog input (stereo) Balanced x2, Single x1 or Balanced x1, Single x3 Analog input (monaural) Balanced x2, Single x1 or Balanced x1, Single x3 ADC 24bit 2 stereo ch, 2 monaural ch DAC 24bit + EVR 3 stereo ch Digital input (IIS) Maximum 5 stereo ch (slave) Digital output (IIS) Maximum 4 stereo ch (master) Input through output 1 stereo ch Sampling rate converter (SRC) Maximum 4 stereo ch (3 or 4 ch Synchronous input) Main microcontroller serial interface Serial interface (I 2C or SPI) DSP (24bit) 220MIPS (DSP 2 Core: operation at 110MHz) Supply voltage Logic (DSP) : 1.5V PLL circuit : 3.3V Crystal oscillation, digital I/O power supply : 3.3V CODEC analog power supply : 3.3V CMOS LSI Car Audio DSP * I2C Bus is a trademark of Philips Corporation. * This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 26 of this data sheet. QIP100E(14X20)
No.A2168-2/26 Specifications Parameter Symbol Applicable pins Ratings Unit Maximum supply voltage V DD max1 CODEC power supply pin -0.3 to +3.9 V VDD max2 Power supply pin for oscillation circuit -0.3 to +3.9 V Digital 3.3V power supply pin -0.3 to +3.9 V VDD max3 Logic (DSP) -0.3 to +1.8 V Maximum input voltage V IN1 CODEC Analog input pin -0.3 to V DD max1 +0.3 V VIN2 Oscillation circuit input pin, TEST setting input pin -0.3 to VDD max2 +0.3 V VIN3 Digital input pin -0.3 to +6.0 V Maximum output current I O All output pin 6.0 mA Allowable power dissipation Pd max Ta = 85 C (Note 1) 900 mW Operating temperature Topr -40 to +85 C Storage temperature Tstg -55 to +125 C Note 1: For a chip mounted on a reference board. (board size: 105 75 1.6mm 4-layer) Allowable Operating Range at Ta = -40 to 85C, DVSS_1 to 3 = COAVSS1 to 6 =AVB = XVSS = AVCOVSS = 0V Parameter Symbol Applicable pins min typ max Unit Supply voltage CODEC ANALOG AVDD CODEC power supply pin 3.14 3.3 3.47 V Supply voltage XTAL, DSP_IO DVDD33 Power supply pin for oscillation circuit Digital 3.3V power supply pin 3.14 3.3 3.47 V Supply voltage PLL AVCOVDD Power supply pin for PLL 3.14 3.3 3.47 V Supply voltage Logic DVDD Power supply pin for Logic 1.43 1.5 1.58 V Input high level voltage V IH1 All digital input pin except for XIN 2.0 5.5 *1 V Input high level voltage V IH2 XIN 2.0 DV DD33 V Input low level voltage V IL1 All digital input pin 0 0.8 V Crystal oscillation frequency (256fs) Fosc XIN, XOUT (fs = 44.1kHz) *2 11.2896 MHz XIN, XOUT (fs = 48kHz) *2 12.288 MHz *1) Only when power is supplied to all the power supplies, you can supply power to input pin up to 5.5V. When the power is turned off, only supply the power up to 3.6V. *2) Crystal for oscillator CI value: CI 150 The evaluation by the crystal supplier is recommended. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recomme nded Operating Ranges limits mayaffect device reliability.
No.A2168-3/26 Parameter Symbol Conditions and applicable pin min typ max Unit Input high level current I IH All digital input pin 10 A Input low level current I IL All digital input pin -10 A Output high level voltage V OH I OH = -2mA: Digital output pin except for DSPIO4, SDAS 2.4 V IOH = -4mA: DSPIO4, SDAS 2.4 V Output low level voltage V OL I OL = 2mA: Digital output pin except for DSPIO4, SDAS 0.4 V IOL = 4mA: DSPIO4, SDAS 0.4 V Output OFF leak current IOFF Unloaded: All digital output pin -10 10 A Crystal oscillator feedback resistance Rf XIN, XOUT 1.0 M CODEC reference voltage VREF ADC_REF, ADC_REF 0.5*AV DD V Power supply current I DDA33 COAV DD1, 2, 3, 4, 5, 6 AVCOAVDD 110 157 mA IDDD33 DV DD33, XVDD 10 12.5 mA IDDD15 DV DD_1, 2 120 173 mA DVSS_1 to 3 = COAVSS1 to 6 =AVB = XVSS = AVCOVSS = 0V Ta = 25C, fs = 44.1kHz, signal frequency 1kHz, measurement band = 10Hz to 20kHz Parameter Symbol Conditions and applicable pin min typ max Unit (Input selector + ADC) Full-scale analog input level 0.85*AV DD Vp-p Analog block input impedance 20 30 k Gain setting level -12 +19 dB Gain setting step 1 dB Error between gain setting steps -0.5 +0.5 dB S/N w/ A-weighted 90 95 dB w/o A-weighted 87 92 dB Dynamic range w/ A-weighted 90 95 dB w/o A-weighted 87 92 dB THD+N Input condition: -3dBFS -90 -80 dB Cross talk 1 Input condition: -3dBFS, 1kHz Cross talk between AUX Lch and Rch when AUX differential input is used. -75 -65 dB Cross talk 2 Input condition: -3dBFS, 1kHz Other than cross talk1 -90 -80 dB (ADC digital filter) Pass band frequency 0 0.4535 fs Stop band frequency 0.5465 fs Pass band ripple 0.04 dB Stop band attenuation -69 dB HPF cutoff frequency DC for offset cancellation fs: 44.1kHz 0.86 Hz (Audio DAC) Full-scale analog output level 0.85*AV DD Vp-p S/N w/ A-weighted 94 100 dB w/o A-weighted 91 97 dB Dynamic range w/ A-weighted 94 100 dB w/o A-weighted 91 97 dB THD+N -3dBFS -91 -80 dB Cross talk Input condition: full-scale, 1kHz -100 -85 dB Mute level w/ A-weighted 94 100 dB Continued on next page.
No.A2168-4/26 Continued from preceding page. Parameter Symbol Conditions and applicable pin min typ max Unit (ADC digital filter) Pass band frequency 0 0.4535 fs Stop band frequency 0.5465 fs Pass band ripple 0.015 dB Stop band attenuation -62 dB HPF cutoff frequency for DC offset cancellation fs: 44.1kHz 1.7 Hz (EVR) Input impedance ZEVRI 20 25 k Volume setting range -70 0 dB Mute level 85 95 dB Volume step 1 dB Volume setting step error -0.5 0.5 dB 1.5V reference level characteristics at Ta = -40 to 85C, DVDD33 = 3.3V, DVSS_1 to 3 = COAVSS1 to 6 =AVB = XVSS = AVCOVSS = 0V Parameter Symbol Condition min typ max Unit FET Control Output voltage DVREF DV DD33 = 3.3V 0 3.3 V <Addition>
- 1.5V reference level circuit is a circuit that prepared 1.5V power-supply voltage needed in this LSI to be easily generable. The power supply of 1.5V is enabled by using recommendation FET shown in Figure 5-1. <Figure 5-1> 1.5V reference level circuit peripheral block
- As for power supply ON, the order of DVDD33 power supply voltage (3.3V) to FET source supply voltage (3.3V) is recommended. DVDD33 DVSS_2 DVREF DVDD_2 DVDD_1 LC75055PE 10nF 10F 3.3V 1.5V FET D S G * FET Recommended Device No. NTR2101P (ON Semiconductor) * C1 is the capacitor to prevent oscillation. In the range of operating temperature, make sure to maintain low ESR and the capacitance recommended value is 10F because oscillation may occur when the capacitance value changes due to the change of temperature. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per formance may not be indicated by the Electrical Characteristics if operated under different conditions.
No.A2168-5/26 Package Dimensions unit : mm PQFP100 14x20 / QIP100E CASE 122BV ISSUE A XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data GENERIC MARKING DIAGRAM* *This information is generic. Please refer to device data sheet for actual part marking. XXXXXXXXX YMDDD (Unit: mm) 22.30 16.30 0.430.65 1.30 SOLDERING FOOTPRINT* NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 20.0±0.1 0.65 (0.58) 0.13 14.0±0.1 17.2±0.2 23.2±0.2 100 0.3±0.05 0.10
3.0 MAX
(2.7)0.1±0.1 0~10° 0.15 0.8±0.2
No.A2168-6/26 Pin Assignment COAVSS6 AVB EVROUT1L EVRIN1L DACOUT1L DACOUT1R EVRIN1R EVROUT1R EVROUT2L EVRIN2L DACOUT2L DACOUT2R EVRIN2R EVROUT2R EVROUT3L EVRIN3L DACOUT3L DACOUT3R EVRIN3R EVROUT3R AVCOAVSS AVCOAVDD XVDD XOUT XIN XVSS DVSS_1 DVDD_1 OUT_SEL3 OUT_SEL2 COAVDD2 COAVSS1 COAVDD1 VREFAMPO ADC_VREF DAC_VREF MIN3 MIN2N MIN2P MIN1P MIN1N TEST1 TEST2 DVSS_3 DVDD33 MODE BUSYO SP_DO/SDAS SP_CL/SCLS SP_DI/GPIO_2 SP_SSB/GPIO_3 GPO_1(ERR) PWDB RSTB DSPIO1 DVDD_2 DVSS_2 DVREF DVDD33 DSPIO2 DSPIO3 DSPIO4 IISI1_DATA IISI1_LRCK IISI1_BCLK IISI2_DATA IISI2_LRCK IISI2_BCLK IISI3_DATA IISI3_LRCK IISI3_BCLK IISI4_DATA IISI4_LRCK IISI4_BCLK IIS_SUB1 IIS_SUB2 IIS_SUB3 IISO_BCLK IISO_LRCK OUT_SEL1 COAVSS2 AIN3LO AIN3LN AIN3LP COAVDD3 COAVSS3 AIN3RP AIN3RN AIN3RO COAVDD4 COAVSS4 AIN2L AIN2R AIN1LP AIN1LN AIN1RN AIN1RP COAVDD5 COAVSS5 COAVDD6 100 LC75055PE (Top view)
No.A2168-7/26 Block Diagram DVDD_1 DVSS_1 DVSS33 DVSS_3 DVDD33 DVDD_2 DVSS_2 DVREF COAVDD1 COAVSS1 MIN1P MIN1N MIN2N MIN2P MIN3 COAVDD2 COAVSS2 AIN3RO AIN3RN AIN3RP AIN3LP AIN3LN AIN3LO AIN2R AIN2L AIN1RP AIN1RN AIN1LN AIN1LP COAVDD3 COAVSS3 VREFAMPO ADC_VREF COAVDD4 COAVSS4 DAC_VREF EVROUT1L EVRIN1L DACOUT1L DACOUT1R EVRIN1R EVROUT1R EVROUT2L EVRIN2L DACOUT2L DACOUT2R EVRIN2R EVROUT2R EVROUT3L EVRIN3L DACOUT3L DACOUT3R EVRIN3R EVROUT3R Digital Filters for ADC Digital Filters for DAC P-S Circuit for Digital outputs Digital inputs Selectors Audio Clock Control IISI1_DATA IISI1_LRCK IISI1_BCLK IISI2_DATA IISI2_LRCK IISI2_BCLK IISI3_DATA IISI3_LRCK IISI3_BCLK IISI4_DATA IISI4_LRCK IISI4_BCLK IIS_SUB1 IIS_SUB2 IIS_SUB3 OUT_SEL1 OUT_SEL2 OUT_SEL3 IISO_LRCK IISO_BCLK DSPIO1 DSPIO2 DSPIO3 DSPIO4 SP_CL/SCLS SP_DI/GPIO_2 SP_SSB/GPIO_3 SP_DO/SDAS BUSYO GPO_1(ERR) MODE RSTB PWDB TEST1 TEST2 Sampling Rate Converters (4ch) Host I/F VCO Audio DSP XVSS XVDD XIN XOUT AVCOVDD AVCOVSS COAVSS6 COAVDD6 COAVSS5 COAVDD5 AVB 24Bit ADC (Mono 2ch) Analog Input Source Selectors Analog Input Source Selectors EVR EVR 24Bit Stereo DAC EVR EVR 24Bit Stereo DAC Buffer 24Bit ADC (Stereo_1) 24Bit ADC (Stereo_2) EVR EVR 24Bit Stereo DAC IIS_SUB Control 1.5V Reference output
No.A2168-8/26 Pin functions No Pin name Input/output Input/output (RSTB=L) Functions 1 COAV DD2 Power supply for CODEC analog (3.3V)
2 COAV SS1 Power supply for CODEC analog (GND)
3 COAV DD1 Power supply for CODEC analog (3.3V)
4 VREFAMPO AO AO Reference voltage buffer outp ut pin, used as external reference voltage
5 ADC_VREF AO AO Reference voltage output pin for CODEC ADC
A coupling capacitor is required between this pin and GND.
6 DAC_VREF AO AO Reference voltage output pin for CODEC DAC
A coupling capacitor is required between this pin and GND.
7 MNI3 AI AI Analog single-end input pin for monaural3
When this pin is unused, connect it to GND via capacitor.
8 MNI2N AI AI
Negative analog input pin for monaural 2 or Analog single-end input pin for monaural 5. When this pin is unused, connect it to GND via capacitor.
9 MNI2P AI AI
Positive analog input pin for monaural 2 or Analog single-end input pin for monaural 4. When this pin is unused, connect it to GND via capacitor.
10 MNI1P AI AI Positive analog input pin for monaural 1
When this pin is unused, connect it to GND via capacitor.
11 MNI1N AI AI Negative analog input pin for monaural 1
When this pin is unused, connect it to GND via capacitor. 12 TEST1 I I Test mode setting input pin1. Normally connected to GND 13 TEST2 I I Test mode setting input pin2. Normally connected to GND
14 DV SS_3 Power supply for digital (GND)
15 DV DD33 Power supply for digital (3.3V)
16 MODE I Select pin for serial communication mode (“0”: I 2C, “1”: SPI)
17 BUSYO O O (H) System busy signal output pin for HOST CPU communication
(High level: the system is busy)
18 SP_DO/SDAS I/O I Data output pin for SPI (slave) communication or
data input/ output pin for IIC (Slave) communication
19 SP_CL/SCLS I I Clock input pin for data transfer for SPI (slave) communication or
data transfer clock input pin for IIC (Slave) communication
20 SP_DI/GPIO_2 I/O I Data input pin for SPI (slave) communication or
General-purpose input/output pin2 for Audio DSP
21 SP_SSB/GPIO_3 I/O I Enable signal input pin for SPI (slave) communication (Active: low level) or
General-purpose input/output pin3 for audio DSP
22 GPO_1 (ERR) O O(L) General-purpose output pin 1 for integrated DSP (will be designed to correspond to
communication error signal output) 23 PWDB I I Power-down mode setting pin. Normally high level. 24 RSTB I I System reset pin. Make sure to set to low level when turning on power.
25 DSPIO1 I/O I Audio DSP general input/output pin 1
26 DV DD_2 Power supply for internal logic (1.5V)
27 DV SS_2 Power supply for digital (GND)
28 DVREF O Control output pin for 1.5V level 29 DV DD33 Power supply for digital (3.3V)
30 DSPIO2 I/O I Audio DSP general-purpose input/output pin2
31 DSPIO3 I/O I Audio DSP general-purpose input/output pin3
32 DSPIO4 I/O I Audio DSP general-purpose input/output pin4 or 256fs_clock out pin.
33 IISI1_DATA I I IIS data input pin1
34 IISI1_LRCK I I IIS word clock input pin1
35 IISI1_BCLK I I IIS bit clock input pin1
36 IISI2_DATA I I IIS data input pin2
37 IISI2_LRCK I I IIS word clock input pin2
38 IISI2_BCLK I I IIS bit clock input pin2
39 IISI3_DATA I I IIS data input pin3
40 IISI3_LRCK I I IIS word clock input pin3
41 IISI3_BCLK I I IIS bit clock input pin3
42 IISI4_DATA I I IIS data input pin4
Continued on next page.
No.A2168-9/26 Continued from preceding page. No Pin name Input/output Input/output (RSTB=L) Functions
43 IISI4_LRCK I I IIS word clock input pin4
44 IISI4_BCLK I I IIS bit clock input pin4
45 IIS_SUB1 I/O I IIS data input pin5 or
IIS data output pin1 or IIS data output pin4
46 IIS_SUB2 I/O I IIS data input pin6 or IIS word clock input pin5 or
IIS data output pin2 or IIS word clock output pin4
47 IIS_SUB3 I/O I IIS data input pin7 or IIS bit clock input pin5 or
IIS data output pin3 or IIS bit clock output pin4
48 IISO_BCLK O O (L) IIS bit clock output pin (for IIS data output 1 to 3)
49 IISO_LRCK O O (L) IIS word clock output pin (for IIS data output 1 to 3)
50 OUT_SEL1 O O (L) IIS data output pin1 or IIS data output pin4 or internal signal output pin1
(During reset, this pin is fixed to low level output.)
51 OUT_SEL2 O O (L) IIS data output pin2 or IIS word clock output pin4 or internal signal output pin2
(During reset, this pin is fixed to low level output.)
52 OUT_SEL3 O O (L) IIS data output pin3 or IIS bit clock output pin4 or internal signal output pin3
(During reset, this pin is fixed to low level output.) 53 DV DD_1 Power supply for internal logic (1.5V)
54 DV SS_1 Power supply for digital (GND)
55 XV SS Crystal for oscillation circuit power supply. (GND) 56 XIN Oscillation Crystal oscillation circuit input (11.2896MHz or 12.288MHz)
57 XOUT Oscillation Crystal oscillation circuit output
58 XV DD Crystal for oscillation circuit power supply (3.3V) 59 AVCOAV DD VCO analog power supply for CODEC main clock generation(3.3V)
60 AVCOAV SS VCO analog power supply for CODEC main clock generation (GND)
61 EVROUT3R AO AO
Electronic volume output pin. When output of EVR3 is OFF, EVRIN3R input signal output to EVROUT3R via 50k register.
62 EVRIN3R AI AI
Electronic volume input pin. Make sure to connect this pin with DACOUT3R (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor. 63 DACOUT3R AO AO DAC analog output pin. (R-channel output) When output of DAC3 is OFF, pin output becomes GND. 64 DACOUT3L AO AO DAC analog output pin. (L-channel output) When output of DAC3 is OFF, pin output becomes GND.
65 EVRIN3L AI AI
Electronic volume input pin. Make sure to connect this pin with DACOUT3L (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor.
66 EVROUT3L AO AO
Electronic volume output pin. When output of EVR3 is OFF, EVRIN3L input signal output to EVROUT3L via 50k register.
67 EVROUT2R AO AO
Electronic volume output pin. When output of EVR2 OFF, EVRIN2R input signal output to EVROUT2R via 50k register.
68 EVRIN2R AI AI
Electronic volume input pin. Make sure to connect this pin with DACOUT2R (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor. 69 DACOUT2R AO AO DAC analog output pin. (R-channel output) When output of DAC2 is OFF, pin output becomes GND. 70 DACOUT2L AO AO DAC analog output pin. (L-channel output) When output of DAC2 is OFF, pin output becomes GND.
71 EVRIN2L AI AI
Electronic volume input pin. Make sure to connect this pin with DACOUT2L (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor.
72 EVROUT2L AO AO
Electronic volume output pin. When output of EVR2 is OFF, EVRIN2L input signal output to EVROUT2L via 50k register.
73 EVROUT1R AO AO
Electronic volume output pin. When output of EVR1 is OFF, EVRIN1R input signal output to EVROUT1R via 50k register. Continued on next page.
No.A2168-10/26 Continued from preceding page. No Pin name Input/output Input/output (RSTB=L) Functions
74 EVRIN1R AI AI
Electronic volume input pin. Make sure to connect this pin with DACOUT1R (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor. 75 DACOUT1R AO AO DAC analog output pin. (R-channel output) When the output setting of DAC1 is OFF, the pin output becomes GND. 76 DACOUT1L AO AO DAC analog output pin. (L-channel output) When the output setting of DAC1 is OFF, the pin output becomes GND.
77 EVRIN1L AI AI
Electronic volume input pin. Make sure to connect this pin with DACOUT1L (DAC output) via coupling capacitor. When this pin is unused, leave it open or connect it to GND via capacitor.
78 EVROUT1L AO AO
Electronic volume output pin. When the output setting of EVR1 is OFF, EVRIN1L input signal output to EVROUT1L via 50k register.
79 AVB
CODEC Substrate GND pin. Make sure to connect this pin to GND with low impedance. Note that when the pin is open, latch-up may occur.
80 COAV SS6 Power supply for CODEC analog (GND)
81 COAV DD6 Power supply for CODEC analog (3.3V)
82 COAV SS5 Power supply for CODEC analog (GND)
83 COAV DD5 Power supply for CODEC analog (3.3V)
84 AIN1RP AI AI
R-channel for stereo1 Positive analog input pin. or R-channel for stereo 4 analog input pin. When this pin is unused, connect it to GND via capacitor.
85 AIN1RN AI AI
R-channel for stereo 1 Negative analog input pin. or L-channel for stereo 4 analog input pin. When this pin is unused, connect it to GND via capacitor.
86 AIN1LN AI AI
L-channel for stereo 1 Negative analog input pin. or R-channel for stereo 5 analog input pin. When this pin is unused, connect it to GND via capacitor.
87 AIN1LP AI AI
L-channel for stereo1 Positive analog input pin. or L-channel for stereo 5 analog input pin. When this pin is unused, connect it to GND via capacitor. 88 AIN2R AI AI R-channel for stereo 2 analog input pin. When this pin is unused, connect it to GND via capacitor. 89 AIN2L AI AI L-channel for stereo 2 analog input pin. When this pin is unused, connect it to GND via capacitor.
90 COAV SS4 Power supply for CODEC analog (GND)
91 COAV DD4 Power supply for CODEC analog (3.3V)
92 AIN3RO AO AO R-channel for stereo 3 Op Amp output pin
93 AIN3RN AI AI R-channel for stereo 3 Op Amp inverting input pin. When this pin is unused, connect it to GND via capacitor. 94 AIN3RP AI AI R-channel for stereo 3 Op Amp non-inverting input pin. When this pin is unused, connect it to GND via capacitor.
95 COAV SS3 Power supply for CODEC analog (GND)
96 COAV DD3 Power supply for CODEC analog (3.3V) 97 AIN3LP AI AI L-channel for stereo 3 Op Amp non-inverting input pin. When this pin is unused, connect it to GND via capacitor. 98 AIN3LN AI AI L-channel for stereo 3 Op Amp inverting input pin. When this pin is unused, connect it to GND via capacitor.
99 AIN3LO AO AO L-channel for stereo 3 Op Amp output pin
100 COAV SS2 Power supply for CODEC analog (GND)
(Caution) * Make sure to connect decoupling capacitor between VDD and VSS. * The unused input pins that are not particularly specified above should be connected to GND. * The unused output pins that are not particularly specified above should be left open (do not connect to anything else). * Make sure to connect AVB (#79) to GND.(When the pin is open, latch-up may occur).
No.A2168-11/26 Input/Output PIN equivalent circuit I/O Equivalent circuit Pin Comment Digital input TEST1 : 12 TEST2 : 13 MODE : 16 5V-Tolerant Digital input SP_CL/SCLS : 19 PWDB : 23 IISI1_DATA : 33 IISI1_LRCK : 34 IISI1_BCLK : 35 IISI2_DATA : 36 IISI2_LRCK : 37 IISI2_BCLK : 38 IISI3_DATA : 39 IISI3_LRCK : 40 IISI3_BCLK : 41 IISI4_DATA : 42 IISI4_LRCK : 43 IISI4_BCLK : 44 5V-Tolerant Digital input RSTB : 24 5V-Tolerant 3.3V Output (Inverting) Digital output BUSYO : 17 GPO_1(ERR) : 22 IISO_BCLK : 48 IISO_LRCK : 49 OUT_SEL1 : 50 OUT_SEL2 : 51 OUT_SEL3 : 52 5V-Tolerant Digital input/output SP_DI/GPIO_2 : 20 SP_SSB/GPIO_3 : 21 DSPIO1 : 25 DSPIO2 : 30 DSPIO3 : 31 IIS_SUB1 : 45 IIS_SUB2 : 46 IIS_SUB3 : 47 5V-Tolerant Digital input/output SP_DO/SDAS : 18 DSPIO4 : 32 5V-Tolerant
No.A2168-12/26 I/O Equivalent circuit Pin Oscillation circuit XIN : 56 XOUT : 57 I/O Equivalent circuit Pin DAC DACOUT3R : 63 DACOUT3L : 64 DACOUT2R : 69 DACOUT2L : 70 DACOUT1R : 75 DACOUT1L : 76 EVR In/Out VINDA EVRIN3R : 62 EVRIN3L : 65 EVRIN2R : 68 EVRIN2L : 71 EVRIN1R : 74 EVRIN1L : 77 VOUT EVROUT3R : 61 EVROUT3L : 66 EVROUT2R : 67 EVROUT2L : 72 EVROUT1R : 73 EVROUT1L : 78 I/O Equivalent circuit Pin VREF AMP Output VREFAMPO : 4 VREF Output ADC_VREF : 5 DAC_VREF : 6 VOUT VINDA DAC_VREF Inner ADC_VREF
No.A2168-13/26 I/O Equivalent circuit Pin Analog input (differential) INN AIN3RN : 93 AIN3LN : 98 INP AIN3RP : 94 AIN3LP : 97 COMPO AIN3RO : 92 AIN3LO : 99 Analog Selector input (stereo) AINN AIN1RN : 85 AIN1LN : 86 AIN2 AIN2R : 88 AIN2L : 89 AINP AIN1RP : 84 AIN1LP : 87 COMPO INN INP AINN AIN2 AINP Inner ADC_VREF
No.A2168-14/26 I/O Equivalent circuit Pin Analog Selector input (monaural) MIN3 : 7 MIN2P : 9 MIN1P : 10 MIN1N : 11 MIN2N : 8 Inner ADC_VREF
No.A2168-15/26 Power On/Off Timing (1) Power supply ON timing order *1) When a 1.5V power supply is applied in external power source directly, Please refer to this sequential order. RSTB signal should be set in Low level more than 1ms from either late power supply turned on or positive edge of the PWDB signal.. In addition, the reset time is less than 100msec. When a 1.5V power supply is produced using a onchip 1.5V reference level and external FET, It is recommended that 3.3V power supply of LC75055 (DVDD33) and 3.3V power of external FET are turned on the following order. Parameter Symbol Conditions Min Typ Max Unit Power on (3.3V 1.5V) tpup3315 0 100 msec Power on (3.3V 3.3V) tpup3333 0 (2) Power supply OFF timing order *2) When a 1.5V power supply is applied in external power source directly, Please refer to this sequential order. Parameter Symbol Conditions Min Typ Max Unit Power off (1.5V 3.3V) tpdn1533 0 100 msec In addition, 5V-Tolerant input pin of LC75055 can input 3.6V voltage even if in power supply OFF condition. Furthermore, it can be applied to 5V after regular voltage was applied to each power supply. Be careful because the I/O direction of the pin is not decided before a 1.5V power supply being input. In the voltage of each power supply, the voltage of the 3.3V power supply must be higher than the voltage of the 1.5V power supply. 3.3V Power supply (1.5V Power PWDB RSTB BUSYO tpup3315 1ms After BUSYO=Low, command acceptable 0ms (min) 100 ms (max) max time from RSTB=“H” to BUSY=“L” 3.3V power supply (1.5V Power tpdn1533 tpup33333.3V (DVDD33) 3.3V (FET)
No.A2168-16/26 Audio input Function (1) Digital audio input LC75055 has 4ch sampling rate converter as digital audio input, and Implement an independent selector circuitry every channel. (2) Digital input format 1) Pin Name IISI1_DATA, IISI1_LRCK, IISI1_BCLK, IISI2_DATA, IISI2_LRCK, IISI2_BCLK, IISI3_DATA, IISI3_LRCK, IISI3_BCLK, IISI4_DATA, IISI4_LRCK, IISI4_BCLK, IIS_SUB1 (*1), IIS_SUB2(*1), IIS_SUB3(*1) 2) Mode MASTER MODE, SLAVE MODE 3) Format IIS MODE, LEFT JUSTIFIED MODE, RIGHT JUSTIFIED MODE (*2) 4) Bit length 16bit, 20bit, 24bit (*2) 5) BCLK Frequency max 64fs (selectable from 32fs, 48fs, 64fs) 6) Input fs 8kHz to 96kHz (Internal automatic distinction) (*1) As for the pin of IIS_SUB1/2/3, input or output is selectable. (*2) These modes can be set independently in IIS1 and IIS2. The setting method is shown in software specifications. (3) IIS MODE input timing (4) LEFT JUSTIFIED MODE Input Timing (5) RIGHT JUSTIFIED MODE Input Timing (6) Combination of IIS Input/Output About IIS application pin, the following configurations are enabled.
- 4 independent input and 4 output
- 5 independent input and 3 output
- 3 independent input and 3 multi-channel input and 3 output The setting method is shown in software specifications. BCLK DATA 1 2 3 n-1 n 1 2 3 n-1 n LRCK LEFT CHANNEL RIGHT CHANNEL MSB LSB MSB LSB 1BCL 1BCL BCLK DATA 1 2 3 n-1 n 123 n - 1 n LRCK RIGHT CHANNEL LEFT CHANNEL MSB LSB MSB LSB BCLK DATA 1 2 3 n-1 n 1 2 3 n-1 n LRCK RIGHT CHANNEL LEFT CHANNEL MSB LSB MSB LSB
No.A2168-17/26 (7) Input timing chart Parameter symbol Conditions Min Typ Max Unit LRCK Cycle Time - 8 96 kHz BCLK Cycle Time t BCY BCLK : 64FS 512 6144 kHz BCLK : 32FS 256 3072 BCLK pulse width “H” t BCH 60 nsec BCLK pulse width “L” t BCL 60 nsec LRCK setup time to BCLK rising edge t LRSU 30 nsec LRCK hold time to BCLK rising edge t LRH 30 nsec DATA setup time to BCLK rising edge t DS 30 nsec DATA hold time to BCLK rising edge t DH 30 nsec (8) Sampling rate Converter (SRC) The sampling rate converter converts the sampling frequency into internal 44.1kHz or 48kHz for IIS digital input. It is decided which frequency it is converted into by crystal to use. In the case of 44.1kHz Cr ystal oscillator is 11.2896MHz (44.1kHz × 256) In the case of 48kHz: Crystal osc illator is 12.288MHz (48kHz × 256) Setting of the control information is necessary. About the setting method, it is shown in software specification. 1) Input sampling frequency 8kHz to 96kHz 2) Output sampling frequency 44.1kHz or 48kHz 3) number of the channels: 4 stereo channel (8 channel) It takes 2782fs (based on fs of either slow input or output) period after starting input and output of the digital audio before SRC output is stable (THD+N is stable). Because noise may occur during this period, please do mute processing. tBCH tBCL tBCY tDStDH tLRH tLRSU BRCK LRCK DATA
No.A2168-18/26 (9) Analog audio input LC75055 has 2 ADCs (main/sub) for stereo sounds and 2 ADCs (INTA/INTB) for interruption monaural voices as analog audio in. In addition, a source select circuitry with gain setting is implemented in each ADC. As stereo input, one of single end input or op-amp input or the differential input can be chosen. As monaural voice inputting, one of single end input or the differential input can be chosen. 1) Main and Sub ADC input In audio main/sub ADC, a source selector of the single end input/op-amp input/differential input, and the Amp that can set a gain for each input individually are implemented. The gain set point of the main/sub is settable every each input source. Each amplifier gain is settable independently in the range of -12dB to +19dB (1dB step). In addition, please do mute processing because a noise may occur when gain setting is changed. About the setting command, it is shown on software specifications. single end input differential input Lch Rch Lch Rch Single end: 3 Differential: 1 AIN1LP AIN1LN AIN3LP, AIN3LN AIN3RP, AIN3RN AIN1RN AIN1RP AIN2L AIN2R Single end: 1 Differential: 2 AIN2L AIN2R AIN1LP, AIN1LN AIN1RP, AIN1RN AIN3LP, AIN3LN AIN3RP, AIN3RN About the method of these setting, it is appointed on software specifications. (i) Single end input: 3, differential input: 1 (ii) Single end input: 1, differential input: 2 AIN1RP AIN1RN AIN1LN AIN1LP AIN2R AIN2L AIN3RO AIN3RN AIN3RP AIN3LP AIN3LN AIN3LO R L R L Single end (AIN5) Single end (AIN4) Single end (AIN2) Differential (AIN3) AIN1RP AIN1RN AIN1LN AIN1LP AIN2R AIN2L AIN3RO AIN3RN AIN3RP AIN3LP AIN3LN AIN3LO Differential (AIN1) Single end (AIN2) Differential (AIN3)
No.A2168-19/26 2) Monaural ADC input Audio system ADC for interrupt sound (INTA/INTB) has the amplifier which can set a gain for a source selector of the single-end input/differential input and each input individually. The gain setting of INTA/INTB is settable every each input source. The range of the gain is -12 to +19dB (1dB steps), and set from the outside. In addition, perform mute processing by all means because the noise outbreak is possible at the time of the gain setting change. About the method of the gain setting change, it is appointed on software specifications. By a number and the kind of the interrupt sound, the following combination is enabled. Combination single end input differential input Single end: 3 Differential: 1 MIN2N MIN1P, MIN1N MIN2P MIN3 Single end: 1 Differential: 2 MIN3 MIN1P, MIN1N MIN2P, MIN2N About the method of these setting, it is appointed on software specifications. (i) Single end input: 3, differential input: 1 (ii) Single end input: 1, differential input: 2 (10) Internal digital filter characteristic in A/D and D/A converter block 1) A/D converter block 2) D/A converter block (8- TIMES OVER SAMPLING DIGITAL FILTER) MIN1N MIN1P MIN2P MIN2N MIN3 Differential input (MIN1) Single end (MIN4) Single end (MIN5) Single end (MIN3) MIN1N MIN1P MIN2P MIN2N MIN3 Differential input (MIN1) Differential input (MIN2) Single end (MIN3) ADC Digtal Filter Frequency Response (passband) -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0 5 10 15 20 Frequency [kfs] (fs=44.1kHz) amplitude [db] ADC Digtal Filter Frequency Response -140 -120 -100 -80 -60 -40 -20 01234 Frequency [×fs] amplitude [db] ADC Digtal Filter Frequency Response -140 -120 -100 -80 -60 -40 -20 00 . 51 2 3 1.5 2.5 3.5 4 Frequency [fs] Gain [dBFS] ADC Digtal Filter Ripple -0.1 -0.08 -0.09 -0.07 -0.06 -0.01 -0.02 -0.03 -0.04 -0.05 0 5 10 15 20 Frequency [kfs] (fs=44.1kHz) Gain [dBFS]
No.A2168-20/26 Audio output Function Digital audio output LC75055 has the digital output function of up to four systems. The digital output is fixed with IIS24bit/64fs format. (1) IIS output format (DSP processing) 1) Pin Name IISO_BCLK, IISO_LRCK, OUT_SEL1, OUT_SEL2, OUT_SEL3, IIS_SUB1 (*1), IIS_SUB2(*1), IIS_SUB3(*1) 2) Format IIS MODE 3) Mode MASTER mode 4) Bit length 24bit 5) BCLK Frequency 64fs (*1) As for the pin of IIS_SUB1/2/3, input or output is selectable. Timing Chart (2) Through output format LC75055 has a digital through output function other than four above digital output. With this mode, input data are output from the OUT_SEL1/2/3 terminal regardless of DSP processing. It is set from the outside which data are output from these terminals. 1) Selectable data IISI1_DATA, IISI1_LRCK, IISI1_BCLK, IISI2_DATA, IISI2_LRCK, IISI2_BCLK, IISI3_DATA, IISI3_LRCK, IISI3_BCLK, IISI4_DATA, IISI4_LRCK, IISI4_BCLK, IIS_SUB1 (*1), IIS_SUB2(*1), IIS_SUB3(*1) 2) Pin Assign OUT_SEL1 : DATA OUT_SEL2 : LRCK OUT_SEL3 : BCLK 3) Format As for the IIS output, an input signal is just output. When it is used by the through output, there are not the rules such as formats in particular. (*1) It is only on the condition that IIS_SUB1/2/3 is used as input. BCLK DATA 1 2 3 n-1 n 1 2 3 n-1 n LRCK LEFT CHANNEL RIGHT CHANNEL MSB LSB MSB LSB 1BCL 1BCL
No.A2168-21/26 MICON Interface As communication interface of a host microcomputer and this LSI, one of IIC method or SPI methods is selectable. The choice of the communication mode is decided by MODE pin. MODE: “0”: IIC Interface “1”: SPI Interface (1) I 2C Interface The IIC slave transmission and reception interface of this LSI is based on IIC Interface Specification ver.2.1. (Standard mode: 100Kbps, High speed mode: 400Kbps) The slave address of this LSI is 0x15 (value of upper 7 bits). The data to transfer assume 8 bits 1 unit. The format of the data transmission is performed according to the following. In addition, each byte data are the MSB first. Data write (6byte transmission example) Make sure to perform communication when BUSYO pin is “L”. If communication is started when BUSYO pin is “H”, the operation of LC75055 will not be guaranteed. Data read The content of each data is specified by the software specification. Stop (or Repeated Start) Slave address (0x15) data write Start SP_CL/SCLS W A A A A Ack data data Ack Ack Ack A A A data data data Ack Ack Ack SP_DO/SDAS C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 : Signals from LC75055PE to a master Slave address data Write Start SP_CL/SCLS W A A A A Ack data data Ack Ack Ack A A A data Ack Ack Ack Slave address Read R A Ack A A A Ack Ack Nak data data data data data Stop Start Wait until BUSYO becomes "L". Stop (or Repeated Start) SP_DO/SDAS C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 : Signals from LC75055PE to a master
No.A2168-22/26 Data access timing Symbol Timing Parameter Standard mode (100kbps) Fast mode (400kbps) unit Min Max Min Max a Start (Repeated-Start) condition hold time 4000 600 - ns b SP_CL/SCLS “P_ level pulse width 4700 1300 - ns c SP_CL/SCLS “HP level pulse width 4000 600 - ns d Start (Repeated-Start) condition setup time 4700 600 - ns e SP_DO/SDAS hold time 0 3450 0 900 ns f SP_DO/SDAS setup time 250 100 - ns g SP_CL/SCLS, SP_DO/SDAS rise time - 1000 20+0.1Cb (1) 300 ns h SP_CL/SCLS, SP_DO/SDAS fall time - 300 20+0.1Cb (1) 300 ns i Stop condition setup time 4000 600 - ns j Bus release time 4700 1300 - ns k Allowable spikes pulse width - 0 - ns Cb = total capacitance of one bus line in pF. (2) SPI Interface The SPI slave sending and receiving interface of this LSI communicates by using four terminals (SP_SSB/GPIO_3, SP_CL/SCLS, SP_DI/GPIO_2, and SP_DO/SDAS). The fast transfer in 2Mbps or less is possible unlike I2C method. The slave address is 0x15 (six bit value) when the data transfer is done to this LSI, and one unit of data is 8 bits. The data transfer is formatted as follows. Each byte data are the MSB first. Data write (Ex. 6byte transmission) Make sure to perform communication when BUSYO pin is “L”. If communication is started when BUSYO pin is “H”, the operation of LC75055 will not be guaranteed. SP_CL/SCLS e f cb h g i k j a h Start ad g SP_DO/SDAS Repeated Start Slave address (0x15) data Write Start SP_CL/SCLS A Ack Stop SP_DI/GPIO_2 SP_SSB/GPIO_3 data data SP_D0/SDAS data data data W C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 : Signals from LC75055PE to a master
No.A2168-23/26 Data read The content of each data is specified by the software specification. SP_CL/SCLS W A SP_DI/GPIO_2 SP_SSB/GPIO_3 SP_DO/SDAS Slave address data write Start Ack data data Stop data data data data Slave address read R A Ack data data Start Wait until BUSYO becomes "L". Stop SP_CL/SCLS SP_DI/GPIO_2 SP_SSB/GPIO_3 SP_DO/SDAS C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 : Signals from LC75055PE to a master
No.A2168-24/26 Data write timing Data read timing Symbol Parametre Min Typ Max Unit a SP_SSB setup time 500 ns b SP_SSB hold time 250 ns c SP_CL Low level pulse width 250 ns d SP_CL High level pulse width 250 ns e SP_DI setup time 100 ns f SP_DI hold time 100 ns g Command transfer interval 500 ns h SP_DO access time 0 100 ns i SP_DO hold time 120 ns SP_DI/GPO_2 fe SP_CL/SCLS dc SP_SSB/GPO_3 a g b SP_DO/SDAS SP_CL/SCLS dc SP_SSB/GPO_3 a b h i
No.A2168-25/26 Application Schematics Note 1) This application schematics is just for reference and the characteristics are not guaranteed. Note 2) The confirmation of the constant for the oscillator and the evaluation request to the oscillator vendor are recommended. COAVDD2 COAVSS1 COAVDD1 VREFAMPO ADC_VREF DAC_VREF MIN3 MIN2N MIN2P MIN1P MIN1N TEST1 TEST2 DVSS_3 DVDD33 MODE BUSYO SP_DO/SDAS SP_CL/SCLS SP_DI/GPIO_2 SP_SSB/GPIO_3 GPO_1(ERR) PWDB RSTB DSPIO1 DVDD_2 DVSS_2 DVREF DVDD33 DSPIO2 COAVSS6 AVB EVROUT1L EVRIN1L DACOUT1L DACOUT1R EVRIN1R EVROUT1R EVROUT2L EVRIN2L DACOUT2L DACOUT2R EVRIN2R EVROUT2R EVROUT3L EVRIN3L DACOUT3L DACOUT3R EVRIN3R EVROUT3R AVCOAVSS AVCOAVDD XVDD XOUT XIN XVSS DVSS DVDD_1 OUT_SEL3 OUT_SEL2 DSPIO3 DSPIO4 IISI1_DATA IISI1_LRCK IISI1_BCLK IISI2_DATA IISI2_LRCK IISI2_BCLK IISI3_DATA IISI3_LRCK IISI3_BCLK IISI4_DATA IISI4_LRCK IISI4_BCLK IIS_SUB1 IIS_SUB2 IIS_SUB3 IISO_BCLK IISO_LRCK OUT_SEL1 COAVSS2 AIN3LO AIN3LN AIN3LP COAVDD3 COAVSS3 AIN3RP AIN3RN AIN3RO COAVDD4 COAVSS4 AIN2L AIN2R AIN1LP AIN1LN AIN1RN AIN1RP COAVDD5 COAVSS5 COAVDD6 100 S D G LC75055PE AVSS AVDD D3.3 D3.3 AVSS DVSS DVSS FL FR RL RR Cen SW D-out (1-3) D-in or D-out D-in (1-4) Host I/F M-Comp1 M-Comp2 or M-Sing2,3 M-Sing1 St-Comp1 St-Sing1 St-Comp2 or St-Sing2,3 C C3 C4 CD1 CD2 CD3 CD4 C10 C11 C12 C13 C14 C15 C16C17C18 C19 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 R10 R11 R12 R13 R14 R15 R16 R17 R18 Separation with the buffer is recommended when crosstalk is concerned about. *2) D3.3 R19 Host-I/F I2C: “0”/SPI: “1”
PS No.A2168-26/26 *) BOM for Application Schematics Name Parameter Condition Model Locations Notice Ceramic Capacitor 0.1F 1608 C1, C2, C3, C4, C5, C6, C7, C10, C13, C14, C15, C16, C17, C18, C19 Ceramic Capacitor 10F 3216 C9 Ceramic Capacitor 18pF 1608 C11, C12 The confirmation of the constant for the oscillator and the evaluation request to the oscillator vendor are recommended. Ceramic Capacitor 10nF 1608 C8 Electrolytic Capacitor 47 F DC50V±20% CD1, CD2, CD8, CD9, CD32 Electrolytic Capacitor 4.7 F DC50V±20% CD10, CD11, CD12, CD13, CD14, CD15, CD16, CD17, CD18, CD19, CD20, CD21 The polarity depends on the constitution of other circuits. Electrolytic Capacitor 2.2 F DC50V±20% CD3, CD4, CD5, CD6, CD7, CD22, CD23, CD24, CD25, CD26, CD27, CD28, CD29, CD30, CD31 Chip Resistor 10k 1608 R1, R5, R6, R7, R8, R19 Chip Resistor 30k 1608 R11, R16 Chip Resistor 30k 1608 R12, R15 Chip Resistor 15k 1608 R13, R14 Chip Resistor 15k 1608 R10, R17 Chip Resistor 0 1608 R9, R18 Chip Resistor 100 1608 R2, R4 Chip Resistor 33 1608 R3 Chip Bead MPZ1608R391A 1608 L1 FET NTR2101P Q1 Cristal Oscillator 11.2896MHz 12.288MHz CX8045GA X1 Selectable by System constitution. Notice: *) The locations of the bypass capacitors (C1, C2, C5, C6, C10, C14, C15, C16, C17, C18) must be arranged close to the each LSI pin and in the aspect of the same side as the LC75055PE. *) The location of the Q1 (FET) must be arranged close to the LC75055PE. *) The locations of C7, CD8, C9, and CD9 must be arranged close to the Q1 (FET). *) The length of the Lch and Rch of each Audio input/output wiring same as much as possible is recommended. (It is similar in the case of the length of the +ch and –ch of each differential input/output.) Device Package Shipping (Qty / Packing) LC75055PE-6158-H QIP100E(14X20) (Pb-Free / Halogen Free) 50 / Tray Foam ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use a s components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and dis tributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personali n j u r yo r death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture oft h e part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.