LC72725KV

60612HK 20060913-S00003/83006HKIM 20060822-S00002,20060823-S00002 No.A0503-1/9

Document overview

• PDF pages: 9

Technical content

60612HK 20060913-S00003/83006HKIM 20060822-S00002,20060823-S00002 No.A0503-1/9 http://onsemi.com Semiconductor Components Industries, LLC, 2013 June, 2013 LC72725KV Overview The LC72725KV is IC that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RBDS (Radio Broadcast Data System) standard. This IC include band-pass filter, demodulator, and data buffer on chip. RDS data can be read out from this on-chip memory by external clock input in slave operation mode. Functions

• Bandpass filter: Switched capacitor filter (SCF)
• RDS Demodulation: 57KHz carrier and RDS data clock regeneration, biphase decode, differential decode.
• Buffer: 128 bit (about 100ms) can be restored in the on-chip data buffer RAM.
• Data output: Master or slave output mode can be selected.
• RDS-ID: Detect RDS signal which can be reset by RST signal input.
• Standby control: Crystal oscillator can be stopped.
• Fully adjustment free
• Low Voltage Specifications Absolute Maximum Ratings at Ta = 25°C, VSSd = VSSa = 0V Parameter Symbol Pin Name Conditions Ratings Unit Maximum supply voltage V DD max V DDd, VDDa * V DDa≤VDDd+0.3V -0.3 to +6.5 V Maximum input voltage V IN1 max TEST, MODE, XIN, RDCL, RST -0.3 to VDDd+0.3 V VIN2 max MPXIN, CIN -0.3 to VDDa+0.3 V Maximum output voltage V O1 max RDS-ID(READY) -0.3 to +6.5 V VO2 max XOUT, RDDA, RDCL -0.3 to VDDd+0.3 V VO3 max FLOUT -0.3 to VDDa+0.3 V Maximum output current I O1 max XOUT, FLOUT, RDDA, RDCL +2.0 mA IO2 max RDS-ID(READY) +8.0 mA * VDDa≤VDDd+0.3V Continued on next page. CMOS IC RDS(RBDS) Demodulation IC

No.A0503-2/9 Continued from preceding page. Parameter Symbol Pin Name Conditions Ratings Unit Allowable power dissipation Pd max Ta ≤85°C 100 mW Operating temperature Topr1 V DD = 2.7V to 5.5V -20 to +70 °C Topr2 V DD = 3.0V to 5.5V -40 to +85 °C Storage temperature Tstg -40 to +125 °C Allowable Operating Ranges at Ta = -20 to +70°C, VSSd = VSSa = 0V, VDDd = VDDa = 2.7V to 5.5V Ta = -40 to +85°C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V Parameter Symbol Pin Name Conditions Ratings unit min typ max Supply voltage V DD1 V DDd, VDDa Ta = -20 to +70 °C 2.7 5.5 V VDD2 V DDd, VDDa Ta = -40 to +85 °C 3.0 5.5 Input high-level voltage V IH1 TEST, MODE, RST 0.7VDDd 6 . 5 V VIH2 RDCL 0.7VDDd V DDdV Input low-level voltage V IL TEST, MODE, RST, RDCL 0 0.3V DDdV Output voltage V O1 RDDA, RDCL V DDdV VO2 RDS-ID(READY) 6.5 V Input amplitude V IN MPXIN f = 57 ±2kHz 1.6 50 mVrms VXIN XIN 400 1500 mVrms Guaranteed crystal oscillator frequencies Xtal XIN, XOUT CI ≤120Ω 4.332 MHz Crystal oscillator operating range TXtal XIN, XOUT Fo = 4.332MHz ±100 ppm RDCL setup time tCS RDCL, RDDA 0 μs RDCL high-level time tCH RDCL 0.75 μs RDCL low-level time tCL RDCL 0.75 μs Data output time tDC RDCL, RDDA 0.75 μs READY output time tRC RDCL, READY 0.75 μs READY low-level time tRL READY 107 ms Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Oper ating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No.A0503-3/9 Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Pin Name Conditions Ratings unit min typ max Input resistance Rmpxin MPXIN-V SSa f = 57kHz 100 k Ω Rcin CIN-V SSa f = 57kHz 100 k Ω Internal feedback resistance Rf XIN 1.0 M Ω Center frequency fc FLOUT 56.5 57.0 57.5 kHz -3dB band width BW-3dB FLOUT 2.5 3.0 3.5 kHz Gain Gain MPXIN-FLOUT f = 57kHz 28 31 34 dB Stop band attenuation Att1 FLOUT Δf = ±7kHz 30 dB Att2 FLOUT F<45kHz, f>70kHz 40 dB Att3 FLOUT F<20kHz 50 dB Reference voltage output Vref Vref V DDa = 3V 1.5 V Hysteresis VHIS TEST, MODE, RST, RDCL 0.1VDDd V Output low-level voltage V OL1 RDDA, RDCL I = 2mA 0.4 V VOL2 RDS-ID(READY) I = 8mA 0.4 V Output high-level voltage V OH RDDA, RDCL I = 2mA VDDd-0.4 V Input high-level current I IH1 TEST, MODE, RST, RDCL VI = 6.5V 5.0 μA IIH2 XIN V I = VDDd 2.0 11 μA Input low-level current I IL1 TEST, MODE, RST, RDCL VI = 0V 5.0 μA IIL2 XIN V I = 0V 2.0 11 μA Output off leakage current IOFF RDS-ID(READY) V O = 6.5V 5.0 μA Current drain I DD V DDd+VDDa V DDd+VDDa (VDDd = VDDa = 3V) 5 mA Package Dimensions unit : mm (typ) 3178B SANYO : SSOP16(225mil) 5.2 4.4 6.4 0.22 0.65 (0.33) 916 0.5 0.15 1.5max 0.1 (1.3)

No.A0503-4/9 Pin Assignment Block Diagram LC72725KV Top view 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 XOUT TEST CIN FLOUT VSSa VDDa MPXIN VREF RDS-ID/READY RDCL RDDA RST MODE VDDd XIN VSSd REFERENCE VOLTAGE CIN FLOUT VREF VREF ANTIALIASING FILTER 57kHz BPF (SCF) SMOOTHING FILTER MPXIN +3V VDDa VSSa PLL (57kHz) CLOCK RECOVERY (1187.5Hz) +3V VDDd RDS-ID/ READY RST VSSd DATA DECODER XOUTXIN TEST TEST CLK(4.332MHz) OSC RAM (128bit) RDDA RDCL RDS-ID DETECT MODE

No.A0503-5/9 Pin Descriptions Pin No. Pin Name I/O Function Pin Circuit

3 VREF Output Reference voltage output (Vdda/2)

4 MPXIN Input Baseband (multiplexed) signal input

7 FLOUT Output Subcarrier output (filter output)

8 CIN Input Subcarrier input (comparator input)

5 V DDa - Analog system power supply (+3V)

6 V SSa - Analog system ground

14 XOUT Output Crystal oscillator output (4.332MHz)

13 XIN Input Crystal oscillator input

(external reference signal input)

9 TEST Test input

10 MODE Read out mode (0:master, 1:slave)

15 RST RDS-ID/RAM reset (active high)

2 RDDA Output RDS data output

16 RDCL I/O RDS clock output (master mode) /

RDS read out clock input (slave mode)

1 RDS-ID/

Output RDS reliability data output (High:data with high RDS reliability Low: data with low RDS reliability) READY output (active high)

12 V DDd - Digital system power supply (+3V)

11 V SSd - Digital system ground

S VSSd VSSd VDDd VSSd S VSSd VDDd

No.A0503-6/9 Input/Output Data Format TEST MODE Circuit Operation Mode RDCL Pin RDS-ID/READY Pin 0 0 Master read out mode Cl ock output RDS-ID output 0 1 Slave read out mode Clock input READY output 1 0 Standby mode (crystal oscillator stopped) - - 1 1 IC test mode which is not available to user applications. - - RST Pin RST = 0 Normal operation RST = 1 RDS-ID • demodulation circuit clear + READY • memory clear (when slave mode) RDS-ID/READY Pin Master mode RDS-ID output (Active-high) Slave mode READY output (Active-high) Note: RDS-ID(READY) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data. RDCL/RDDA Output Timing in Master Mode RDS-ID Output Timing Note: RDS-ID is High: data with high RDS reliability, Low: data with low RDS reliability 421μs 421 μs 17μs 17 μs Tp1 Tp2 RDCL output RDDA output RDDA RDCL High/Low High/Low High/Low High/Low High/Low High/Low High/Low RDS-ID

No.A0503-7/9 RST Operation in Master Mode Note: RDCL and RDDA outputs keep high level after input of RST until RDS detection circuit output is detected. RDCL Operation in Slave Mode Parameter Symbol Pin Name Conditions Ratings unit min typ max RDCL setup time tCS RDCL,RDDA 0 μs RDCL high-level time tCH RDCL 0.75 μs RDCL low-level time tCL RDCL 0.75 μs Data output time tDC RDCL,RDDA 0.75 μs READY output time tRC RDCL,READY 0.75 μs READY high-level time tRH READY 107 ms RDCL RDDA RDSdetection circuit output (IC internal) RST Tp3≥250ns RDDA RDCL READY tCH tCLtCS tCStDC tRC tRH ≈≈≈

No.A0503-8/9 Notes: 1. RDCL input must be started after READY signal goes high. When READY signal is low, RDCL must be low level. 2. READY status must be checked after tRC time from RDCL is set low. If the READY status is high, then next read cycle can be continued. If the READY status is low, next RDCL clock input must be stopped. 3. If the above condition is satisfied, RDS data (RDDA) can be read out at both rising and falling edge of RDCL. 4. READY signal goes low after the last data is read out from on-chip memory. If one RDS data is stored in the memory, READY signal goes high again. 5. When the reception channel is changed, a memory and READY reset must be applied using RST input. If a reset is not applied, reception data from the previous channel may remain in memory. If RST input is applied, reception data is not stored in memory until the first RDS-ID is detected, and READY output goes high after the first RDS-ID is detected. After the first RDS-ID is detected, reception data is stored even if RDS-ID is not detected. 6. The readout mode may be switched between master and slave modes during readout. Applications must observe the following points to assure data continuity during this operation. 1) Data acquisition timing in master made Data must be read on the falling edge of RDCL 2) Timing of the switch from master mode to slave mode After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE high immediately. Then, the microcontroller starts output by setting the RDCL signal low. The microcontroller RDCL output must start within 840μs (tms) after RDCL went low. In this case, if the last data read in master mode was data item n, then data starting with item n+1 will be written to memory. 3) Timing of the switch from slave mode to master mode After all data has been read from memory and READY has gone high, the application must then wait until READY goes low once again the next time (timing A in the figure), immediately read out one bit of data and input the RDCL clock. Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set MODE low. The application must switch MODE to low within 840μs (tms) after READY goes low (timing A in the figure). n n+1n-1n-2 m m+1 m+2 Timing A tms tsm INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT RDCL (microcontroller status) RDCL (IC status) RDCL MODE READY RDDA undefined

No.A0503-9/9 Sample Application Connection Circuit (for master mode operation) Note: If the RST pin is unused, it must be connected to ground. PS XOUT TEST VSSd RDCL RST XIN MODE RST RDCLRDSID/READY 4.332MHz VSSd 22pF VSSd 22pF CIN FLOUT VSSa VSSa VDDa VDDa + 3 μF VSSa MPXIN MPXIN 560pF 0.1μF 330pF VREF VSSd VDDd 12 VSSd 0.1μF VDDd VDDd 10kΩ RDSID/READY RDDARDDA ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s techn ical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC productsfor any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, anddistributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture oft h e part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.