LC71F7001PVBS0 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Detection System: 14 Electrostatic Capacitance Sensors Single/Differential Input, Differential Capacitance Value Output. By the Use of Multiple (Up to 8) LC71F7001PVB Capacitance Digital Converter LSI, They Can Increase the Number of the Input
- Input Capacitance Resolution: Less than 1 fF.
- Measurement Time (14 Single Inputs): 0.84 ms (high-speed mode: fCDRV = 200 kHz, OSR = 4) to 107.5 ms (high-resolution mode: fCDRV = 200 kHz, OSR = 512) OSR: Oversampling Ratio
- External Components: Not Required
- On-chip Calibration: Function for Removing Environmental Factors
- Built-in EEPROM: For Storing Calibration Data, EEPROM Rewriting Times 10000 Cycles, EEPROM Data Retention Time 20 years
- Interface: I2C Serial Interface Compatible
- Low Power Consumption: Typ 10 /C0109A (during intermittent operation) to Typ 0.8 mA (during continuous operation).
- Supply V oltage: 2.6 V to 3.6 V Typical Applications
- Consumer: Home Appliance, Digital Cameras
- Industrial: Remote Controllers
- Computing: Cell Phones, Portable Devices, Game Machines www.onsemi.com SSOP24 (225 mil) CASE 565AR MARKING DIAGRAM See detailed ordering and shipping information on page 36 of this data sheet.
ORDERING INFORMATION
XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data XXXXXXXXXX YMDDD
Table 1. ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS = 0 V) should not be assumed, damage may occur and reliability may be affected. Table 2. RECOMMENDED OPERATING CONDITIONS the Recommended Operating Ranges limits may affect device reliability.
Table 3. ELECTRICAL CHARACTERISTICS
0.7 AVDD V (Note 4)
0.3 AVDD
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- Design guarantee values (not tested before shipment).
- Measurements conducted using the test mode in the LSI.
- Maximum output of 3 mA for each port (GPO/C DRV/CDRVX/CDRVY/CDRVB/INT), total output are 9 mA maximum.
Table 4. I2C COMPATIBLE BUS INTERFACE TIMING CHARACTERISTICS performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- Design guarantee values (not tested before shipment).
Figure 1. I2C Bus Timing Definition (FAST-MODE: 400 kHz)
- The SCL and SDA lines are easily subject to noise. They must be connected with lines that are as short as possible.
Figure 2. Simplified Block Diagram
Figure 3. Pin Assignment (Top View) Table 5. PIN ASSIGNMENT
1 CIN0/GPO0/CDRVY
2 CIN1/GPO1/CDRVY
3 No Connect
4 CIN2/GPO2/CDRVY
5 CIN3/GPO3/CDRVY
6 CIN4/GPO4/CDRVY
7 CIN5/GPO5/CDRVY
8 CIN6/GPO6/CDRVX
9 No Connect
10 CIN7/GPO7/CDRVX
11 CIN8/GPO8/CDRVX
12 CIN9/GPO9/CDRVX
13 CIN10/GPO10/CDRVX
14 CIN11/GPO11/CDRVX
15 TEST (Note 8)
16 CIN12/GPO12/CREF/CDRVX
17 CIN13/GPO13/INT/CDRVB/CDRVX
18 SDA
19 SCL
20 DVDD
21 No Connect
22 VSS
23 AVDD
24 CDRV/INT
- Must be connected to V SS when mounted.
Table 6. PIN FUNCTION
Table 6. PIN FUNCTION (continued)
Table 8. CONTROL REGISTER 12.When RUN is set to 1, do not write a register value other than RUN = 0 (standby). Table 9. CONFIGURATION REGISTER 1
13.The optimum frequency varies depending on the sensor load. Table 10. CONFIGURATION REGISTER 2 is automatically stored in the CIN Static Offset Registers.
0 When the first valid data is established after measurement is started. When offset calibration is completed. When a dynamic offset calibration overflow occurs. times specified in the INT Count Register (operations detected). When a dynamic offset calibration overflow occurs. 16.Assume that the moving average count specified in AVG0−AVG1 is N (= 1, 2, 4, 8). When the number of measurement times is under N, the following averaging data is output. When the number of measurement times is N or more, the following averaging data is output. Table 11. GPO CONTROL REGISTER 1 Table 12. GPO CONTROL REGISTER 2
Table 13. INT STATUS REGISTER 1 Table 14. INT STATUS REGISTER 2 17.Reading the INT Status Register 2 in byte units clears the interrupt outputs and the interrupt status flags. When the INT Status Register 2 is read in sequential order, the interrupt outputs and interrupt status flags are not cleared. Table 15. DATA00 REGISTER TO DATA27 REGISTER to 0x52) + CIN Dynamic Offset Registers (0x53 to 0x66) in two’s complement number.
Table 16. EEPROM WRITE PROTECT/INITIALIZE REGISTER 18.Be sure to perform writes to this register in the order of 0x01 → 0x00 → 0x01 during power-on-time initialization. Table 17. FIRST FIXED REGISTER 19.Be sure to write a 0x00 into this register when using the LSI. The LSI will not run normally with any value other than 0x00.
Table 18. CONTROLLER I2C SLAVE ADDRESS REGISTER Table 19. CIN0−CIN1: CONFIGURATION REGISTER 1 20.In the differential input mode, CIN0EN and CIN1EN must be set to 0 or 1 at the same time (setting them to 01 and 10 is prohibited). Table 20. CIN0−CIN1: CONFIGURATION REGISTER 2 factors is compensated using dynamic computation. 21.In the differential input mode, OFFCALD0 and OFFCALD1 must be set to 0 or 1 at the same time (setting them to 01 and 10 is prohibited).
time after capacitance is detected. 22.In the differential input mode, the standard GPO mode cannot be used. 0: Disables operation detection interrupts. 1: Enables operation detection interrupts. 23.In the differential input mode, INT0EN and INT1EN must be set to 0 or 1 at the same time (setting them to 01 and 10 is prohibited). Table 21. CIN12−CIN13: CONFIGURATION REGISTER 1
24.In the differential input mode, CIN12EN and CIN13EN must be set to 0 or 1 at the same time (setting them to 01 and 10 is prohibited). 25.Any value combinations other than those listed above are not allowed. Table 22. CIN12−CIN13: CONFIGURATION REGISTER 2 factors is compensated by dynamic computation. 26.In the differential input mode, OFFCALD12 and OFFCALD13 must be set to 0 or 1 at the same time (setting them to 01 and 10 is prohibited). interval time after capacitance is detected. 27.n the differential input mode, the standard GPO mode cannot be used. 28.In the differential input mode, INT12EN and INT13EN must be set to 0 or 1 at the same time (setting them to 01 and 10 is prohibited).
Table 23. DATA CENTER REGISTER specified in the Data Center Register are set. 29.In the differential input mode, the offset calibration center value is fixed at ±0. Table 24. SINGLE INT THRESHOLD REGISTER This register determines the threshold value beyond which interrupt occurs in the single input mode. interrupt generation flag in the INT Status Register 1, 2 is then set.
Table 25. DIFFERENTIAL INT THRESHOLD REGISTER This register determines the threshold value beyond which positive side interrupt occurs in the differential input mode. range in the differential input mode has occurred continuously for the number of times specified in the INT Count Register. The interrupt generation flag in the INT Status Register 1, 2 is then set. Table 26. INT COUNT REGISTER continuously for the number of times specified in the INT Count Register. Table 27. CIN0 GAIN REGISTER
www.onsemi.com Gain A3 Gain A2 Gain A1 Gain A0 Cf (fF) 0 0 0 0 1600 (minimum gain setting) 0 0 0 1 1500 0 0 1 0 1400 0 0 1 1 1300 0 1 0 0 1200 0 1 0 1 1100 0 1 1 0 1000 0 1 1 1 900 1 0 0 0 800 1 0 0 1 700 1 0 1 0 600 1 0 1 1 500 1 1 0 0 400 1 1 0 1 300 1 1 1 0 200 1 1 1 1 100 (maximum gain setting) CIN0 (1−13) Subsequent stage amplifier gain settings Gain B3 Gain B2 Gain B1 Gain B0 Gain (Times) 0 0 0 0 1 (minimum gain setting) 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 16 (maximum gain setting) CIN1 Gain Register (Address 0x39) => The contents are the same as those in the C IN0 Gain Register. The value of CIN0 Gain Register is valid in the differential input mode. CIN2 Gain Register (Address 0x3A) => The contents are the same as those in the C IN0 Gain Register. CIN3 Gain Register (Address 0x3B) => The contents are the same as those in the C IN0 Gain Register. The value of CIN2 Gain Register is valid in the differential input mode. CIN4 Gain Register (Address 0x3C) => The contents are the same as those in the C IN0 Gain Register. CIN5 Gain Register (Address 0x3D) => The contents are the same as those in the C IN0 Gain Register. The value of CIN4 Gain Register is valid in the differential input mode. CIN6 Gain Register (Address 0x3E) => The contents are the same as those in the C IN0 Gain Register. CIN7 Gain Register (Address 0x3F) => The contents are the same as those in the C IN0 Gain Register. The value of CIN6 Gain Register is valid in the differential input mode.
CIN8 Gain Register (Address 0x40) => The contents are the same as those in the C IN0 Gain Register. CIN9 Gain Register (Address 0x41) => The contents are the same as those in the C IN0 Gain Register. The value of CIN8 Gain Register is valid in the differential input mode. CIN10 Gain Register (Address 0x42) => The contents are the same as those in the C IN0 Gain Register. CIN11 Gain Register (Address 0x43) => The contents are the same as those in the C IN0 Gain Register. The value of CIN10 Gain Register is valid in the differential input mode. CIN12 Gain Register (Address 0x44) => The contents are the same as those in the C IN0 Gain Register. CIN13 Gain Register (Address 0x45) => The contents are the same as those in the C IN0 Gain Register. The value of CIN12 Gain Register is valid in the differential input mode. Table 28. CIN0 CDAC OFFSET POS REGISTER capacitance DA converter. The contents of this register are automatically updated by the static offset calibration command. Table 29. CIN0 CDAC OFFSET NEG REGISTER capacitance DA converter. The contents of the register are automatically updated by the static offset calibration command.
Table 30. CIN0 STATIC OFFSET REGISTER The contents of this register are automatically updated by the static offset calibration command.
CIN1 Static Offset Register (Address 0x63) => The contents are the same as those in the C IN0 Static Offset Register. CIN2 Static Offset Register (Address 0x64) => The contents are the same as those in the C IN0 Static Offset Register. CIN3 Static Offset Register (Address 0x65) => The contents are the same as those in the C IN0 Static Offset Register. CIN4 Static Offset Register (Address 0x66) => The contents are the same as those in the C IN0 Static Offset Register. CIN5 Static Offset Register (Address 0x67) => The contents are the same as those in the C IN0 Static Offset Register. CIN6 Static Offset Register (Address 0x68) => The contents are the same as those in the C IN0 Static Offset Register. CIN7 Static Offset Register (Address 0x69) => The contents are the same as those in the C IN0 Static Offset Register. CIN8 Static Offset Register (Address 0x6A) => The contents are the same as those in the C IN0 Static Offset Register. CIN9 Static Offset Register (Address 0x6B) => The contents are the same as those in the C IN0 Static Offset Register. CIN10 Static Offset Register (Address 0x6C) => The contents are the same as those in the C IN0 Static Offset Register. CIN11 Static Offset Register (Address 0x6D) => The contents are the same as those in the C IN0 Static Offset Register. CIN12 Static Offset Register (Address 0x6E) => The contents are the same as those in the C IN0 Static Offset Register. CIN13 Static Offset Register (Address 0x6F) => The contents are the same as those in the C IN0 Static Offset Register. Table 31. CIN0 DYNAMIC OFFSET REGISTER /C0083/C0068 A/D converter data. The contents of this register are automatically updated by the dynamic offset calibration command.
www.onsemi.com CIN1 Dynamic Offset Register (Address 0x71) => The contents are the same as those in the C IN0 Dynamic Offset Register. The value of C IN0 Dynamic Offset Register is valid in the differential input mode. CIN2 Dynamic Offset Register (Address 0x72) => The contents are the same as those in the C IN0 Dynamic Offset Register. CIN3 Dynamic Offset Register (Address 0x73) => The contents are the same as those in the C IN0 Dynamic Offset Register. The value of CIN2 Dynamic Offset Register is valid in the differential input mode. CIN4 Dynamic Offset Register (Address 0x74) => The contents are the same as those in the C IN0 Dynamic Offset Register. CIN5 Dynamic Offset Register (Address 0x75) => The contents are the same as those in the C IN0 Dynamic Offset Register. The value of C IN4 Dynamic Offset Register is valid in the differential input mode. CIN6 Dynamic Offset Register (Address 0x76) => The contents are the same as those in the C IN0 Dynamic Offset Register. CIN7 Dynamic Offset Register (Address 0x77) => The contents are the same as those in the C IN0 Dynamic Offset Register. The value of C IN6 Dynamic Offset Register is valid in the differential input mode. CIN8 Dynamic Offset Register (Address 0x78) => The contents are the same as those in the C IN0 Dynamic Offset Register. CIN9 Dynamic Offset Register (Address 0x79) => The contents are the same as those in the C IN0 Dynamic Offset Register. The value of C IN8 Dynamic Offset Register is valid in the differential input mode. CIN10 Dynamic Offset Register (Address 0x7A) => The contents are the same as those in the C IN0 Dynamic Offset Register. CIN11 Dynamic Offset Register (Address 0x7B) => The contents are the same as those in the C IN0 Dynamic Offset Register. The value of C IN10 Dynamic Offset Register is valid in the differential input mode. CIN12 Dynamic Offset Register (Address 0x7C) => The contents are the same as those in the C IN0 Dynamic Offset Register. CIN13 Dynamic Offset Register (Address 0x7D) => The contents are the same as those in the C IN0 Dynamic Offset Register. The value of C IN12 Dynamic Offset Register is valid in the differential input mode.
Table 32. DYNAMIC OFFSET THRESHOLD REGISTER Table 33. DYNAMIC OFFSET LPF/IVAL REGISTER the value in the Data Center Register.
Table 34. DRIVE X SCAN REGISTER This register is used to configure X drive scanning when the TPDRV bit in the register 0x02 is enabled. Table 35. DRIVE Y SCAN REGISTER This register is used to configure Y drive scanning when the TPDRV bit in the register 0x02 is enabled. Table 36. RESERVED REGISTER 1 Normally, 0x00 must be written into this register and used.
Table 37. CDRV FREQUENCY VARIABLE REGISTER FSEL0−FSEL3 C DRV drive frequency adjustment. Normally, 0x7 must be written into this register and used. recommended operating ranges and electrical characteristics are only reference values, and no guarantees are made for these values.
Table 38. REGISTER MAP
Table 38. REGISTER MAP (continued)
32.Registers with the shading are ones that are automatically updated by auto offset calibration.
Figure 10. Operation Sequence when a Multiple Number of LC71F7001PVB is Used into bit 0 of address 0x00) during measurement interval time. stopped or during measurement interval time.
- The example when 3 chips (chip 1, chip 2 and chip
3) are used is explained as follows.
- Bit 5 of the 0x00 Control Register of chip 2 and
- The chip 1 measurements are started. After an
- Bit 5 of the 0x00 Control Register of chip 1 is set
- Bit 5 of the 0x00 Control Register of chip 2 is set
data is then read from chip 2.
- Bit 5 of the 0x00 Control Register of chip 2 is set
- Bit 5 of the 0x00 Control Register of chip 3 is set
data is then read from chip 3.
www.onsemi.com PACKAGE DIMENSIONS SSOP24 (225mil) CASE 565AR ISSUE A SOLDERING FOOTPRINT* NOTE: The measurements are not to guarantee but for reference only. (Unit: mm) *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 1.0 5.80 0.32 0.50 Unit: mm
Table 39. ORDERING INFORMATION Specifications Brochure, BRD8011/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries i n the United States and/or other countries. laws and is not for resale in any manner. I2C Bus is a trademark of Philips Corporation.