LC717A00AJ_17 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Detection System: Differential Capacitance Detection (Mutual Capacitance Type)
- Input Capacitance Resolution: Can Detect Capacitance Changes in the Femto Farad Order
- Measurement Interval (8 Differential Inputs): ♦ 18 ms (Typ) (at Initial Configuration) ♦ 3 ms (Typ) (at Minimum Interval Configuration)
- External Components for Measurement: Not Required
- Current Consumption: ♦ 320 /C0109A (Typ) (VDD = 2.8 V) ♦ 740 /C0109A (Typ) (VDD = 5.5 V)
- Supply V oltage: 2.6 V to 5.5 V
- Detection Operations: Switch
- Interface: I2C Compatible Bus or SPI Selectable www.onsemi.com SSOP30 (225 mil) CASE 565AZ MARKING DIAGRAM See detailed ordering and shipping information on page 11 of this data sheet.
ORDERING INFORMATION
XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data XXXXXXXXXX YMDDD
Table 1. ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS = 0 V) should not be assumed, damage may occur and reliability may be affected.
- Apply to Cin0 to 7, Cref, nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN.
- Apply to Cdrv, Pout0 to 7, SDA, SO, ERROR, INTOUT.
Table 2. RECOMMENDED OPERATING CONDITIONS the Recommended Operating Ranges limits may affect device reliability.
- Inserting a high-valued capacitor and a low-valued capacitor in parallel between V
capacitor should be at least 0.1 /C0109F, and is mounted near the LSI. Table 3. ELECTRICAL CHARACTERISTICS (VSS = 0 V, VDD = 2.6 to 5.5 V, TA = −40 to +105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143 kHz.
Table 3. ELECTRICAL CHARACTERISTICS (continued) (VSS = 0 V, VDD = 2.6 to 5.5 V, TA = −40 to +105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 143 kHz.
0.8 VDD − − V (Note 9)
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- Design-guaranteed values (not tested before shipment).
- Measurements conducted using the test mode in the LSI.
- Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN.
- Apply to Cdrv, Pout0 to 7, SO, ERROR, INTOUT.
10.Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN.
Table 4. I2C COMPATIBLE BUS TIMING CHARACTERISTICS performance may not be indicated by the Electrical Characteristics if operated under different conditions.
- Design-guaranteed values (not tested before shipment).
Table 5. SPI BUS TIMING CHARACTERISTICS performance may not be indicated by the Electrical Characteristics if operated under different conditions. 12.Design-guaranteed values (not tested before shipment).
Figure 8. Simplified Block Diagram
Figure 9. Pin Assignment (Top View) Table 7. PIN ASSIGNMENT
1 VDD 16 Cref
2 VSS 17 ERROR
3 Non Connect (Note 13) 18 Cdrv
4 Cin4 19 INTOUT
5 Cin5 20 GAIN
6 Cin6 21 SCL/SCK
7 Cin7 22 SDA/SI
8 Pout0 23 SA/SO
9 Pout1 24 nCS
10 Pout2 25 nRST
11 Pout3 26 Non Connect (Note 13)
12 Pout4 27 Cin0
13 Pout5 28 Cin1
14 Pout6 29 Cin2
15 Pout7 30 Cin3
13.Connect to GND when mounted.
Table 8. PIN FUNCTION
Table 8. PIN FUNCTION (continued) capacitor should be at least 0.1 /C0109F, and is mounted near the LSI. 15.When VSS terminal is not grounded in battery-powered mobile equipment, detection sensitivity may be degraded. doing so, Cdrv and Cin patterns are capacitively coupled. pattern as 8-bit digital data. to detect the capacitance change correctly. being measured are all in “Low” condition. Leave the unused terminals open. connecting any capacitance between this pin and Cdrv pin. detect capacitance change in each Cin pin correctly. a “Low” depending on the result. so that they are capacitively coupled. a measurement process is completed. Leave the terminal open if not in used. If interface is not to be used, fix the pin to “High”. a communication terminal on board is still recommended.
minimum setting when GAIN pin is “High”. Interface selection/Chip-select-inverting input (SPI). until LSI is again initialized. If interface is not to be used, fix the pin to “High”. nRST pin is “Low”, LSI is in the reset state. input pin of the SPI depending on the mode of operation. If interface is not to be used, fix the pin to “High”. a communication terminal on board is still recommended. If interface is not to be used, fix the pin to “High”. a communication terminal on board is still recommended. Table 9. ORDERING INFORMATION Specifications Brochure, BRD8011/D.
www.onsemi.com PACKAGE DIMENSIONS SSOP30 (225 mil) CASE 565AZ ISSUE A SOLDERING FOOTPRINT* NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (Unit: mm) 5.80 0.32 1.00 0.50
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