LC709004A

Features

Document overview

• PDF pages: 13

Technical content

Features

• 4-/5-wire synchronous serial transmission and reception, and 16-bit parallel I/O
• Wide operating voltage range (2.0V to 6.0V)
• Multifunction I/O ports - I/O direction specification: Bit units - CMOS or Nch-OD output type specification: Bit units - Output voltage adjustment: Port (8 bits) units
• Output current: 12mA max. (capable of driving a green LED directly)
• Data transmission and reception: Can control reception of input data and transmission of output data in parallel.
• Cascaded configuration: Ports can be expanded in units of 16 bits × n (n is the number of LSI chips).
• Packaging from: MFP24S (300mil): lead-free type (discontinued) MFP24SJ (300mil): lead-free type CMOS IC I/O-Expander for Microcontroller

No.A0165-2/13 Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Symbol Pin/Remarks Conditions Ratings Unit VDD[V] min typ max Maximum supply voltage V DD max V DD, VDDP1 V DD=VDDP1 -0.3 +7.0 V Input voltage V I RES, CS, DIN, CLK -0.3 V DD+0.3 Output voltage V O DOUT -0.3 V DD+0.3 Input/output voltage V IO(1) Port 0 -0.3 VDDP1 +0.3 VIO(2) Port 1 -0.3 VDDP1 +0.3 High level output current Peak output current IOPH(1 ) Ports 0 to 1 CMOS output selected Per 1 applicable pin mA IOPH(2) DOUT -13 Mean output current (Note 1) IOMH(1) Ports 0 to 1 CMOS output selected Per 1 applicable pin IOMH(2) DOUT -6 Total output current IOP0H Port 0 Total of all applicable pins -32 IOP1H Port 1 Total of all applicable pins -32 IOAH DOUT, ports 0 to 1 Total of all applicable pins -77 Low level output current Peak output current IOPL(1) Ports 0 to 1 Per 1 applicable pin mA IOPL(2) DOUT 13 Mean output current (Note 1) IOML(1) ports 0 to 1 Per 1 applicable pin IOML(2) DOUT 6 Total output current IOP0L Port 0 Total of all applicable pins IOP1L Port 1 Total of all applicable pins IOAL DOUT, ports 0 to 1 Total of all applicable pins Power dissipation Pd max (1) MFP24S (300mil) Ta=-30 to +70 °C 177 mW Pd max (2) MFP24SJ (300mil) T.B.D Operating temperature Topr -30 70 Storage temperature Tstg -55 125 Note 1: The mean output current is a mean value measured over 100ms. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Oper ating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No.A0165-3/13 Allowable Operating Conditions at Ta = -30 to +70°C, VSS = 0V Parameter Symbol Pin/Remarks Conditions Specification (Note 3) Unit VDD[V] min typ max Operating supply voltage V DD(1) V DD 2.0 6.0 V VDD(2) V DDP1 Supply voltage must be within VDD (1)'s specification. 2.0 to 6.0 V DD-3.0 V DD High level input voltage V IH(1) DIN, ports 0 to 1 4.5 to 6.0 0.3V DD+0.7 V DDPx VIH(2) DIN, ports 0 to 1 2.0 to 6.0 0.3V DD+0.7 V DDPx VIH(3) RES, CS, CLK 4.5 to 6.0 0.4V DD+0.7 V DD VIH(4) RES, CS, CLK 2.0 to 6.0 0.4V DD+0.7 V DD Low level input voltage V IL(1) DIN, ports 0 to 1 4.5 to 6.0 V SS 0.2V DD+0.1 VIL(2) DIN, ports 0 to 1 2.0 to 6.0 V SS 0.2V DD+0.1 VIL(3) RES, CS, CLK 4.5 to 6.0 V SS 0.1V DD+0.2 VIL(4) RES, CS, CLK 2.0 to 6.0 V SS 0.1V DD+0.2 Note 3: VDDPx denote the power supply pin (VDDP1) for port pins. Electrical Characteristics at Ta = -30 to +70°C, VSS = 0V Parameter Symbol Pin/Remarks Conditions (Note 3) Ratings Unit VDD[V] V DDPx[V] min typ max High level input current IIH RES, CS, CLK, Ports 0 to 1 VIN=VDD (including output Tr. off leakage current) 2.0 to 6.0 10 μA Lower level input current IIL RES, CS, CLK, Ports 0 to 1 VIN=VSS (including output Tr. off leakage current) 2.0 to 6.0 -10 High level output voltage V VOH(7) DOUT I OH=-5mA 4.5 to 6.0 V DDPx-0.5 VOH(8) I OH=-10mA 4.5 to 6.0 V DDPx-1.0 VOH(9) I OH=-2mA 2.0 to 6.0 V DDPx-0.5 Lower level output voltage VOL(2) I OL=12mA 4.5 to 6.0 2.0 to 6.0 1 VOL(5) I OL=12mA 4.5 to 6.0 4.5 to 6.0 1 VOL(7) DOUT I OL=5mA 4.5 to 6.0 0.4 VOL(8) I OL=10mA 4.5 to 6.0 1 VOL(9) I OL=2mA 2.0 to 6.0 0.4 Pull-up resistance Rpu(1) CS VOH=VSS 4.5 to 6.0 100 230 650 k Ω Voltage hysteresis VHIS RES, CS, CLK 2.0 to 6.0 0.1V DD V Consumption current (operation stopped) IDDSP V DD=VDDP1 RES=CS=VDD CLK=DIN=VDD or VSS DOUT=open P0 to P1=open or VDD or VSS (Note 2) 2.0 to 6.0 20 μA Pin capacity CP All pins Other than test pin VIN=VSS f=1MHz Ta=25°C 2.0 to 6.0 10 pF Note 2: The consumption current does not include the current flowing into the port's output transistor. Note 3: VDDPx denote the power supply pin (VDDP1) for port pins.

No.A0165-4/13 Switching I/O Characteristics at Ta=-30 to +70°C, VDD=VDDP1, VSS=0V Parameter Symbol Pin/Remarks Conditions Specification (Note 3) Unit VDD[V] min typ max Clock setup time TsCLK CS, CLK •Specified with respect to falling edge of CS.

• See Fig. 8. 2.0 to 6.0 100 ns Chip select low level setup time TslCS CS, CLK •Specified with respect to falling edge of CS.
• See Fig. 8. 2.0 to 6.0 100 Chip select low level hold time ThlCS CS, CLK •Specified with respect to falling edge of CS
• See Fig. 8. 2.0 to 6.0 100 Clock hold time ThCLK CS, CLK •Specified with respect to falling edge of CS.
• See Fig. 8. 2.0 to 6.0 200 Clock low level pulse width TwlCLK CLK •See Fig. 8. 4.5 to 6.0 250 2.7 to 6.0 500 2.0 to 6.0 1000 Clock high level pulse width TwhCLK CLK •See Fig. 8. 4.5 to 6.0 250 2.7 to 6.0 500 2.0 to 6.0 1000 Chip select high level setup time TshCS CS, RES •See Fig. 8. 2.0 to 6.0 200 Chip select high level hold time ThhCS CS, RES •See Fig. 8. 2.0 to 6.0 100 Chip select low level pulse width TwlCS CS, RES •See Fig. 8. 2.0 to 6.0 200 Reset low level pulse width TwlRES CS, RES •See Fig. 8. 2.0 to 6.0 150 Data setup time TsDIN DIN •Specified with respect to falling edge of CLK
• See Fig. 8. 4.5 to 6.0 30 2.0 to 6.0 50 Data hold time ThDIN DIN •Specified with respect to falling edge of CLK.
• See Fig. 8. 4.5 to 6.0 50 2.7 to 6.0 150 2.0 to 6.0 300 Serial data output delay time (Note 4) TdD0UT DOUT •Specified with respect to falling edge of CLK.
• See Fig. 8. 4.5 to 6.0 200 2.7 to 6.0 400 2.0 to 6.0 800 Port data output delay time TdPOUT Port 0 to 1 •Specified with respect to rising edge of CS.
• See Fig. 8. 4.5 to 6.0 200 2.7 to 6.0 400 2.0 to 6.0 800 Port data input setup time TsPIN Port 0 to 1 •Specified with respect to rising edge of CLK.
• See Fig. 8. 4.5 to 6.0 30 2.0 to 6.0 50 Port data input hold time ThPIN Port 0 to 1 •Specified with respect to rising edge of CLK.
• See Fig. 8. 4.5 to 6.0 50 2.7 to 6.0 150 2.0 to 6.0 300 Note 4: The input data of P00 will be out from DOUT terminal at the first negative edge of CLK signal. Because of this, Serial data output delay time of the first clock will be the time measured from the negative edge of the CLK or the time at the input data (P00) is settled.

No.A0165-5/13 Package Dimensions Package Dimensions unit : mm (typ) unit : mm (typ) 3112B 3419 Pin Assignment MFP24S (300mil): lead-free type/MFP24SJ (300mil): lead-free type SANYO : MFP24S(300mil) 1 12 1324 12.5 0.63 7.6 5.4 0.151.0 0.35 (0.75) 1.7max 0.1 (1.5) DOUT DIN CLK CS VDD RES VSS P17 P16 P15 P14 P13 P00 P01 P02 P03 P04 P05 P06 P07 VDDP1 P10 P11 P12 Top view LC709004A SANYO : MFP24SJ(300mil) 13.0 0.45 8.0 6.0 0.151.0 0.4(1.0)

1.9 MAX

0.1 (1.5)

No.A0165-6/13 Block Diagram Pin Description Pin Name I/O Description I/O Type Reset Time State VSS - • - power supply pin VDD VDDP1 - • + power supply pin

• VDD is the power supply pin for blocks other than I/O ports (P00 to P17).
• VDDP1 is the power supply pin for port pins P00 to P17. (Notes)
• VDDP1 must not be set higher than VDD (VDDP1≤VDD). Port 0 I/O • 8-bit I/O port
• I/O specifiable in 1 bit units.
• CMOS/Nch-open drain specifiable in 1 bit units.
• Output voltage variable in 1 port units according to VDDP1 voltage. Output: CMOS/Nch-OD Input: TTL Hi-Z P00 to P07 Port 1 I/O • 8-bit I/O port
• I/O specifiable in 1 bit units.
• CMOS/Nch-open drain specifiable in 1 bit units.
• Output voltage variable in 1 port units according to VDDP1 voltage. Output: CMOS/Nch-OD Input: TTL Hi-Z P10 to P17 DIN I • Serial data input pin Input: TTL DOUT O • Serial data output pin Output: CMOS High CLK I • Serial clock input pin
• Port data is placed on DOUT on the falling edge of this clock.
• The data from DIN is latched on the negative-to-positive transition of this clock. Input: TTL Schmidt CS I • Chip select input pin
• Setting this pin to the low level enables serial data to be input or output. Input: TTL Schmidt RES I • Device's system reset input pin
• Setting this pin to the low level initializes the internal control circuit and registers and puts DOUT in the high level and all data port pins (P00 to P17) into the Hi-Z state. Input: TTL Schmidt Port 1 I/O buffer I/O control/output register Serial/parallel converter/shift register Control logic DOUT VDD VSS P17 P10 VDDP1 DIN CLK CS RES Port 0 I/O buffer P07 P00

No.A0165-7/13 Port Output Types and I/O States The output type and I/O states of the LC709004A's ports can be selected by configuring the data direction register (DDR) and data register (DTR). Port data can be taken into the LC709004A only when DDR is set to 0 (Nch-open drain) and DTR is set to 1 (Nch-Tr OFF). The ports are held high for the other settings of DDR and DTR. Port Name DDR DTR Port Output Type Input Output P00 to P07 P10 to P17 0 1 Nch-open drain Enabled Hi-Z 0 0 Nch-open drain Disabled (High) Low 1 1 CMOS Disabled (High) High 1 0 CMOS Disabled (High) Low Port Output Circuit Nch-open drain CMOS Principles of Operation The LC709004A accomplishes data transmission and reception to and from the MCU through synchronous serial communication and performs I/O operations on the extended ports in parallel mode. Its communication modes (MCU to LC709004A by serial to parallel conversion and LC709004A to MCU by parallel to serial conversion) include the initial communication modes (modes 0 and 1) in which the LC709004A initializes itself and the data communication mode in which the LC709004A sends and receives port data. The initial communication modes are used for various communication control purposes for the first time in system operation after a power-on or system reset. In these modes, the LC709004A sets up the I/O mode and output type of the ports. The data communication mode is used for communication control after the end of the initial communication modes. In this mode, the LC709004A carries out actual port I/O operations. The port I/O mode and output type settings are stored in the data direction register (DDR). The data output state settings ("High" output, "Hi-Z" output, or "Low" output) are stored in the data register (DTR). The LC709004A's operating modes are summarized below, followed by detailed mode descriptions. Communication Mode Description Initial communication mode Mode 0 Sets the output type of all ports to "N-ch-open drain." Mode 1 Sets the I/O direction of the ports and the their output type to CMOS or "Nch-open-drain" on a bit basis. Data communication mode Sends and receives port data. VDDP1

No.A0165-8/13 (1) Initial communication modes

• Mode 0 1) Setting the RES pin to the low level initializes the system, sets the DOUT pin to the high level, and sets the DDR register of all ports to 0 and the DTR register to 1. The output type of the ports is set to Nch-open drain and their I/O state (Nch-Tr=OFF) to the "Hi-Z" (input mode) state. 2) When the RES pin is set high (reset) and the CS pin is set and held low for a certain period (TwlCS), the DDR is fixed at 0. Subsequently, the LC709004A is placed in the data communication mode. Fig. 1
• Mode 1 1) When the RES pin is set to the low level, the LC709004A initializes the system, sets the DOUT pin to the high level, and sets the DDR register of all ports to 0 and the DTR register to 1. The output type of the ports is set to Nch-open drain and their I/O state (Nch-Tr=OFF) to the "Hi-Z" (input mode) state. 2) When the RES pins is set high (reset) and the CS pin is set low, the LC709004A gets ready for serial communication. 3) The input data at P00 is sent directly to the DOUT pin on the first falling edge of the transmission clock signal CLK. The data at pins P01 to P17 is loaded into the shift register on the rising edge of the next clock. 4) Subsequently, the ports' input data, which is loaded into the shift register on the falling edge of CLK, is placed at the DOUT pin sequentially (P00→P07, P10→P17) in synchronization with the falling edges of CLK, starting at port pin P00. In parallel with this operation, when data to be placed at the ports is supplied to the DIN pin sequentially starting at the port pin P00 (P00→P07, P10→P17), it is loaded into the internal shift register in synchronization with the rising edges of CLK. 5) When the CS pin is set high after the rising edge of the 16th clock, the data loaded in the shift register is loaded into the DDR register which determines the I/O mode and output type of the data (serial data is loaded into the DDR register after a reset is effected). Subsequently, the LC709004A controls serial data transmission and reception in the data communication mode. Fig. 2 RES CS CLK DIN DOUT Hi-Z DDR DTR *DDR and DTR denote the state of the internal registers. P00 to P17 RES CS CLK DIN DOUT P00 to P17 P00_DR P01 _DR P00_DI P01 _DI P02_DR P03 _DR P02_DI P03 _DI P04_DR P05 _DR P04_DP 0 5 _DI P06_DR P07_DR P06_DP 0 7 _DI P10_DR P11_DR P10_DI P11 _DI P16_DR P17 _DR P16_DI P17 _DI DDR DTR 0 1 2 3 4 5 67 8 9 14 15 Hi-Z Hi-Z * PXX_DR denotes the input data to the port DDR identified by PXX. * PXX_DI denotes the input data from the port pin identified by PXX.

No.A0165-9/13 (2) Data communication mode 1) When the CS pin is set low with the RES pin held high, the LC709004A gets ready for serial communication. (Subsequently, processing in steps 2) and 3) are identical to steps 2) and 3) in paragraph (1)-2). 2) The input data at P00 is sent directly to the DOUT pin on the first falling edge of the CLK signal. Data at pins P01 to P17 is loaded into the shift register on the next rising edge of the clock. 3) Subsequently, the ports' input data, which is loaded into the shift register on the falling edge of CLK, is placed at the DOUT pin sequentially (P00→P07, P10→P17) in synchronization with the falling edges of CLK, starting at port pin P00. In parallel with this operation, when data to be placed at the ports is supplied to the DIN pin sequentially starting at the port pin P00 (P00→P07, P10→P17), it is loaded into the internal shift register in synchronization with the rising edges of CLK. 4) When the CS pin is set high after the rising edge of the 16th clock, the data loaded in the shift register is loaded into the DDR register which determines the output state of the ports and the states of all port pins (P00 to P17) are then changed (output) according to the conditions established in the DDR and DTR registers. Serial data that occurs following the initial communication mode processing is always loaded into the DTR register. Fig. 3 5) Subsequently, the state of all port pins (P00 to P17) is updated each time the set of steps 1) to 4) described in paragraph (2) are performed. Fig. 4 RES CS CLK DIN DOUT P00 to P17 P00_DO P01 _DO P00_DI P01 _DI P02_DO P03 _DO P02_DI P03 _DI P04_DO P05 _DO P04_DI P05 _DI P06_DO P07 _DO P06_DI P07 _DI P10_DO P11_DO P10_DI P11_DI P16_DO P17 _DO P16_DI P17 _DI DDR DTR P00-P17_OUT 0 1 2 3 4 51 4 15 P27_DI(Previous Data) Hi-Z Hi-Z * PXX_DO denotes the output data to the port pin identified by PXX. 6 7 8 9 RES CS CLK DIN DOUT P00 to P17 P00_DO P01 _DO P00_DI P01 _DI P02_DO P03 _DO P02_DI P03 _DI P04_DO P05 _DO P04_DI P05 _DI P06_DO P07 _DO P06_DI P07 _DI P10_DO P11_DO P10_DI P11_DI P16_DO P17 _DO P16_DI P17 _DI DDR DTR P00-P17_OUT 0 1 2 3 4 51 4 15 P00-P17_OUT (Previous Data) P00-P17_OUT (Previous Data) P17_DI(Previous Data) 6 7 8 9

No.A0165-10/13 Application Examples (1) Example of a cascade configuration Two or more LC709004A LSI chips can be cascaded to realize port expansion beyond 16 bits. Port expansion, however, need to be made in units of 16 bits × n (n denotes the number of LSI chips). Fig. 5 (2) Variable port power level example When controlling the level of I/O ports according to the power voltage level of the peripheral equipment, the user can connect the output from the power supply of the peripheral equipment directly to the power supply pins for the I/O ports. The LC709004A dispenses with the need to add an external level shifter circuit. Note the following when configuring the LC709004A in this way: Note 5:

• VDDP1: The voltage level of VDDP1 must not be higher than that of VDD (VDDP1≤VDD).
• The input level of all ports (P00 to P17) is dependent on the VDD power source; it depends on none of the power sources VDDP1. * Be sure to check the electrical characteristics of the LC709004A. Fig. 6 System Reset (RES) Serial CS Output (CS) Serial Data Output (SDO) Serial Clock Output (SCK) Serial Data Input (SDI) Microcontroller (MCU) RES CS DIN CLK DOUT LC709004 RES CS DIN CLK DOUT LC709004 RES CS DIN CLK DOUT LC709004 System Reset (LSI=1) (LSI=2) (LSI=n) Microcontroller (MCU) LC709004A 5.0V 5.0V selial send/receive 5.0V parallel data I/O 3.3V parallel data I/O Nch-open drain display data output 5.0V peripheral 3.3V peripheral LED display 5.0V 3.3V 3.3V VDD VSS VDDP1 P00 to P07 P10 to P13 P14 to P17 RES, CE, CLK, DIN, DOUT VDD VSS

No.A0165-11/13 Example of Placing Bypass Capacitors between VDD and VSS Terminals Fig. 7 In the case of using single voltage source as showing in the Fig.7 (a), you must connect a bypass capacitor (C1, about 0.1μF) between VDD and VSS. When connecting the capacitor (C1) and VDD-VSS, use a thick wire, and try to make its length as short as possible: moreover, try to make the impedance of VDD-C1 and VSS-C1 equal. In addition, when using several voltage sources as showing in the Fig.7 (b), it is suggested to connect the bypass capacitor to each set of the voltage terminals. Fig. 8: Reset Circuit 5.0V VDD VDDP1 VSS LC709004 LC709004 3.3V (a) The case of using single voltage (VDD= VDDP1) (b) The case of using variable voltage 5.0V VDD VDDP1 VSS Note 6: The values of CRES and RRES must be determined so that a reset period of 1μs or longer is set up after the operating voltage goes beyond its lower-limit value and the reset can be released after the operating power voltage is completely reached. CRES VDD RRES RES

No.A0165-12/13 Fig. 9: Serial I/O and Parallel Data I/O Timing Diagram TsCLK TslCS TwlCLK TwhCLK ThlCS ThCLK TshCS TwlRES ThhCS TwlCS TsDIN ThDIN TdDOUT TdPOUT TsPIN ThPIN CS CLK CS RES CLK DIN CLK DOUT CS P00 to P17 CS CLK P00 to P17

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