LC550EGY LG | Alldatasheet
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- PDF pages: 40
Technical content
Datasheet sections
- 1 GENERAL DESCRIPTION
- 2 ABSOLUTE MAXIMUM RATINGS
- 3 ELECTRICAL SPECIFICATIONS
- 4 OPTICAL SPECIFICATIONS
- 5 MECHANICAL CHARACTERISTICS
- 6 MECHANICAL DIMENSION
- 7 RELIABILITY
- 8 INTERNATIONAL STANDARDS
- 9 PACKING
- 10 PRECAUTIONS
Ver 1.0 Title 55.0” QWUXGA TFT LCD BUYER SET MODEL SUPPLIER LG Display Co., Ltd. *MODEL LC550EGY SUFFIX SHM2 (RoHS Verified) FOR APPROVAL SPECIFICATION APPROVED BY SIGNATURE DATE Please return 1 copy for your confirmation with your signature and comments. ( ) Preliminary Specification ( ●) Final Specification APPROVED BY SIGNATURE DATE K.Y. Chong / Team Leader REVIEWED BY K.Y. Chong/ Project Leader PREPARED BY S.W. Kwag / Engineer TV Product Development Dept. LG Display Co., Ltd.
Ver 1.0 2 /39 Revision No. Revision Date Page Description
0.1 May 1, 2014 - Preliminary Specification (First Draft)
0.2 Jun. 9, 2014 19 Updated the drawing of control board assembly 1.0 Jun. 27, 2014 - Final CAS release RECORD OF REVISIONS
Ver 1.0 3 /39 General Features 1. General Description Active Screen Size 54.64 inches(1387.8mm) diagonal Outline Dimension 1225.2 (H) x 696.7 (V) x 1.4 (D) mm(Typ.) Pixel Pitch 0.420 mm x 0.315 mm Resolution 3840 horiz. by 2160 vert. Color Depth 10bit(D), 1.07Billon colors Drive IC Data Interface Source D-IC : 8-bit EPI, gamma reference voltage, and control signals Gate D-IC : Gate In Panel Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.)) Weight 2.6 Kg (Typ.) Display Mode Transmisive mode, Normally black Surface Treatment (Top) Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 1%(Typ.) ) The LC550EGY is a Color Active Matrix Liquid Crystal Display with an integral the Source PCB and Gate implanted on Panel (GIP). The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive type display operating in the normally black mode. It has a 54.64 inch diagonally measured active display area with QWUXGA resolution (2160 vertical by 3840 horizontal). Each pixel is divided into Red, Green, Blue and White sub-pixels or dots which are arranged in vertical stripes. Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot. Therefore, it can present a palette of more than 1.07Bilion colors. It has been designed to apply the 10-bit 8 Lane V by One interface. It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut, high color depth and fast response time are important. Source Driver Circuit TFT - LCD Panel [Gate In Panel] S1 S11520 EPI(RGBW) Timing Controller Vby1 Rx + M+ EEPROM Power Circuit Block SDASCL CN1 (51pin) Control Signal s Power Signals +12V Vby1 8lane Data format Bit select HTPDN LOCKN Vby1 1~8lane Option signal I2C G2160 (3840 × 2160 pixels)
Table 1. ABSOLUTE MAXIMUM RATINGS
- Ambient temperature condition (Ta = 25 2 °C )
- Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39°C, and no condensation of water.
- Gravity mura can be guaranteed below 40°C condition.
- The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber. improper thermal management in final product design.
- Electrical Specifications
Table 2. ELECTRICAL CHARACTERISTICS
- The specified current and power consumption are under the VLCD=12.0V, Ta=25 2°C, fV=60Hz
condition, and mosaic pattern(8 x 6) is displayed and fV is the frame frequency.
- The current is specified at the maximum current pattern.
- The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
- Ripple voltage level is recommended under ± 5% of typical voltage
Table 3. MODULE CONNECTOR(CN1) PIN CONFIGURATION Note 1. All GND (ground) pins should be connected together to the LCD module‟s metal frame.
- All Input levels of V-by-One signals are based on the V-by-One-HS Standard Version 1.4
- #20 NC(No Connection) : These pins are used only for LGD (Do not connect)
- About specific pin(#22), Please see the Appendix Ⅷ.
- Specific pin No. #23 is used for “No signal detection” of system signal interface.
It should be GND for NSB (No Signal Black) while the system interface signal is not. If this pin is “H”, LCD Module displays AGP (Auto Generation Pattern).
9 NC NO CONNECTION 35 Rx2p V-by-One HS Data Lane 2
10 GND Ground 36 GND Ground
11 GND Ground 37 Rx3n V-by-One HS Data Lane 3
12 GND Ground 38 Rx3p V-by-One HS Data Lane 3
13 GND Ground 39 GND Ground
14 PWM TIN External VBR (From System) 40 Rx4n V-by-One HS Data Lane 4
15 PWM TOUT External VBR (For System) 41 Rx4p V-by-One HS Data Lane 4
16 Mplus Mode „L‟ or „NC‟ :Low Power,
42 GND Ground
17 Mplus EN „L‟: RGB Mode, „H‟ or NC : Mplus Mode 43 Rx5n V-by-One HS Data Lane 5
18 SDA SDA (For I2C) 44 Rx5p V-by-One HS Data Lane 5
19 SCL SCL (For I2C) 45 GND Ground
20 NC NO CONNECTION (Note 3) 46 Rx6n V-by-One HS Data Lane 6
21 Bit SEL ‘H’ or NC= 10bit(D) , ‘L’ = 8bit 47 Rx6p V-by-One HS Data Lane 6
22 Data format „L‟ : Non division, „H‟ 2 division 48 GND Ground
23 AGP or NSB ‘H‟ or NC : AGP
49 Rx7n V-by-One HS Data Lane 7
24 GND Ground 50 Rx7p V-by-One HS Data Lane 7
25 HTPDN Hot plug detect 51 GND Ground
26 LOCKN Lock detect - - -
should be satisfied with the following specification for normal operation. Table 4. TIMING TABLE (DE Only Mode) notes: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode). If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.
- The performance of the electro-optical characteristics may be influenced by variance of the vertical
※ Timing should be set based on clock frequency.
Ver 1.0 8 /39 3-4-1. V by One Input Signal Timing Diagram A B F E D C ㆍ ㆍ ㆍ ㆍ ㆍ ㆍ Y=0mV X=0 UI X=1 UI 1UI = 1/(Serial data rate) Y X X[UI] Note Y[mV] Note A 0.25 (max) 2 0 - B 0.3 (max) 2 50 3 C 0.7(min) 3 50 3 D 0.75(min) 3 0 - E 0.7(min) 3 l -50 l 3 F 0.3(max) 2 l -50 l 3 Table5. Eye Mask Specification 3-4. V by One input signal Characteristics notes 1. All Input levels of V by One signals are based on the V by One HS Standard Ver. 1.4 2. This is allowable maximum value. 3. This is allowable minimum value. 4. The eye diagram is measured by the oscilloscope and receiver CDR characteristic must be emulated. - PLL bandwidth : 20 Mhz - Damping Factor : 1.5
Ver 1.0 9 /39 <TCON – VbyOne Brief Diagram > 3-4-2. V by One Input Signal Characteristics tRISK_INTER Lane0 Lane1 Vdiff =0 Vdiff =0 Description Symbol Min Max Unit notes Allowable inter-pair skew between lanes tRISK_INTER - 5 UI 1,3 Allowable iner-pair skew between sub-blocks tRISK_BLOCK - 1 DE 1,4 <Inter-pair Skew between two Lanes> <Inter-pair Skew between two sub Blocks> Notes 1.1UI = 1/serial data rate 2. it is the time difference between the true and complementary single-ended signals. 3. it is the time difference of the differential voltage between any two lanes in one sub block. 4. it is the time difference of the differential voltage between any two blocks in one IP. Rx1 Vblank Hblank Rx2 Vblank DE Max 1 DE DE T-CON V By One Rx IP Rx1 (Sub Block) Rx2 (Sub Block)
4 Lane 4 Lane
2) AC Specification 1) DC Specification VRCT VRTH VRTL Description Symbol Min Max Unit CML Differential input High threshold VRTH - 50 mV CML Differential input Low threshold VRTL -50 - mV CML common mode Bias Voltage VRCT 0.6 0.8 V
Table 6. ELECTRICAL CHARACTERISTICS
The brightness of each primary color (red, green, blue) is based on the 10bit or 8bit gray scale data input for the color. The higher binary input, the brighter the color. Table 7 provides a reference for color versus data input. Table 7. COLOR DATA REFERENCE
Table 8. POWER SEQUENCE
- Even though T1 is over the specified value, there is no problem if I2T spec of fuse is satisfied.
- If T2 is satisfied with specification after removing V by One Cable, there is no problem.
- The T3 / T4 is recommended value, the case when failed to meet a minimum specification,
abnormal display would be shown. There is no reliability problem.
- T5 should be measured after the Module has been fully discharged between power off and on period.
- If the on time of signals (Interface signal and user control signals) precedes the on time of Power (VLCD),
it will be happened abnormal display. When T6 is NC status, T6 doesn‟t need to be measured.
- It is recommendation specification that T7 has to be 0ms as a minimum value.
※ Please avoid floating state of interface signal at invalid period. ※ When the power supply for LCD (VLCD) is off, be sure to pull down the valid and invalid data to 0V.
Optical characteristics are determined after the unit has been „ON‟ and stable in a dark environment at 25± 2°C. The values are specified at distance 50cm from the LCD surface at a viewing angle of and equal to 0 °. FIG. 1 shows additional information concerning the measurement equipment and method. Table 9. OPTICAL CHARACTERISTICS
Table 10. GRAY SCALE SPECIFICATION n = the Position number(1, 2, 3, 4, 5). For more information, see FIG 2.
- Response time is the time required for the display to transit from any gray to white (Rise Time, Tr)
and from any gray to black (Decay time, Tf). For additional information see the FIG. 3. ※ G to GBW Spec stands for average value of all measured points.
- G to G σ is Variation of Gray to Gray response time composing a picture
- The value of transmittance should be extracted using the standard light source of D65
- The value of color coordinates should be extracted using the standard light source of D65
- Viewing angle is the angle at which the contrast ratio is greater than 10. The angles are
is normal to the LCD module surface. For more information, see the FIG. 4. Gamma Value is approximately 2.2. For more information, see the Table 10.
Ver 1.0 15 /39 FIG. 3 Response Time WhiteGray(N) Tr Tf 100 Optical Response N = 0(Black)~1023(White) Gray(N) Black Response time is defined as the following figure and shall be measured by switching the input signal for “Gray(N)” and “Black or White”. FIG. 2 Points for Contrast Ratio Measure A : H / 4 mm B : V / 4 mm @ H,V : Active Area H A V B Measuring point for Contrast Ratio
Ver 1.0 16 /39 FIG. 4 Viewing Angle Dimension of viewing angle range Normal Y E = 0, Right = 180, Lef t = 270, Down = 90, Up
Table 11 provides general mechanical characteristics.
- Mechanical Characteristics
Table 11. MECHANICAL CHARACTERISTICS Note : Please refer to a mechanic drawing in terms of tolerance at the next page.
Ver 1.0 18 /39 6-1. Board Assembly Dimension 6. Mechanical Dimension
Ver 1.0 19 /39 6-2. Control Board Assembly Dimension
Table 12. ENVIRONMENT TEST CONDITION
1 High temperature storage test Ta= 60°C 90% 240h
2 Low temperature storage test Ta= -20°C 240h
3 High temperature operation test Ta= 50°C 50%RH 500h
4 Low temperature operation test Ta= 0°C 500h
5 Humidity condition Operation Ta= 40 °C ,90%RH
6 Altitude operating
Note : Before and after Reliability test, LCM should be operated with normal function.
Ver 1.0 21 /39 8. International Standards 8-1. Safety a) UL 60065, Underwriters Laboratories Inc. Audio, Video and Similar Electronic Apparatus - Safety Requirements. b) CAN/CSA C22.2 No.60065:03, Canadian Standards Association. Audio, Video and Similar Electronic Apparatus - Safety Requirements. c) IEC 60065, The International Electrotechnical Commission (IEC). Audio, Video and Similar Electronic Apparatus - Safety Requirements. 8-2. Environment a) RoHS, Directive 2011/65/EU of the European Parliament and of the council of 8 June 2011
Ver 1.0 22 /39 9-1. Packing Form 9. Packing a) Package quantity in one Pallet : 120 pcs b) Pallet Size : 1390 mm(W) X 890 mm(D) X 1090 mm(H)
Ver 1.0 23 /39 Please pay attention to the followings when you use this TFT LCD module. 10. Precautions 10-1. Handling Precautions (1) Please attach the surface transparent protective film to the surface in order to protect the polarizer. Transparent protective plate should have sufficient strength in order to the resist external force. (2) Acetic acid type and chlorine type materials for the cover case are not desirable because the former generates corrosive gas of attacking the polarizer at high temperature and the latter causes circuit break by electro-chemical reaction. (3) Do not touch, push or rub the exposed polarizers with glass, tweezers or anything harder than HB pencil lead. And please do not rub with dust clothes with chemical treatment. Do not touch the surface of polarizer for bare hand or greasy cloth.(Some cosmetics are detrimental to the polarizer.) (4) After removing the protective film, when the surface becomes dusty, please wipe gently with absorbent cotton or other soft materials like chamois soaks with petroleum benzine. Do not use acetone, toluene and alcohol because they cause chemical damage to the polarizer. (5) Wipe off saliva or water drops as soon as possible. Their long time contact with polarizer causes deformations and color fading. (6) Since a module is composed of electronic circuits, it is not strong to electrostatic discharge. Make certain that treatment persons are connected to ground through wrist band etc. And don‟t touch interface pin directly. Panel ground path should be connected to metal ground. (7) Please make sure to avoid external forces applied to the Source PCB and D-IC during the process of handling or assembling the TV set. If not, It causes panel damage or malfunction. (8) Panel and BLU should be protected from the static electricity. If not, it causes IC damage. (9) Do not pull or fold the source D-IC which connect the source PCB and the panel. (10) Panel(board ass‟y) should be put on the BLU structure precisely to avoid mechanical impact. (11) FFC Cable should be connected between System board and Source PCB correctly. (12) Mechanical structure for backlight system should be designed for sustaining board ass‟y safely. (13) Surface temperature of the Source D-IC should be controlled under 100℃ with TV Set status. If not, problems such as IC damage or decrease of lifetime could occur. 10-2. Operating Precautions (1) Response time depends on the temperature.(In lower temperature, it becomes longer.) (2) Brightness depends on the temperature. (In lower temperature, it becomes lower.) And in lower temperature, Stable time(required time that brightness is stable after turned on) becomes longer (3) Be careful for condensation at sudden temperature change. Condensation makes damage to polarizer or electrical contacted parts. And after fading condensation, smear or spot will occur. (4) When fixed patterns are displayed for a long time, remnant image is likely to occur. (5) Module has high frequency circuits. Sufficient suppression to the electromagnetic interference shall be done by system manufacturers. Grounding and shielding methods may be important to minimized the interference.
Ver 1.0 24 /39 10-3. Protection Film (1) Please keep attaching the protection film before assembly. (2) Please peel off the protection film slowly. (3) Please peel off the protection film just like shown in the Fig.1 (4) Ionized air should be blown over during the peeling. (5) Source PCB should be connected to the ground when peel off the protection film. (6) The protection film should not be contacted to the source D-IC during peeling it off. < Fig. 1 > 10-4. Storage Precautions When storing modules as spares for a long time, the following precautions are necessary. (1) Temperature : 5 ~ 40 ℃ (2) Humidity : 35 ~ 75 %RH (3) Period : 6 months (4) Control of ventilation and temperature is necessary. (5) Please make sure to protect the product from strong light exposure, water or moisture. Be careful for condensation. (6) Please keep the modules at a circumstance shown below Fig. 2 2 month 3 month 6 month No Baking 50℃, 10%, 24hr 50℃, 10%, 48hr 10-5. Packing Precautions Product assembled into module should be stored in the Al-bag(cover case). < Fig. 2 >
Ver 1.0 25 /39 # APPENDIX-Ⅰ-1 ■ Pallet Ass‟y Desiccant X4
Ver 1.0 26 /39 # APPENDIX-Ⅰ- 2 ■ Control PCB Packing Ass’y NO. DESCRIPTION MATERIAL
1 PCB Packing A,ssy -
2 Tray PET
3 Box SWR4
a) Control PCB Qty / Box : 120 pcs b) Tray Qty / Box : 13Tray(Upperst Tray Is empty) c) Tray Size : 453 X 353 X 16 d) Box size : 468 X 355 X 165 [10pcs/Tray] [12Tray] [12Tray+Empty Tray] [Inserting into Box]
Ver 1.0 27 /39 # APPENDIX-Ⅱ-1 20± 0.2mm LC550EGY-SHM2 6± 0.2mm Serial Label Model Name 15mm 6± 0.2mm 20± 0.2mm 17mm Inch P/N Serial No.
Ver 1.0 28 /39 # APPENDIX-Ⅱ-2 ■ BOX Label ■ Pallet Label LC550EGY-SHM2 QTY : 15 LC550EGY SHM2
120 PCS 001/01-01
MADE IN CHINA RoHS Verified XXXXXXXXXXXXX XXX
Ver 1.0 29 /39 # APPENDIX- Ⅲ ■ Required signal assignment for Flat Link (Thine : THCV215) Transmitter notes: 1. The LCD module uses a 100 nF capacitor on positive and negative lines of each receiver input. 2. Refer to Vx1 Transmitter Data Sheet for detail descriptions. (THCV215 or Compatible) 3. About Module connector pin configuration, Please refer to the Page 7. Packer Scrambler 8/10b Encoder Serializer j h g f i e d c b a Tx_n Tx_p H G F E D C B A j h g f i e d c b aD/K H G F E D C B A D/K PD[7:0] D[7:0] D[15:8] D[23:16] D[31:24] PD[7:0] THCV215 or Compatible D[7:0] D[15:8] D[23:16] D[31:24] Tx_n Tx_p HTPDN LOCKN TX’s Inner Structure Tx’s Inner Strucure Timing Controller Rx_n Rx_p HTPDN LOCKN a b c d e i f g h g First Last time Timing diagram of the Serializer FI-RE51(41)S-HF 100nF 100nF VCC
Ver 1.0 30 /39 # APPENDIX- Ⅳ-1 ■ Option Pin Circuit Block Diagram 1) Circuit Block Diagram of Mplus Mode Selection pin ASIC (TCON) 75kΩ System Side LCM Side Data format Select (Pin16) Mplus Mode 1KΩ Mplus Mode Selection : Pin 16 2) Circuit Block Diagram of Mplus Enable pin ASIC (TCON) System Side LCM Side Mplus Enable (Pin 17) Mplus Enable 1KΩ Mplus Enable : Pin 17 VCC 75kΩ
Ver 1.0 31 /39 # APPENDIX- Ⅳ-2 ■ Option Pin Circuit Block Diagram 4) Circuit Block Diagram of Data format Selection pin ASIC (TCON) 75kΩ System Side LCM Side Data format Select (Pin 15,16) Data format Select 1KΩ Data format Select Pin : Pin 22 3) Circuit Block Diagram of Bit Selection pin ASIC (TCON) System Side LCM Side Bit Select (Pin 21) Bit Select 1KΩ Bit Select Pin : Pin 21 VCC 75kΩ
Ver 1.0 32 /39 # APPENDIX- Ⅳ-3 ■ Option Pin Circuit Block Diagram Vcc : 3.3V 1kΩ 10kΩ System Side R1 ≤ 1kΩ (0Ω recommand) FI-RE51S-HF pin #23 LCM Side AGP(auto Generation Pattern ) or NSB (no signal black) : Pin 23 5) Circuit Block Diagram of AGP Selection pin ASIC (TCON) 75kΩ
Ver 1.0 33 /39 # APPENDIX- Ⅳ-4 ■ Option Pin Circuit Block Diagram 6) I2C (SDA/SCL) Selection Pin System Side LCM Side SDA/SCL (Pin 18, 19) 100Ω SDA/SCL : Pin 18, 19 VCC 4.7kΩ EEPROM PM IC EEPROM Slave Address : 70 Slave Address : A0 Slave Address : 40 ASIC (TCON) Note : I2C Line of Set Soc avoid using slave address 40, 70, A0 because LCD module uses those
Ver 1.0 34 /39 # APPENDIX- V VDD*0.9 VDD*0.1 Rising Time Falling Time VDD EXTVBR-B Frequency
50 Hz for PAL
60 Hz for NTSC
Rising Time MAX 10.0 μs Falling Time MAX 10.0 μs ◊ When Mplus Enable is “L", PWM TOUT = System Dimming. PWM TOUT signals are synchronized with V-Sync Freq. of System in T-Con Board. #15 PWM TOUT Pin must be connected to LED Driver, In case of non-Scanning mode. ■ Scanning and Mplus Mode Design Guide Chassis 3.3V Low Power High Luminance System Main IC (PWM Generator) LED Driver B/L Signal Generation Block #1#4 14pin T-Con LCM T-con Board #1 #51 (4pin) #1 : PWM_TOUT #1 #2 : PWM_TOUT #2 #3 : PWM_TOUT #3 #4 : GND (51pin) #14 : PWM TIN #15 : PWM TOUT #16 : M plus Mode #14 PWM TIN #16 Mplus Mode CNT4 CNT1 51pin ◊ PWM Specification ( VDD = 3.3V ) 1. PWM High Voltage Range : 2.5V~3.6V 2. PWM Low Voltage Range : 0.0V~0.7V #15 PWM TOUT
Ver 1.0 35 /39 ■ Flicker Adjustment # APPENDIX- Ⅵ-1 Parameter Unit Min Typ Max Note Inversion Method - V2-Dot Inversion Adjust Pattern / Gray Level - V2Dot Full Flicker / 511Gray 60Hz Position - Center Voltage range V 4.734 5.56 6.371 1) Mplus EN(#17) must be „L‟(RGB Mode) for flicker adjustment LCD Module PMICSCL SDA Adjustment JIG A A : Pull-up Resistors (If it is necessary) B : I2C Connector (Refer to Appendix IX) B 511Gray 0Gray Row 1 Row 2 Row 3 Row 4 Row 1 Row 2 Row 3 Row 4 Row 1 Row 2 Row 3 Row 4 Row 1 Row 2 Row 3 Row 4 <M+ Panel><Input data> Tune the V-com level till the flicker level became stable on center position.
Ver 1.0 36 /39 # APPENDIX- VI -2 Vcom Adjustment Pin No Description Note 1~15 -
17 Mplus EN „L‟: RGB Mode, “H”:Mplus Mode
18 SDA
19 SCL
21~51 - MODULE 51 Pin CNT(CN1) PIN CONFIGURATION LC550EGY-SHM2 Control PCB Assembly uses TI PWM IC(TPS65178). PWM IC (Slave) Address is 40h (01000000), Vcom Register address is 0x16. If you need detailed information, Please refer to TI PWM IC(TPS65178) Data Sheet or contact with TI company.
Ver 1.0 37 /39 ■ The reference method of BL dimming It is recommended to use synchronous V-sync frequency to prevent waterfall (Vsync * 2 =P-Dim Frequency) # APPENDIX- Ⅶ
Ver 1.0 38 /39 ■ input mode of pixel data Lane 1st Data 2nd Data Data# Lane0 1 9 3833 Lane1 2 10 3834 Lane2 3 11 3835 Lane3 4 12 3836 Lane4 5 13 3837 Lane5 6 14 3838 Lane6 7 15 3839 Lane7 8 16 3840 Lane 1st Data 2nd Data Data# Lane0 1 5 1917 Lane1 2 6 1918 Lane2 3 7 1919 Lane3 4 8 1920 Lane4 1921 1925 3837 Lane5 1922 1926 3838 Lane6 1923 1927 3839 Lane7 1924 1928 3840 Mode 1 : Non-Division Mode 2 : 2 Division # APPENDIX- Ⅷ
Ver 1.0 39 /39 # APPENDIX-Ⅸ ◈ Note - Pad : GOLD Plating - ＃ ≥ Cpk 1.0 - ## ≥ Cpk 1.33 - Stiffener color : Sky Blue - H-F - Dimensions unit : mm - Material List 124 ± 1.0 124 ± 1.0 # 0.5 +0.07/-0.045 # 3+0.5/-0.35 # 29.5± 0.05 < Pad Detail– -0.035 # 0.5 +0.07/ 0.045 # 3+0.5/ 0.35 0.05 < Pad Detail– 60Pin > (Adhesive) 4.5+0.8/-0.4 # 0.31+0.03/-0.02 Conductor Pad Bottom Side # 0.31+0.03/-0.02 (Adhesive) 4.5+0.8/-0.4 (Adhesive) 4.5+0.8/ 0.4 # 0.31+0.03/ 0.02 Conductor Pad Bottom Side # 0.31+0.03/-0.02 (Adhesive) 4.5+0.8/-0.4 Adhesive Area Adhesive -left Adhesive -right # 0.3 mm Max Adhesive -left Adhesive -right # 0.3 mm Max Adhesive Area (Stiffener) 16.0+0.8/-0.4 Silicone Tape Area