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Document overview
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Technical content
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www.onsemi.com © Semiconductor Components Industries, LLC, 2015 January 2015 - Rev. 2
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of this data sheet. LC05111CMT Overview The LC05111CMT is a protection IC for 1-cell lithium-ion secondary batteries with integrated power MO S FET. Also it integrates highly accurate detection circuits and detection delay circuits to prevent batteries from over-charging, over-discharging, over-current discharging and over-current charging. A battery protection system can be made by only LC05111CMT and few external parts. Feature Charge-and-discharge power MOSFET are integrated at Ta = 25C, VCC = 4.5V ON resistance (total of charge and discharge) 11.2m (typ) Highly accurate detection voltage/current at Ta = 25C, VCC = 3.7V Over-charge detection ±25mV Over-discharge detection ±50mV Charge over-current detection ±0.7A Discharge over-current detection ±0.7A Delay time for detection and release (fixed internally) Discharge/Charge over-current detection is compensated for temperature dependency of power FET 0V battery charging : “Permission” Auto wake-up function battery charging : “Permission” Over charge detection voltage : 4.0V to 4.5V (5mV steps) Over charge release hysteresis : 0V to 0.3V (100mV steps) Over discharge detection voltage : 2.2V to 2.7V (50mV steps) Over discharge release hysteresis at Auto wake-up : 0V to 0.6V (200mV steps) Over discharge release hysteresis : 0V to 0.075V (25mV steps) Discharge over current detection : 2.0A to 8.0A (0.5A steps) Charge over current detection : 8.0A to -2.0A (0.5A steps) Typical Applications Lithium ion battery protection CMOS LSI 1-Cell Lithium-Ion Battery Protection IC with integrated Power MOS FET WDFN6 2.6x4.0, 0.65P, Dual Flag
www.onsemi.com Specifications Absolute Maximum Ratings at Ta = 25C Parameter Symbol Conditions Ratings Unit Supply voltage VCC Between PAC+ and VCC : R1=680 0.3 to +12.0 V S1 - S2 voltage VS1-S2 24.0 V CS terminal Input voltage CS VCC24.0 V Charge or discharge current BAT-, PAC- 10.0 A TST Input voltage TST 0.3 to +7.0 V Storage temperature Tstg 55 to +125 C Current between S1 and S2(DC) ID VCC = 3.7V 10.0 A Current between S1 and S2 (continuous pulse) IDP Pulse Width<10s, duty cycle<1% 35 A Operating ambient temperature Topr 40 to +85 C Allowable power dissipation Pd Glass epoxy four-layer board. Board size 27.4mm x 3.1mm x 0.8mm 450 mW Junction temperature Tj 125 C Caution 1) Absolute maximum ratings represent the values which cannot be exceeded even for a moment. Caution 2) If you should intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a confirmation. Example of Application Circuit Components Recommended value MAX unit Description R1 680 1k R2 1k 2k C1 0.1 1.0 F * We don’t guarantee the characteristics of the circuit shown above. * TST pin would be better to be connected to VSS pin, though it is connected to VSS with internal resistor (100k typ). * Battery voltage drop occurs, a current of about 60uA flow period of 1.5V-1.3V . Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
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Electrical Characteristics
Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Over-charge detection voltage Vov R1=680 25C Vov_set -25 Vov_set Vov_set +25 mV30 to 70C Vov_set -30 Vov_set Vov_set +30 Over-charge release voltage Vovr R1=680 25C Vovr_set -40 Vovr_set Vovr_set +40 mV30 to 70C Vovr_set -70 Vovr_set Vovr_set +70 Over-discharge detection voltage Vuv R1=680 25C Vuv_set -50 Vuv_set Vuv_set +50 mV30 to 70C Vuv_set -80 Vuv_set Vuv_set +80 Over-discharge release voltage Vuvr R1=680 CS=0V 25C Vuvr_set -100 Vuvr_set Vuvr_set +100 mV 30 to 70C Vuvr_set -120 Vuvr_set Vuvr_set +120 Over-discharge release voltage2 Vuvr2 R1=680 CS=open 25C Vuvr2_set -100 Vuvr2_set Vuvr2_set +100 mV 30 to 70C Vuvr2_set -120 Vuvr2_set Vuvr2_set +120 Discharge over-current detection current Ioc R2=1k 25C VCC=3.7V Ioc_set -0.7 Ioc_set Ioc_set +0.7 A 30 to 70C VCC=2.6 to 4.3V Ioc_set -1.2 Ioc_set Ioc_set +1.2 Discharge over-current release current Iocr R2=1k 25C VCC=3.7V (Ioc_set-0.7) (Ioc_set) (Ioc_set+0.7) A 30 to 70C VCC=2.6 to 4.3V (Ioc_set-1.2) (Ioc_set) oc_set+1.2) Discharge over-current detection current(Short circuit) Ioc2 R2=1k 25C VCC=3.7V Ioc2_set*0.8 Ioc2_set Ioc2_set*1.2 A Charge over-current detection current Ioch R2=1k 25C VCC=3.7V Ioch_set -0.7 Ioch_set Ioch_set +0.7 A 30 to 70C VCC=2.6 to 4.3V Ioch_set -1.2 Ioch_set Ioch_set +1.2 Charge over-current release current Iochr R2=1k 25C VCC=3.7V Ioch_set -0.7 Ioch_set Ioch_set +0.7 A 30 to 70C VCC=2.6 to 4.3V Ioch_set -1.2 Ioch_set Ioch_set +1.2 Input voltage Operating Voltage for 0V charging Vchg VCC-CS VCC-GND =0V 25C 1.4 V Current consumption Operating current Icc At normal state 25C VCC=3.7V 3 6 A Stand-by current Istb At Stand-by state 25C VCC=2.0V 0.95 AAuto wake-up =enable Continued on next page.
www.onsemi.com Continued from preceding page. Parameter Symbol Conditions MIN. TYP. MAX. Unit Resistance ON resistance 1 of Ron1 VCC=3.1V 25C 10.4 13 18.2 m integrated power MOS FET I=±2.0A ON resistance 2 of Ron2 VCC=3.7V 25C 9.6 12 15.6 m integrated power MOS FET I=±2.0A ON resistance 3 of Ron3 VCC=4.0V 25C 9.2 11.6 15 m integrated power MOS FET I=±2.0A ON resistance 4 of Ron4 VCC=4.5V 25C 8.8 11.2 14 m integrated power MOS FET I=±2.0A Internal resistance (VCC-CS) Rcsu VCC=Vuv _set CS=0V 25C 300 k Internal resistance (VSS-CS) Rcsd VCC=3.7V CS=0.1V 25C 15 k Detection and Release delay time Over-charge detection delay time Tov 25C 0.8 1 1.2 sec 30 to 70C 0.6 1 1.5 Over-charge release delay time Tovr 25C 12.8 16 19.2 ms 30 to 70C 9.6 16 24 Over-discharge detection delay time Tuv 25C 16 20 24 ms 30 to 70C 12 20 30 Over-discharge release delay time Tuvr 25C 0.9 1.1 1.3 ms 30 to 70C 0.6 1.1 1.5 Discharge over-current detection delay time 1 Toc1 VCC=3.7V 25C 9.6 12 14.4 ms 30 to 70C 7.2 12 18 Discharge over-current release delay time 1 Tocr1 VCC=3.7V 25C 3.2 4 4.8 ms 30 to 70C 2.4 4 6 Discharge over-current detection delay time 2 (Short circuit) Toc2 VCC=3.7V 25C 280 400 560 30 to 70C 180 400 800 Charge Over-current detection delay time Toch VCC=3.7V 25C 12.8 16 19.2 ms 30 to 70C 9.6 16 24 Charge Over-current release delay time Tochr VCC=3.7V 25C 3.2 4 4.8 ms 30 to 70C 2.4 4 6 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per formance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com SELECTION GUIDE Device Vov(V) Vovr(V) Vuv(V) Vuvr(V) Vuvr2(V) AWUP Ioc(A) Ioch(A) Ioc2(A) 0Vcharge Pdmax-Ta graph
www.onsemi.com Recommended board layout Board schematic Board size L=27.4mm W=3.1 mm H=0.8mm glass-epoxy 4layers All layer Top layer 2nd layer 3rd layer 4th layer PACK+ PACK- 27.4mm 3.1mm
www.onsemi.com Note Please connect the VSS line to a pin of S1 directly. Please connect the resistance of R2 to a pin of S2 directly. It can perform the detection of the overcurrent exactly by performing these. It can get rid of influence of the wiring impedance caused by a severe electric current flowing through S1 and S2. Red line of schematic is very important line. Zoom
www.onsemi.com Package Dimensions unit : mm WDFN6 2.6x4.0, 0.65P , Dual Flag CASE 511BZ ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. PROFILE TOLERANCE APPLIES TO THE EXPOSED PADS AS WELL AS THE LEADS. XXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week = Pb−Free Package 12 3 TOP VIEW SIDE VIEW D E BA 0.10 C 0.10 C A 0.05 C 0.10 C GENERIC MARKING DIAGRAM* XXXXX XXXXX AYWW PIN ONE REFERENCE NOTE 3 C SEATING PLANE (Note: Microdot may be in either location) SOLDERING FOOTPRINT* 0.27 0.65 0.40 2.29 PITCH 2.50 DIMENSION: MILLIMETERS 4.20 6X0.53 PACKAGE 0.40 OUTLINE RECOMMENDED DIM MIN MILLIMETERS A −−− A3 0.10 b 0.25 D 2.60 BSC D2 2.075 D3 1.20 E 4.00 BSC E2 2.95 E3 2.25 L 0.12 MAX 0.80 0.25 0.40 2.375 1.50 3.05 2.55 0.32 D4 0.40 0.70 e 0.65 BSC L2 −−− 0.10 BOTTOM VIEW L e b6X AM0.10 B C M0.05 C 4X L2 D4D3 b24X 4X L3 b2 0.15 0.30 E1 3.80 REF L3 −−− 0.55
www.onsemi.com Pin Functions Pin No. Symbol Pin Function Description
1 S2 Charger minus voltage input pin
2 CS Charger minus voltage input pin
4 VSS Negative power input
5 VCC VCC terminal
6 S1 Negative power input
7 Drain Drain of FET Exposed pad
8 Sub IC Sub (VSS) Exposed pad
1.2V Discharge Over- current De t e c t o r DCHG_ SW CHG_SW Short- circuit Detector C harge O ver- current De t e c to r （Pack minus） 1.2V VSS
www.onsemi.com (1) Normal mode LC05111CMT controls charging and discharging by detecting cell voltage (VCC) and controls S2-S1 current. In case that cell voltage is between ov er-discharge detection voltage (Vuv) and over-charge detection voltage (Vov), and S2-S1 current is between charge over-current detection current (Ioch) and discharge over-current detection current (Ioc), internal power MOS FETs as CHG_SW, DCHG_SW are all turned ON. This is the normal mode, and it is possible to be charged and discharged. (2) Over-charging mode Internal power MOS FET as CHG_SW will be turned off if cell voltage will get equal to or higher than over-charge detection voltage (Vov) over the delay time of over-charging (Tov). This is the over-charging detection mode. The recovery from over-charging will be made after the following three conditions are all satisfied. a. Charger is removed from IC. b. Cell voltage will get lower than over-charge release voltage (Vovr) over the delay time of over-charging release (Tovr) due to discharging through load. Consequently, internal power MOS FET as CHG_SW will be turned on and normal mode will be resumed. In over-charging mode, discharging over-current detection is made only when CS pin will get higher than discharging over-current detection current 2(Ioc2), because discharge current flows through parasitic diode of CHG_SW FET. If CS pin voltage will get higher than discharging over-current detection current 2 (Ioc2) over the delay time of discharging over-current 2 (T oc2), discharging will be shut off, because internal power FETs as DCHG_SW is turned off.(short-circuit detection mode) After detecting short-circuit, CS pin will be pulled down to Vss by internal resistor Rcsd. The recovery from short circuit detection in ov er-charging mode will be made after the following two conditions are satisfied. a. Load is removed from IC. b. CS pin voltage will get equal to or lower than discharging over-current detection current 2 (Ioc2) due to CS pin pulled down through Rcsd. Consequently, internal power MOS FET as DCHG_SW will be turned on, and over-charging detection mode will be resumed. (3) Over-discharging mode If cell voltage will get lower than over-discharge detection voltage (Vuv) over the delay time of over-discharging (Tuv), discharging will be shut off, because internal power FETs as DCHG_SW is turned off. This is the over-discharging mode. After detecting over-discharging, CS pin will be pulled up to Vcc by internal resistor Rcsu and the bias of internal circuits will be shut off. (Stand-by mode) In stand-by mode, operating current is suppressed under 0.95uA (max). The recovery from stand-by mode will be made by internal circuits biased after the following two conditions are satisfied. a. Charger is connected. b. VCC level rise more than Over-discharge release voltage2(Vuvr2) without charger.(Auto wake-up function) If CS pin voltage will get lower than charger detecting voltage (Vchg) by connecting charger under the condition that cell voltage is lower than over-disc harge detection voltage, internal power MOS FET as DCHG_SW is turned on and power dissipation in power MOS FETs is suppressed. *In case that charging current is low enough, ripple current will be appeared at S2 terminal when CS pin voltage is near by the threshold of charger detecting voltage (Vchg). It is caused that the two modes, charger detected and charger not detected (charging through parasitic diodes of DCHG_SW, is alternately appeared. Continue into next page
www.onsemi.com Continued from previous page By continuing to be charged, if cell voltage will get higher than over-discharge detection voltage (Vuvr) over the delay time of over-discharging (Tuvr), internal power MOS FETs as DCHG_SW is turned on and normal mode will be resumed. In over-discharge detection mode, charging over-current detection does not operate. By continuing to be charged, char ging over-current detection starts to operate after cell voltage goes up more than over-discharge release voltage (Vuvr). (4) Discharging over-current detection mode 1 Internal power MOS FET as DCHG_SW will be turned off and discharging current will be shut off if CS pin voltage will get equal to or higher than discharging over-current detection current (Ioc) over the delay time of discharging over-current (Toc1). This is the discharging over-current detection mode 1. In discharging over-current detection mode 1, CS pin will be pulled down to Vss with internal resistor Rcsd. The recovery from discharging over-current detection mode will be made after the following two conditions are satisfied. a. Load is removed from IC. b. CS pin voltage will get equal to or lower than dischar ging over-current release current (Iocr) over the delay time of discharging over-current release (Tocr1) due to CS pin pulled down through Rcsd. Consequently, internal power MOS FET as DCHG_ SW will be turned on, and normal mode will be resumed. (5) Discharging over-current detection mode 2 (short circuit detection) Internal power MOS FET as DCHG_SW will be turned off and discharging current will be shut off if CS pin voltage will get equal to or higher than discharging over -current detection current2 (Ioc2) over the delay time of discharging over-current 2 (Toc2). This is the short circuit detection mode. In short circuit detection mode, CS pin will be pulled down to Vss by internal resistor Rcsd. The recovery from short circuit detection mode will be made after the following two conditions are satisfied. a. Load is removed from IC. b. CS pin voltage will get equal to or lower than dischar ging over-current release current (Iocr) over the delay time of discharging over-current release (Tocr1) due to CS pin pulled down through Rcsd. Consequently, internal power MOS FET as DCHG_ SW will be turned on, and normal mode will be resumed. (6) Charging over-current detection mode Internal power MOS FET as CHG_SW will be turned off and charging current will be shut off if CS pin voltage will get equal to or lower than charging over-current detection current (Ioch) over the delay time of charging over-current (Toch). This is the charging over-current detection mode. The recovery from charging over-current detection mode will be made after the following two conditions is satisfied. a. Charger is removed from IC and CS pin will get higher by load connected. b. CS pin voltage will get equal to or higher than chargi ng over-current release current (Iochr) over the delay time of charging over-current release (Tocrh). Consequently, internal power MOS FET as CHG_SW will be turned on, and normal mode will be resumed. *Internal current flows out through CS and S2 terminals. After charger is removed, it flows through parasitic diode of CHG_SW FET. Therefore, CS pin voltage will go up more than charging over-current release current (Iochr). So CS pin voltage is not an indispensable condition for recovery from charging over-current detection. Continue into next page
www.onsemi.com Continued from previous page (7) Available Voltage for 0V charging It is the function that the voltage of a connected batte ry can charge from the st ate that became 0V by self-discharge. The 0V battery charge start battery charger voltage (Vchg), it fix a gate of the charge system order FET to the VDD terminal voltage when it connect a battery charger of the above-mentioned voltage to PAC+ terminal between PAC- terminals. Gate-source voltage of the charge control FET becomes equal to the turn-on voltage or more due to the charger voltage, the charging control FET. To start charging row is turned on. Discharge control FET is off at this time, the charge current flows through the internal parasitic diode in the discharging control FET. It is the normal state battery voltage becomes the overdischarge release voltage (Vuvr) or more.
www.onsemi.com Timing Chart Over-charge detection/release, Over-discharge detection/release (connect charger)
www.onsemi.com Over-charge detection/release, Over-discharge detection/release (non connect charger) VCC Vov Vovr Vuv DCHG_SW CHG_SW CS VCC VCC VCC Charger connection Load connection Tov Tovr Tuv Tuvr Load connection Vuvr2
www.onsemi.com Discharge over-current detection1, Discharge over-current detection2 (Short circuit)
www.onsemi.com Charge over-current detection
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