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3-phase bipolar drive Full complement of on-chip protection circuits, including lock protection, current limiter, under-voltage protection, and thermal shutdown protection circuits Direct PWM drive + synchronous rectification IO max1 = 2.5A IO max1 = 3.0A (t 0.1ms) Circuit to switch slowing down method while stopped (Free run or Short-circuit brake) Output current control circuit PLL speed control circuit Constraint protection detection signal switching circuit (FG or LD) Phase lock detection output Forward / Reverse switching circuit (with mask function) Hall bias pin (Bias current cut in a stopped state) Compatible with Hall FG SDCC (Speed Detection Current Control) function Provides a 5V regulator output Specifications Absolute Maximum Ratings at Ta = 25C Parameter Symbol Conditions Ratings Unit Supply voltage V CC max V CC pin 37 V VG max VG pin 42 V Output current I O max1 *1 2.5 A IO max2 t 0.1ms *1 3.0 A Allowable Power dissipation Pd max Mounted on a specified board *2 1.7 W Operation temperature Topr -25 to +80 C Storage temperature Tstg -55 to +150 C Junction temperature Tj max 150 C *1. Tj max = 150C must not be exceeded. Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time. Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current, high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details. Bi-CMOS LSI 3-phase Brushless Motor Driver for Polygon Mirror Motor Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. SSOP44K(275mil) Exposed Pad
No.A1416-2/15 Allowable Operating Ranges at Ta = 25C Parameter Symbol Conditions Ratings Unit Supply voltage range V CC 10 to 35 V 5V constant voltage output current I REG 0 to -30 mA LD pin applied voltage V LD 0 to 5 V LD pin output current I LD 0 to 15 mA FG pin applied voltage V FG 0 to 5 V FG pin output current I FG 0 to 15 mA HB pin output current I HB 0 to -30 mA Electrical Characteristics at Ta 25C, VCC = 24V Parameter Symbol Conditions Ratings Unit min typ max Current drain I CC1 5.5 6.5 mA ICC2 In a stop state 1.0 1.5 mA 5V Constant Voltage Output Output voltage VREG 4.65 5.0 5.35 V Line regulation VREG1 V CC = 10 to 35V 20 100 mV Load regulation VREG2 I O = -5 to -20mA 25 60 mV Temperature coefficient VREG3 Design target value * 0 mV/ C Output Block Output ON resistance R ON I O = 1A , Sum of the lower and upper side outputs 1.5 1.9 Output leakage current I Oleak Design target value * 10 A Lower side Diode forward voltage V D1 I D = -1A 1.0 1.35 V Upper side Diode forward voltage V D2 I D = 1A 1.0 1.35 V Charge Pump Output (VG pin) Output voltage VG OUT V CC+4.9 V CP1 pin Output ON resistance (High level) V OH(CP1) I CP1 = -2mA 500 700 Output ON resistance (Low level) V OL(CP1) I CP1 = 2mA 300 400 Hall Amplifier Block Input bias current I HB(HA) -2 -0.5 A Common mode input voltage range V ICM 0.5 VREG-2.0 V Hall input sensitivity 80 mVp-p Hysteresis VIN(HA) 15 24 42 mV Input voltage L H V SLH 12 mV Input voltage H L V SHL -12 mV Hall Bias (HB pin) P-channel Output Output voltage ON resistance V OL(HB) I HB = -20mA 20 30 Output leakage current I L(HB) V O = 0V 10 A FG Amplifier Schmitt Block (IN1) Input amplifier gain G FG Design target value * 5 times Input hysteresis (H L) V SHL(FGS) Input referred, Design target value * 0 mV Input hysteresis (L H) V SLH(FGS) Input referred, Design target value * 10 mV hysteresis V FGL Input referred, Design target value * 10 mV * Design target value, Do not measurement. Continued on next page. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recomme nded Operating Ranges limits mayaffect device reliability.
No.A1416-3/15 Continued from preceding page. Parameter Symbol Conditions Ratings Unit min typ max FGFIL pin High level output voltage V OH(FGFIL) 2.7 3.0 3.3 V Low level output voltage V OL(FGFIL) 0.75 0.85 0.95 V External capacitor charge current I CHG1 V CHG1 = 1.5V -5 -4 -3 A External capacitor discharge current I CHG2 V CHG2 = 1.5V 3 4 5 A Amplitude V(FGFIL) 1.95 2.15 2.35 Vp-p FG Output Output ON resistance V OL(FG) I FG = 7mA 20 30 Output leakage current I L(FG) V O = 5V 10 A PWM Oscillator High level output voltage V OH(PWM) 2.95 3.2 3.45 V Low level output voltage V OL(PWM) 1.3 1.5 1.7 V External capacitor charge current I CHG(PWM) V PWM = 2V -90 -70 -50 A Oscillation frequency f(PWM) C = 150pF 180 225 270 kHz Amplitude V(PWM) 1.5 1.7 1.9 Vp-p Recommended operation frequency range fOPR 15 300 kHz CSD Oscillation Circuit High level output voltage V OH(CSD) 2.7 3.0 3.3 V Low level output voltage V OL(CSD) 0.8 1.0 1.2 V Amplitude V(CSD) 1.75 2.0 2.25 Vp-p External capacitor charge current I CHG1(CSD) V CHG1 = 2.0V -14 -10 -6 A External Capacitor Discharge Current I CHG2(CSD) V CHG2 = 2.0V 8 11 14 A Oscillation frequency f(CSD) C = 0.068 F, Design target value * 30 40 50 Hz Phase comparing output Output ON resistance (high level) V PDH I OH = -100A 500 700 Output ON resistance (low level) V PDL I OL = 100A 500 700 Phase Lock Detection Output Output ON resistance V OL(LD) I LD = 10mA 20 30 Output leakage current I L(LD) V O = 5V 10 A Error Amplifier Block Input offset voltage V IO(ER) Design target value * -10 +10 mV Input bias current I B(ER) -1 +1 A High level output voltage V OH(ER) I OH = -100A EI+0.7 EI+0.85 EI+1.0 V Low level output voltage V OL(ER) I OL = 100A EI-1.75 EI-1.6 EI-1.45 V DC bias level V B(ER) -5% VREG/2 5% V Current Control Circuit Drive gain GDF While phase locked 0.5 0.55 0.6 times Current Limiter Circuit (pins RF and RFS) Limiter voltage V RF 0.465 0.515 0.565 V Under-voltage Protection Operation voltage VSD 8.3 8.7 9.1 V Hyteresis VSD 0.2 0.35 0.5 V CLD Circuit External capacitor charge current I CLD V CLD = 0V -4.5 -3.0 -1.5 A Operation voltage V H(CLD) 3.25 3.5 3.75 V Thermal Shutdown Operation Thermal shutdown operation temperature TSD Design target value (Junction temperature) 150 175 C. Hysteresis TSD Design target value (Junction temperature) 30 C * Design target value, Do not measurement. Continued on next page.
No.A1416-4/15 Continued from preceding page. Parameter Symbol Conditions Ratings Unit min typ max CLK pin External input frequency f I(CLK) 0.1 10 kHz High level input voltage V IH(CLK) 2.0 VREG V Low level input voltage V IL(CLK) 0 1.0 V Input open voltage V IO(CLK) VREG-0.5 VREG V Hysteresis V IS(CLK) 0.2 0.3 0.4 V High level input current I IH(CLK) V CLK = VREG -10 0 +10 A Low level input current I IL(CLK) V CLK = 0V -110 -85 -60 A CSDSEL pin High level input voltage V IH(CSD) 2.0 VREG V Low level input voltage V IL(CSD) 0 1.0 V Input open voltage V IO(CSD) VREG-0.5 VREG V High level input current I IH(CSD) V CSD = VREG -10 0 +10 A Low level input current I IL(CSD) V CSD = 0V -110 -85 -60 A S/S pin High level input voltage V IH(SS) 2.0 VREG V Low level input voltage V IL(SS) 0 1.0 V Input open voltage V IO(SS) VREG-0.5 VREG V Hysteresis V IS(SS) 0.2 0.3 0.4 V High level input current I IH(SS) V S/S = VREG -10 0 +10 A Low level input current I IL(SS) V S/S =0V -110 -85 -60 A BRSEL pin High level input voltage V IH(BRSEL) 2.0 VREG V Low level input voltge V IL(BRSEL) 0 1.0 V Input open voltage V IO(BRSEL) VREG-0.5 VREG V High level input current I IH(BRSEL) V BRSEL = VREG -10 0 +10 A Low level input current I IL(BRSEL) V BRSEL = 0V -110 -85 -60 A F/R pin High level input voltage V IH(FR) 2.0 VREG V Low level input voltage V IL(FR) 0 1.0 V Input open voltage V IO(FR) VREG-0.5 VREG V High level input current I IH(FR) V F/R = VREG -10 0 +10 A Low level input current I IL(FR) V F/R = 0V -110 -85 -60 A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per formance may not be indicated by the Electrical Characteristics if operated under different conditions.
No.A1416-5/15 Package Dimensions unit : mm SSOP44K (275mil) Exposed Pad CASE 940AF ISSUE A
No.A1416-6/15 SOLDERING FOOTPRINT* *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (Unit: mm) 7.00 0.32 1.00 0.65 (4.7) (3.5) NOTES: 1. The measurements are for reference only, and unable to guarantee. 2. Please take appropriate action to design the actual Exposed Die Pad and Fin portion. 3. After setting, verification on the product must be done. (Although there are no recommended design for Exposed Die Pad and Fin portion Metal mask and shape for Through-Hole pitch (Pitch & Via etc), checking the soldered joint condition and reliability verification of soldered joint will be needed. Void gradient insufficient thickness of soldered joint or bond degradation could lead IC destruction because thermal conduction to substrate becomes poor.) XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data GENERIC MARKING DIAGRAM* *This information is generic. Please refer to device data sheet for actual part marking. may or may not be present. XXXXXXXXXX YMDDD
No.A1416-7/15 -20 0 20 40 60 80 1000 2.0 1.5 1.0 0.5 Pd max -- Ta 1.7 0.95 Ambient temperature, Ta -- °C Allowable power dissipation, Pd max -- W Specified board: 114.3×76.1×1.6mm3 glass epoxy board. Pin Assignment 44 43 42 41 40 39 38 37 2930313233343536 232425262728 1CLK 2LD 3S/S 4VREG 5BRSEL 6CSDSEL 7F/R 8CLD 161514131211109 222120191817 CSD FG PWM FC FGFIL PH PD EI EO TOC GND HB CP2 CP1 VG VCC1 VCC2 RFS RF OUT1 OUT2 OUT3 GND2 SUB IN3− IN3+ IN2− IN2+ IN1− IN1+ LV8111V Top view
No.A1416-8/15 Block Diagram and Application Circuit Example CSDSEL CSD OSC BRSEL S/S F/R COUNT LOGIC LD LD MASK CLK PLL FG FILTER HALL HYS AMP HB CURR LIM CNTROL CIRCUIT LOGIC PWM OSC COMP CONT AMP PEAK HOLD VREG LVDS DRIVER CHARGE PUMP VREG PD EI EO TOC FC PH VREG VCC1 VCC2 VG CP1 CP2 VCC OUT1 OUT2 OUT3 GND2 SUB GNDRFRFSHBIN1+ IN2+ IN3+IN1− IN2− IN3− FGFIL FG CLK CLD LD F/R S/S BRSEL CSD CSDSEL PWM LD output CLK input FG output TSD
No.A1416-9/15 Pin Function Pin No. Pin name Function Equivalent circuit
1 CLK Clock input pin (10kHz maximum)
5kΩ 10kΩ 55kΩ VREG 2 LD Phase lock detection output pin. Goes ON during PLL-phase lock. Open drain output. VREG 3 S/S Start/Stop input pin. START with a low-level input. STOP with a high-level input or open input 5kΩ 10kΩ 55kΩ VREG 4 VREG 5V regulator output pin. (the control circuit power supply) Connect a capacitor between this pin and GND for stabilization. VCC 50Ω 5 BRSEL Brake selection pin. By low level, short-circuit braking when the S/S pin is in a stopped state. (Brake for the inspection process) 5kΩ 55kΩ VREG 6 CSDSEL Motor constraint protection detection signal selection pin. Select FG with low, and LD with high or in an open state. 5kΩ 55kΩ VREG Continued on next page.
No.A1416-10/15 Continued from preceding page. Pin No. Pin name Function Equivalent circuit 7 F/R Pin to select Forward / Reverse. 5kΩ 55kΩ VREG 8 CLD Pin to set phase lock signal mask time. Connect a capacitor between this pin and GND. If there is no need for masking, this pin must be left open. 500Ω VREG 2kΩ
9 CSD Pin for both the constraint protection circuit operation time
and the initial reset pulse setting. Connect a capacitor between this pin and GND. If the motor constraint protection circuit is not used, a capacitor and a resistor must be connected in parallel between the CSD pin and GND. 500Ω VREG 10 FG FG Schmitt output pin. Open drain output. VREG 12 PWM Pin to set the oscillation frequency of PWM. Connect a capacitor between this pin and GND. VREG 200Ω 2kΩ
14 FC Frequency characteristics correction pin of the current
limiter circuit. Connect a capacitor between this pin and GND. VREG 500Ω 110kΩ Continued on next page.
No.A1416-11/15 Continued from preceding page. Pin No. Pin name Function Equivalent circuit 15 FGFIL FG filter pin. When the noise of the FG signal is a problem, connect a capacitor between this pin and GND for stabilization. 500Ω VREG 15kΩ 16 PH Pin to stabilize the RF waveform. Connect a capacitor between this pin and GND. VREG 500Ω 10kΩ 17 PD Phase comparison output pin. The phase error is output by the duty changing of the pulse. VREG 500Ω 18 EI Error amplifier input pin. VREG 500Ω 19 EO Error amplifier output pin. VREG 100kΩ 20 TOC Torque command voltage input pin. Normally, this pin must be connected with the EO pin. VREG 21 GND Ground pin of the control circuit block. Continued on next page.
No.A1416-12/15 Continued from preceding page. Pin No. Pin name Function Equivalent circuit 22 HB Hall element bias current pin. Goes ON when the S/S pin is in a start state. Goes OFF when the S/S pin is in an stopped state. VREG IN1+ IN1 IN2+ IN2 IN3+ IN3 Hall amplifier input pin. A high level state of logic is recognized when IN+ > IN. In reverse case is a low-level state. The input amplitude of 100mVp-p or more (differential) is desirable in the Hall sensor inputs. If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. VREG 500Ω500Ω 2624 28 2723 29 SUB Frame ground pin. This pin is connected with the GND2 pin. 30 GND2 Ground pin of the output circuit block. OUT3 OUT2 OUT1 Output pin. As for PWM, Duty control is executed on the upper- side FET. VCC 34 36 38 RF Source pin of output MOSFET (lower-side). Connect a low resistance (Rf) between this pin and GND. 39 RFS Output current detection pin. Connect to RF pin. 5kΩ VREG 40 V CC2 Power supply pin. Connect a capacitor between this pin and GND for stabilization. 41 V CC1 Power supply pin for control.
42 VG Charge pump output pin (Power supply for the upper side
FET gate). Connect a capacitor between this pin and VCC. VCC 500Ω 100Ω CP1 CP2 Pin to connect a capacitor for charge pump. Connect a capacitor between CP1 and CP2.
No.A1416-13/15 3-phase Logic Truth Table (IN = “H” indicates the state where in IN+ > IN) F/R = H F/R = L Output IN1 IN2 IN3 IN1 IN2 IN3 OUT1 OUT2 OUT3 H L H L H L L H M H L L L H H L M H H H L L L H M L H L H L H L H H L M L H H H L L H M L L L H H H L M H L S/S Pin BRSEL Pin Input state Mode Input state While stopped High or Open Stop High or Open Free run Low Start Low Short-circuit brake CSDSEL Pin Input state Mode High or Open LD standard Low FG standard LV8111V Description 1. Speed Control Circuit This IC can realize a high efficiency, low-jitter, a stable rotation by adopting the PLL speed control method. This the PLL circuit compares the phase difference of the edge between the CLK signal and the FG signal and controls by using the output of error. The FG servo frequency under control becomes congruent with the CLK frequency. fFG (Servo) = fCLK 2. Output Drive Circuit This IC adopts the direct PWM drive method to reduce power loss in the output. Adjusts the driving force of the motor by changing on-duty of output transistor. The PWM switching of the output is performed by the upper-side output transistor. Also, this IC has a parasitic diode of the output DMOS as a regeneration route when the PWM switching is off. But, this IC is cut down the fever than the diode regeneration by performing synchronous rectification. 3. Current Limiter Circuit This IC limits the (peak) current at the value I = VRF / Rf (VRF = 0.515V (typical), Rf : current detection resister)). The current limitation operation consists of reducing the PWM output on duty to suppress the current. To prevent malfunction of the current limitation operation when the reverse recovery current of diode is detected, the operation has a delay (approximately 300ns). In case of a coil resistance of motor is small or small inductance, since the current change at start-up is fast, there is a possibility that the current more than specified current is flowed by this delay. It is necessary to set the current increases by the delay. 4. Power Saving Circuit This IC becomes the power saving state of decreasing the consumption current in the stop state. The bias current of the majority circuits is cut in the power saving state. Also, 5V regulator output is output in the power saving state. 5. Reference Clock Note that externally-applied clock signal has no noise of chattering. The input circuit has a hysteresis. But, if noise is a problem, that noise must be excluded by inserting capacitors across the inputs. If clock input goes to the no input state when the IC is in the start state, the drive is turned off after a few rotation of motor if the motor constrained protection circuit does operate. (Clock disconnection protection)
No.A1416-14/15 6. PWM Frequency The PWM frequency is determined by using a capacitor C (F) connected to the PWM pin. fPWM 1 / (29500 C ) … 150pF or more fPWM 1 / (32000 C ) … 100pF or more, less than 150pF The frequency is oscillated at about 225kHz when a capacitor of 150pF is connected. The GND of a capacitor must be placed as close to the control block GND (GND pin ) of the IC as possible to reduce influence of the output. 7. Hall Effect Sensor Input Signals The signal input of the amplitude of hysteresis of 42mV max or more is required in the Hall effect sensor inputs. Also, an input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs in view of influence of noise. If the output waveform (when the phase changes ) is distorted by noise, that noise must be excluded by inputting capacitors across the inputs. 8. FG Signals The Hall signal of IN1 is used as the FG signal in the IC. If noise is a problem, the noise of the FG signal can be excluded by inserting a capacitor between the FGFIL pin and GND. Note that normal operation becomes impossible if the value of the capacitor is overlarge. Also, note that the trouble of noise occurs easily when the position of GND of a capacitor is incorrect. 9. Constraint Protection Circuit This IC has an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. when the CSDSEL pin is set to the high level or open input, if the LD output remains high (unlocked statement) for a fixed period in the start state, this circuit operates. In the low level setting case, if the FG signal is not switched for a fixed period in the start state, this circuit is operates. Also, the upper-side output transistor is turned off while the constraint protection circuit is operating. This time is set by the capacitance of the capacitor attached to the CSD pin. The set time (in seconds) is 102 C (F) When a capacitor of 0.068F is attached, the protection time becomes about 7.0 seconds. The set time must be set well in advance for the motor start-up time. When the motor is decelerated by switching the clock frequency, this protection circuit is not operated. To clear the motor constrained state, the S/S pin is switched into a stop state or the power must be turned off and reapplied. Since the CSD pin also functions as the power-on reset pin, if the CSD pin were connected directly to ground, the logic circuit goes to the reset state and the speed cannot be controlled. Therefore, if the motor constraint protection circuit is not used, a resistor of about 220k and a capacitor of about 4700pF must be connected in parallel between the CSD pin and GND. 10. Phase Lock Signals (1) Phase lock range This IC has no the speed system counter. The speed error range in the phase lock state is indeterminable only by the characteristics of the IC. ( because the accelerations of the change in FG frequency influences.) When it is necessary to specify for the speed error as a motor, the value obtained while the motor is actually operating must be measured. Since the speed error occurs easily when the accelerations of FG is large, the speed error will be the largest when the IC goes into the lock state during start-up or the unlocked state by switching the clock. (2) Phase lock signal mask functions When the IC goes into the lock state during start-up or the unlocked state by switching the clock, the low signal for a short-time by using the hunting when the IC goes into the locked state is masked. Therefore, the lock signal is output in stable state. But, the mask time duration causes the delay of the lock signal output. The mask time is set by the capacitance of the capacitor attached between the CLD pin and GND. The mask time (seconds) is 1.8 C (F) When a capacitor of 0.1F is attached, the mask time becomes about 180ms. If the signals should be masked completely, the mask time must be set well in advance. When there is no need for masking, the CLD pin must be left open.
PS No.A1416-15/15 ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A lis ting of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended tosupport or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject t oa l l applicable copyright laws and is not for resale in any manner. 11. Power Supply Stabilization Since this IC is used in applications that draw large ou tput currents and adopts the drive method by switching, the power-Supply line is subject to fluctuations. Therefore, capacitors with capacitances adequate to stabilize the power-supply voltage must be connected between the V CC pin and GND. The ground-side a capacitor must be connected as close to the GND2 pin of power GND as possible. If it is impossible to connect a capacitor (electrolytic capacitor) near the pin, the ceramic capacitor of about 0.1F must be connected as close to the pin as possible. If diodes are inserted in the power-supply line to prevent IC destruction due to reverse power supply connection, Since this makes the power-supply voltage even more subject to fluctuations, even larger capacitors will be required. 12. VREG Stabilization To stabilize the VREG voltage that is the power supply of the control circuit, connect a capacitor of 0.1F or more. GND of the capacitor must be attached as close to the control block GND (GND1 pin) of the IC as possible. 13. Error Amplifier External components of the error amplifier block must be placed as close to the IC as possible to reduce influence of noise. Also, these components must be placed as separate from the motor as possible. 14. IC Reverse Metal To improve heat radiation, the metal part on the reverse of IC is stuck fast to the substrate by using highly-conduction solder. 15. SDCC (Speed Detection Current Control) function The SDCC circuit controls the speed detection current. It limits the current to 75% of the specified current to reduce acceleration of the motor when the rotation of the motor exceeds 95% of its target speed. This enables stabilized phase lock pull-in and minimizes the variation in startup time.
ORDERING INFORMATION
Device Package Shipping (Qty / Packing) LV8111V-TLM-E SSOP44K(275mil) EP (Pb-Free / Halogen Free) 2000 / Tape & Reel