L6599 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 36
Technical content
Datasheet sections
- 1 Device description
- 2 Pin Settings
- 2.1 Connection
- 2.2 Functions
- 3 Typical system block diagram
- 4 Electrical data
- 4.1 Maximum ratings
- 4.2 Thermal data
- 5 Electrical characteristics
- 6 Typical electrical performance
- 7 Application information
- 7.1 Oscillator
- 7.2 Operation at no load or very light load
- 7.3 Soft-start
- 7.4 Current sense, OCP and OLP
- 7.5 Latched shutdown
- 7.6 Line sensing function
- 7.7 Bootstrap section
- 7.8 Application example
- 8 Package mechanical data
- 9 Revision history
Features
■ 50% duty cycle, variable frequency control of resonant half-bridge ■ High-accuracy oscillator ■ Up to 500kHz operating frequency ■ Two-level OCP: frequency-shift and latched shutdown ■ Interface with PFC controller ■ Latched disable input ■ Burst-mode operation at light load ■ Input for power-ON/OFF sequencing or brownout protection ■ Non-linear soft-start for monotonic output voltage rise ■ 600V-rail compatible high-side gate driver with integrated bootstrap diode and high dV/dt immunity ■ -300/800mA high-side and low-side gate drivers with UVLO pull-down ■ DIP-16, SO-16N packages
Applications
■ LCD & PDP TV ■ Desktop PC, entry-level server ■ Telecom SMPS ■ AC-DC adapter, open frame SMPS Order code Part number Package Packaging L6599D SO-16N Tube L6599TR SO-16N Tape and reel L6599N DIP-16 Tube DIP-16 SO-16N Block diagram STANDBY DI S ISEN_DIS GND Ifmin ISEN 0.8V 1.5V PFC_STOP Vcc VBOOT OUT CBOOT LC TANK CIRCUIT H.V. LV G UV DETECTION Vs HVG SYNCHRONOUS BOOTSTRAP DIODE HVG DRIVER L VG DRIVER Css CF DISABLE DIS LINE DEAD TIME LEVEL SHIFTER RFmin 1.85V S Q R UVLO UVLO Q S R UVLO CONTROL LOGIC - LI NE_OK1.25V µA DIS ISEN _D IS 17V 6.3V VCO +1.25V STANDBY STBY 5 DRIVING LOGIC DELAY
1 Device description
The L6599 is a double-ended controller specific for the resonant half-bridge topology. It provides 50% complementary duty cycle: the high-side switch and the low-side switch are driven ON 180° out-of-phase for exactly the same time. Output voltage regulation is obtained by modulating the operating frequency. A fixed dead- time inserted between the turn-OFF of one switch and the turn-ON of the other one guarantees soft-switching and enables high-frequency operation. To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage floating structure able to withstand more than 600V with a synchronous-driven high-voltage DMOS that replaces the external fast-recovery bootstrap diode. The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator. At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non linear to minimize output voltage overshoots; its duration is programmable as well. The IC can be forced to enter a controlled burst-mode operation at light load, so as to keep converter's input consumption to a minimum. IC's functions include a not-latched active-low disable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for OCP with frequency shift and delayed shutdown with automatic restart. A higher level OCP latches off the IC if the first-level protection is not sufficient to control the primary current. Their combination offers complete protection against overload and short circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or OVP. An interface with the PFC controller is provided that enables to switch off the pre-regulator during fault conditions, such as OCP shutdown and DIS high, or during burst-mode operation.
2 Pin Settings
2.1 Connection
Figure 1. Pin Connection (Top view)
2.2 Functions
Table 1. Pin functions current sense pin (ISEN) exceeds 0.8V, as long as it stays above 0.75V. intermittently with very low input average power. and determines the switching frequency of the converter.
prevent excessive energy inrush (soft-start). restarts switching as the voltage exceeds the reference by 50mV. Soft-start is not invoked. block diagram). Tie the pin to RFmin if burst-mode is not used.
6 ISEN
soft-start capacitor. IC’s operation is re-enabled (soft-started) as the voltage exceeds 1.25V. as long as the voltage applied at the pin is below 1.25V and is OFF if this value is exceeded. latched). Bias the pin between 1.25 and 6V if the function is not used. the UVLO threshold. Tie the pin to GND if the function is not used. low when the IC is shut down by DIS > 1.85V, ISEN > 1.5V, LINE > 6V and STBY < 1.25V.
10 GND
to this pin and kept separate from any pulsed current return.
3 Typical system block diagram
Figure 2. Typical system block diagram
11 LVG
12 V CC
ease compliance with safety regulations (creepage distance) on the PCB. 14 OUT High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground.
15 HVG
connected to pin 14 (OUT) ensures that the pin is not floating during UVLO.
16 VBOOT
4 Electrical data
4.1 Maximum ratings
4.2 Thermal data
Table 2. Absolute maximum ratings Table 3. Thermal data
5 Electrical characteristics
RRFmin = 12kΩ; unless otherwise specified. Table 4. Electrical characteristics
- Values traking each other
6 Typical electrical performance
Figure 3. Device consumption vs Figure 4. IC consumption vs Figure 5. V CC clamp voltage vs Figure 6. UVLO thresholds vs
7 Application information
enable high-frequency operation with high efficiency and low EMI emissions.
- Variable frequency at heavy and medium/ light load. A relaxation oscillator (see
- Burst-mode control with no or very light load. When the load falls below a value, the
related losses and making it easier to comply with energy saving recommendations. Figure 20. Multi-mode operation
7.1 Oscillator
circuit that explains the operation.
- A resistor RF min connected between the pin and ground that determines the minimum
- A resistor RF max connected between the pin and the collector of the (emitter-grounded)
- An R-C series circuit (C SS + RSS) connected between the pin and ground that enables
contribution of this branch is zero during steady-state operation. Figure 21. Oscillator's internal block diagram.
will be used (see "Operation at no load or very light load" section). Figure 22. Oscillator waveforms and their relationship with gate-driving signals charged and ready to supply the high-side floating driver.
7.2 Operation at no lo ad or very light load
facilitating the converter to comply with energy saving recommendations. input voltage range (e.g. when there is a PFC front-end). Figure 23. Burst-mode implementation: narrow input voltage range. Figure 24. Burst-mode implementation: wide input voltage range.
Essentially, RFmax will define the switching frequency fmax above which the L6599 will enter burst-mode operation. Once fixed fmax, RFmax will be found from the relationship: Note that, unlike the fmax considered in the previous section ("Chapter 7.1: Oscillator"), here fmax is associated to some load PoutB greater than the minimum one. PoutB will be such that the transformer's peak currents are low enough not to cause audible noise. Resonant converter's switching frequency, however, depends also on the input voltage; hence, in case there is quite a large input voltage range with the circuit of Figure 23 the value of PoutB would change considerably. In this case it is recommended to use the arrangement shown in Figure 24 where the information on the converter's input voltage is added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship between switching frequency and input voltage, it is more practical to find empirically the right amount of correction R A / (RA + RB) needed to minimize the change of PoutB. Just be careful in choosing the total value RA + RB much greater than RC to minimize the effect on the LINE pin voltage (see Chapter 7.6: Line sensing function). Whichever circuit is in use, its operation can be described as follows. As the load falls below the value PoutB the frequency will try to exceed the maximum programmed value fmax and the voltage on the STBY pin (VSTBY) will go below 1.25V. The IC will then stop with both gate-drive outputs low, so that both MOSFETs of the half-bridge leg are in OFF-state. The voltage V STBY will now increase as a result of the feedback reaction to the energy delivery stop and, as it exceeds 1.3V, the IC will restart switching. After a while, VSTBY will go down again in response to the energy burst and stop the IC. In this way the converter will work in a burst-mode fashion with a nearly constant switching frequency. A further load decrease will then cause a frequency reduction, which can go down even to few hundred hertz. The timing diagram of Figure 25 illustrates this kind of operation, showing the most significant signals. A small capacitor (typically in the hundred pF) from the STBY pin to ground, placed as close to the IC as possible to reduce switching noise pick-up, will help get clean operation. To help the designer meet energy saving requirements even in power-factor-corrected systems, where a PFC pre-regulator precedes the DC-DC converter, the device allows that the PFC pre-regulator can be turned off during burst-mode operation, hence eliminating the no-load consumption of this stage (0.5 ÷ 1W). There is no compliance issue in that because EMC regulations on low-frequency harmonic emissions refer to nominal load, no limit is envisaged when the converter operates with light or no load. To do so, the device provides pin 9 (PFC_STOP): it is an open collector output, normally open, that is asserted low when the IC is idle during burst-mode operation. This signal will be externally used for switching off the PFC controller and the pre-regulator as shown in Figure 26 When the L6599 is in UVLO the pin is kept open, to let the PFC controller start first. RFmax 8--- RFmin fmax fmin
7.3 Soft-start
sweeping the operating frequency from an initial high value until the control loop takes over. min) to ground (see Figure 27). phototransistor to determine the operating frequency from that moment onwards. Figure 27. Soft-start circuit
Figure 28. Power vs frequency curve in an resonant half-bridge significant signals during the soft-start phase.
7.4 Current sense, OCP and OLP
will only serve as an overcurrent protection (OCP). from reaching too high values. complex but virtually lossless and recommended when the efficiency target is very high. Figure 29. Current sensing technique with sense resistor
Figure 30. Lossless current sensing technique, with capacitive shunt operation results in a nearly constant peak primary current.
The circuit shown in Figure 30 can be operated in two different ways. If the resistor RA in series to CA is small (not above some hundred Ω, just to limit current spiking) the circuit operates like a capacitive current divider; CA will be typically selected equal to CR/100 or less and will be a low-loss type, the sense resistor RB will be selected as: and CB will be such that RB·CB is in the range of 10 /fmin. If the resistor RA in series to CA is not small (in this case it will be typically selected in the ten kΩ ), the circuit operates like a divider of the ripple voltage across the resonant capacitor Cr, which, in turn, is related to its current through the reactance of Cr. Again, CA will be typically selected equal to CR/100 or less, this time not necessarily a low-loss type, while RB (provided it is << RA) according to: where the reactance of CA (XCA) and CR (XCr) should be calculated at the frequency where ICrpk = ICrpkx. Again, CB will be such that RB·CB is in the range of 10 /fmin. Whichever circuit one is going to use, the calculated values of RS or RB should be considered just a first cut value that needs to be adjusted after experimental verification. OCP is effective in limiting primary-to-secondary energy flow in case of an overload or an output short circuit, but the output current through the secondary winding and rectifiers under these conditions might be so high to endanger converter's safety if continuously flowing. To prevent any damage during these conditions it is customary to force converter's intermittent operation, in order to bring the average output current to values such that the thermal stress for the transformer and the rectifiers can be easily handled. With the L6599 the designer can program externally the maximum time T SH that the converter is allowed to run overloaded or under short circuit conditions. Overloads or short circuits lasting less than T SH will not cause any other action, hence providing the system with immunity to short duration phenomena. If, instead, TSH is exceeded an overload protection (OLP) procedure is activated that shuts down the device and, in case of continuous overload/short circuit, results in continuous intermittent operation with a user- defined duty cycle. RB 0.8π ICrpkx CA ⎛⎞= RB 0.8π ICrpkx RA
2 XCA
Figure 31. Soft-start and delayed shutdown upon overcurrent timing diagram This operation will go on until the voltage on CDelay reaches 2V, which defines the time TSH. close to fstart (see Chapter 7.3: Soft-start) to minimize the energy inside the resonant circuit.
The timing diagram of Figure 31 shows this operation. Note that if during TSTOP the supply voltage of the L6599 (Vcc) falls below the UVLO threshold the IC keeps memory of the event and will not restart immediately after VCC exceeds the start-up threshold if V(DELAY) is still higher than 0.3V. Also the PFC_STOP pin will stay low as long as V(DELAY) is greater than 0.3V. Note also that in case there is an overload lasting less than TSH, the value of TSH for the next overload will be lower if they are close to one another.
7.5 Latched shutdown
The device is equipped with a comparator having the non-inverting input externally available at pin 8 (DIS) and with the inverting input internally referenced to 1.85V. As the voltage on the pin exceeds the internal threshold, the IC is immediately shut down and its consumption reduced at a low value. The information is latched and it is necessary to let the voltage on the Vcc pin go below the UVLO threshold to reset the latch and restart the IC. This function is useful to implement a latched overtemperature protection very easily by biasing the pin with a divider from an external reference voltage, where the upper resistor is an NTC physically located close to a heating element like the MOSFET, or the secondary diode or the transformer. An OVP can be implemented as well, e.g. by sensing the output voltage and transferring an overvoltage condition via an optocoupler.
7.6 Line sensing function
This function basically stops the IC as the input voltage to the converter falls below the specified range and lets it restart as the voltage goes back within the range. The sensed voltage can be either the rectified and filtered mains voltage, in which case the function will act as a brownout protection, or, in systems with a PFC pre-regulator front-end, the output voltage of the PFC stage, in which case the function will serve as power-on and power-off sequencing. L6599 shutdown upon input undervoltage is accomplished by means of an internal comparator, as shown in the block diagram of Figure 32, whose non-inverting input is available at pin 7 (LINE). The comparator is internally referenced to 1.25V and disables the IC if the voltage applied on the LINE pin is below the internal reference. Under these conditions the soft-start is discharged, the PFC_STOP pin is open and the consumption of the IC is reduced. PWM operation is re-enabled as the voltage on the pin is above the reference. The comparator is provided with current hysteresis instead of a more usual voltage hysteresis: an internal 1 µA current sink is ON as long as the voltage on the LINE pin is below the reference and is OFF if the voltage is above the reference. This approach provides an additional degree of freedom: it is possible to set the ON threshold and the OFF threshold separately by properly choosing the resistors of the external divider (see below). With voltage hysteresis, instead, fixing one threshold automatically fixes the other one depending on the built-in hysteresis of the comparator.
Figure 32. Line sensing function: internal block diagram and timing diagram thresholds, as shown in the timing diagram of Figure 32.
the UVLO threshold, the IC will restart as the voltage falls below 7V. lower than 6V (worst-case value of the 7V threshold).
7.7 Bootstrap section
The supply of the floating high-side section is obtained by means of a bootstrap circuitry. BOOT. In the L6599 a patented integrated structure, replaces this external diode. Figure 33. Bootstrap supply: internal bootstrap synchronous diode supply is quickly turned off when the internal capacitor of the pump is not fully discharged. CC. This voltage is obtained by means of an internal charge pump (Figure 33). external high-side MOSFET and then its conductive loss.
14 OUT
16 VBOOTVcc 12
Application information L6599 This concern applies to converters designed with a high resonance frequency (indicatively, > 150 kHz), so that they run at high frequency also at full load. Otherwise, the converter will run at high frequency only at light load, where the current flowing in the MOSFETs of the half-bridge leg is lower, so that, generally, an r (DS)ON rise is not an issue. However, it is wise to check this point anyway and the following equation is useful to compute the drop on the bootstrap driver: where Q g is the gate charge of the external power MOS, r(DS)ON is the on-resistance of the bootstrap DMOS (150 , typ.) and Tcharge is the ON-time of the bootstrap driver, which equals about half the switching period minus the dead time TD. For example, using a MOSFET with a total gate charge of 30nC, the drop on the bootstrap driver is about 3V at a switching frequency of 200kHz: If a significant drop on the bootstrap driver is an issue, an external ultra-fast diode can be used, thus saving the drop on the r (DS)ON of the internal DMOS. VDrop ICh earg r DS() ON VF Qg TCh earg VDrop 30 10 9–⋅
7.8 Application example
Figure 34. EVAL6599-90W demo board, 90W adapter with L6563 & L6599: electrical schematic
Table 5. EVAL6599-90W demo board, 90W adapter with L6563 & L6599: evaluation Vout Iout Pout Pin Eff. Vout Iout Pout Pin Eff.
8 Package mechanical data
conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 6. Plastic DIP-16 mechanical data Figure 35. Plastic DIP-16 package dimensions
Figure 36. Package dimensions Table 7. SO16N mechanical data
9 Revision history
Table 8. Revision history