LB1847

LB1847 ONSEMI | Alldatasheet

Document overview

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• PDF pages: 15

Technical content

Features

• PWM current control (fixed OFF time)
• Load current digital selector (1-2, W1-2, 2W1-2, 4W1-2 phase exciter drive possible)
• Selectable current decay pattern (SLOW DECAY, FAST DECAY, MIX DECAY)
• Simultaneous ON prevention function (feed-through current prevention)
• Noise canceler
• Built-in thermal shutdown circuit
• Built-in logic low-voltage OFF circuit Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Motor supply voltage V BB 50 V Output peek current I O peak t W = 20μs 1.75 A Output continuous current I O max 1.5 A Logic supply voltage V CC 7.0 A Logic input voltage range V IN -0.3 to VCC V Emitter output voltage V E 1.0 V Independent IC 3.0 W Allowable power dissipation Pd max With infinitely large heat sink 20 W Operating temperature Topr -20 to +85 °C Storage temperature Tstg -55 to +150 °C Monolithic Digital IC PWM Current Control Type Stepping Motor Driver Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Oper ating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No.5982-2/15 Allowable Operating Ranges at Ta = 25°C Parameter Symbol Conditions Ratings Unit Motor supply voltage range V BB 10 to 45 V Logic supply voltage V CC 4.75 to 5.25 V Reference voltage range V REF 0.0 to 3.0 V Electrical Characteristics at Ta = 25°C, VBB = 45V, VCC = 5V, VREF = 1.52V Ratings Parameter Symbol Conditions min typ max Unit Output Block IBB ON 2.3 3.5 5.0 mA Output stage supply voltage IBB OFF 0.5 0.8 1.1 mA VO(sat)1 I O = +1.0A, sink 1.2 1.6 V VO(sat)2 I O = +1.5A, sink 1.5 1.9 V VO(sat)3 I O = -1.0A, source 1.9 2.2 V Output saturation voltage VO(sat)4 I O = -1.5A, source 2.2 2.4 V IO(leak)1 V O = VBB, sink 50 μA Output leak current IO(leak)2 V O = 0V, source -50 μA Output sustain voltage V SUS L = 15mH, I O = 1.5A, Guaranteed design value * 45 V Logic Block ICC OFF ENABLE = 3.2V 10.5 15 19.5 mA VIH 3.2 V Input voltage VIL 0.8 V IIH V IH = 3.2V 100 μA Input current IIL V IL = 0.8V -10 μA Sensing voltage V E Reference current I REF V REF = 1.5V -0.5 μA CR pin current I CR CR = 1.0V -4.6 -1.0 mA MD pin current I MD MD = 1.0V, CR = 4.0V -5.0 μA DECAY pin current Low I DECL V DEC = 0.8V -10 μA DECAY pin current High I DECH V DEC = 3.2V 5 μA Thermal shutdown temperature TSD 170 °C Logic ON voltage L VSD1 3.35 3.65 3.95 V Logic OFF voltage L VSD2 3.20 3.50 3.80 V LVSD hysteresis width ΔLVSD 0.065 0.15 0.23 V

No.5982-3/15 Package Dimensions unit : mm (typ) 3147C -20 0 20 40 60 80 1000 Pd max -- Ta 1.56 10.4 Ambient temperature, Ta -- °C Allowable power dissipation, Pd max -- W Independent IC With infinitely large heat sink Pin Assignment Top view1 2 3 4 5 6 7 8 9 10 11 12 13 14 MD VREF1 CR1 DECAY1 OUYA OUYA OUYB OUYB DECAY2 CR2 VREF2 VBB 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PHASE1 ENABLE1 IA1 IA2 IA3 IA4 IB4 IB3 IB2 IB1 ENABLE2 PHASE2 GND LB1847 SANYO : DIP28H(500mil) 1 14 28 15 0.4 0.6 4.04.0 26.75 20.0 R1.7 8.4 (1.81) 1.78 1.0 12.7 11.2

No.5982-4/15 Block Diagram OUTA OUTA OUTB OUTBVBB MD PHASE1 DECAY1 ENABLE1 IA1 IA2 IA3 IA4 VREF1 GND PHASE2 DECAY2 ENABLE2 IB1 IB2 IB3 IB4 VREF2 VCC CR1 E1 CR2E2 Control logic circuit Control logic circuit Thermal shutdown circuit Current selector circuit Current selector circuit One-shot multi- blanking time One-shot multi- blanking time

No.5982-5/15 Pin Function Pin No. Pin name Function 1 MD Sets the OFF time for FAST mode and SLOW mode in MIX DECAY. Setting input range: 4V to 1.5V. VREF1 VREF2 Output set current reference supply pin. Setting voltage range: 0V to 3V. CR1 CR2 Output OFF time setting pin for switching operation. Pin for controlling the set current with sensing resistor RE. DECAY1 DECAY2 SLOW mode/FAST mode selector pin. DECAY2 SLOW DECAY: H FAST DECAY: L OUTA OUTA OUTB OUTB Output pin. 14 V BB Output stage supply voltage pin. 15 GND Ground pin. PHASE1 PHASE2 Output phase selector input pin ENABLE1 ENABLE2 Output ON/OFF setting input pin. 22,23 24,25 21,20 19,18 IA4,IA3 IA2,IA1 IB4,IB3 IB2,IB1 Output set current digital input pin. 15-stage voltage setting.

28 V CC Logic block supply voltage pin

− H OFF OFF Set Current Truth Table IA4 I A3 I A2 I A1 Set current Iout Current ratio 1 1 1 1 11.5/11.5 × VREF/3.04RE = Iout 100 1 1 1 0 11.0/11.5 × VREF/3.04RE = Iout 95.65 1 1 0 1 10.5/11.5 × VREF/3.04RE = Iout 91.30 1 1 0 0 10.0/11.5 × VREF/3.04RE = Iout 86.95 1 0 1 1 9.5/11.5 × VREF/3.04RE = Iout 82.61 1 0 1 0 9.0/11.5 × VREF/3.04RE = Iout 78.26 1 0 0 1 8.5/11.5 × VREF/3.04RE = Iout 73.91 1 0 0 0 8.0/11.5 × VREF/3.04RE = Iout 69.56 0 1 1 1 7.0/11.5 × VREF/3.04RE = Iout 60.87 0 1 1 0 6.0/11.5 × VREF/3.04RE = Iout 52.17 0 1 0 1 5.0/11.5 × VREF/3.04RE = Iout 43.48 0 1 0 0 4.0/11.5 × VREF/3.04RE = Iout 34.78 0 0 1 1 3.0/11.5 × VREF/3.04RE = Iout 26.08 0 0 1 0 2.0/11.5 × VREF/3.04RE = Iout 17.39 * Current ratio (%) is the calculated set current value. Current Decay Switching Truth Table Current decay mode DECAY pin MD pin Output chopping SLOW DECAY H L Upper-side chopping FAST DECAY L L Dual-side chopping MIX DECAY L 4V to 1.5V input voltage setting CR voltage > MD: dual-side chopping CR voltage < MD: upper-side chopping

No.5982-6/15 Sequence Table Phase A Phase B No. I A4 I A3 I A2 I A1 ENA1 PHA1 Iout I B4 I B3I B2I B1 ENA2 PHA2 Iout Phase 1-2 Phase W1-2 Phase 2W1-2 Phase 4W1-2 0 1 1 1 1 0 0 100% 0 0 1 0 1 * 0% { { { { 1 1 1 1 1 0 0 100 0 0 1 0 0 0 17.39 { 2 1 1 1 1 0 0 100 0 0 1 1 0 0 26.08 { { 3 1 1 1 0 0 0 95.65 0 1 0 0 0 0 34.78 { 4 1 1 0 1 0 0 91.30 0 1 0 1 0 0 43.48 { { { 5 1 1 0 0 0 0 86.95 0 1 1 0 0 0 52.17 { 6 1 0 1 1 0 0 82.61 0 1 1 1 0 0 60.87 { { 7 1 0 1 0 0 0 78.26 1 0 0 0 0 0 69.56 { 8 1 0 0 1 0 0 73.91 1 0 0 1 0 0 73.91 { { { { 9 1 0 0 0 0 0 69.56 1 0 1 0 0 0 78.26 { 10 0 1 1 1 0 0 60.87 1 0 1 1 0 0 82.61 { { 11 0 1 1 0 0 0 52.17 1 1 0 0 0 0 86.95 { 12 0 1 0 1 0 0 43.48 1 1 0 1 0 0 91.30 { { { 13 0 1 0 0 0 0 34.78 1 1 1 0 0 0 95.65 { 14 0 0 1 1 0 0 26.08 1 1 1 1 0 0 100 { { 15 0 0 1 0 0 0 17.39 1 1 1 1 0 0 100 { 16 0 0 0 1 1 * 0 1 1 1 1 0 0 100 { { { { 17 0 0 1 0 0 1 17.39 1 1 1 1 0 0 100 { 18 0 0 1 1 0 1 26.08 1 1 1 1 0 0 100 { { 19 0 1 0 0 0 1 34.78 1 1 1 0 0 0 95.65 { 20 0 1 0 1 0 1 43.48 1 1 0 1 0 0 91.30 { { { 21 0 1 1 0 0 1 52.17 1 1 0 0 0 0 86.95 { 22 0 1 1 1 0 1 60.87 1 0 1 1 0 0 82.61 { { 23 1 0 0 0 0 1 69.56 1 0 1 0 0 0 78.26 { 24 1 0 0 1 0 1 73.91 1 0 0 1 0 0 73.91 { { { { 25 1 0 1 0 0 1 78.26 1 0 0 0 0 0 69.56 { 26 1 0 1 1 0 1 82.61 0 1 1 1 0 0 60.87 { { 27 1 1 0 0 0 1 86.95 0 1 1 0 0 0 52.17 { 28 1 1 0 1 0 1 91.30 0 1 0 1 0 0 43.48 { { { 29 1 1 1 0 0 1 95.65 0 1 0 0 0 0 34.78 { 30 1 1 1 1 0 1 100 0 0 1 1 0 0 26.08 { { 31 1 1 1 1 0 1 100 0 0 1 0 0 0 17.39 { * Don’t care Note: Iout percentage (%) is the calculated setting value.

No.5982-7/15 E pin Output pin RC pin Output pin Switching waveform Noise spike Switch Timing Chart During PWM Drive SLOW DECAY (upper-side chopping) DECAY pin: High MD pin: Low tn E pin Output pin RC pin Output pin Switching waveform FAST DECAY DECAY pin: Low MD pin: Low

No.5982-8/15 MIX DECAY tm tn toff ton E pin Output pin RC pin Output pin Switching waveform Noise spike ton : Output ON time toff : Output OFF time tm : FAST DECAY time in MIX DECAY mode tn : Noise cancelling time MIX DECAY logic setting DECAY pin : L MD pin : 1.5V to 4.0V voltage setting CR voltage and MD pin voltage are compared to select dual-side chopping or upper-side chopping. CR voltage > MD pin voltage: dual-side chopping CR voltage < MD pin voltage: upper-side chopping

No.5982-9/15 SLOW DECAY Current Path Regenerative current during upper-side transistor switching operation ON OUTA SBDSBD Re VBB OFF OUTA ON constant Sensing voltage comparator Regenerative current at upper-side transistor OFF Current path at output ON FAST DECAY Current Path ON ON OFF OUTA SBDSBD Re OUTA VBB OFF Sensing voltage comparator Current path at output ON Current path at FAST DECAY

No.5982-10/15 Composite Spectrum of Set Current (1 step normalized to 90°) 16 15 14 IOUT IOUT Phase A Phase B Sequence No. No. θ Rotation angle Composite spectrum 0 θ0 0 ° 100.0 1 θ1 9.87 ° 101.5 2 θ2 14.6 ° 103.35 3 θ3 20.0 ° 101.78 4 θ4 25.5 ° 101.12 5 θ5 30.96 ° 101.4 6 θ6 36.38 ° 102.61 7 θ7 41.63 ° 104.7 8 θ8 45.0 ° 104.5 9 θ9 48.37 ° 104.7 10 θ10 53.62 ° 102.61 11 θ11 59.04 ° 101.4 12 θ12 64.5 ° 101.12 13 θ13 70.0 ° 101.78 14 θ14 75.4 ° 103.35 15 θ15 80.13 ° 101.5 16 θ16 90.0 ° 100.0 * Rotation angle and composite spectrum are calculated values.

No.5982-11/15 Set Current Waveform Model IOUT IOUT PHASE1 PHASE2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Phase A Phase B

No.5982-12/15 Sample Application Circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VREF1 CR1 DECAY1 OUYA OUYA OUYB OUYB DECAY2 CR2 VREF2 VBB 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PHASE1 ENABLE1 IA1 IA2 IA3 IA4 IB4 IB3 IB2 IB1 ENABLE2 PHASE2 GND LB1847 MD SBD SBD SBD SBD LL 0.51Ω 0.51Ω 15kΩ 470pF 15kΩ 470pF 42V 47μF 1.5V to 4.0V voltage setting 1.5V 5V10μF Logic input Notes on Usage 1. External diodes Because this IC uses upper-side transistor switching in SLOW DECAY mode and dual-side transistor switching in FAST DECAY mode, it requires external diodes between the OUT pins and ground, for the regenerative current during switching OFF. Use Schottky barrier diodes with low VF. 2. VREF pin Because the VREF pin serves for input of the set current reference voltage, precautions against noise must be taken. The input voltage range is 0 to 3.0V. 3. GND pin The ground circuit for this IC must be designed so as to allow for high-current switching. Blocks where high current flows must use low-impedance patterns and must be removed from small-signal lines. Especially the ground connection for the sensing resistor RE at pin E, and the ground connection for the Schottky barrier diodes should be in close proximity to the IC ground. The capacitors between VCC and ground, and VBB and ground should be placed close to the VCC and VBB pins, respectively.

No.5982-14/15 Switching OFF time and CR setting range (toff time : approx. 8 to 100μs) 50k 100k 1000 2000 3000 toff time : 30μs toff time : 50μs toff time : 100μs C [pF] R [Ω]

PS No.5982-15/15 ICC -- VCC IBB -- VBB VO(sat) -- IO VO(sat) -- IO 01 2 3 4 5 6 7 0 1 02 03 04 05 06 0 2.8 2.0 1.6 1.2 0.4 0.8 2.4 2.8 2.0 1.6 1.2 0.4 0.8 2.4 Logic supply current, ICC -- mA Input logic voltage: IA1,2,3,4 PHA,ENA = VCCtyp. Input logic voltage: IA1,2,3,4 PHA,ENA = VCCtyp. Output ON Output OFF Logic supply voltage, VCC -- mV Output stage supply current voltage, VBB -- V Output stage supply current, IBB -- mA Output ON Output OFF Output current, IO -- A Output current, I O -- A Output saturation voltage, VO(sat) -- V Output saturation voltage, VO(sat) -- V Sink side [typ.] Source side [typ.] 2.4 ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s techn ical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC productsfor any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, anddistributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture oft h e part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.