LB15JG

IDT72205LB RENESAS | Alldatasheet

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IDT72205LB, IDT72215LB, IDT72225LB, IDT72235LB, IDT72245LB IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ©2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2766/4 CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES:

• •••• 256 x 18-bit organization array (IDT72205LB)
• •••• 512 x 18-bit organization array (IDT72215LB)
• •••• 1,024 x 18-bit organization array (IDT72225LB)
• •••• 2,048 x 18-bit organization array (IDT72235LB)
• •••• 4,096 x 18-bit organization array (IDT72245LB)
• •••• 10 ns read/write cycle time
• •••• Empy and Full flags signal FIFO status
• •••• Easy expandable in depth and width
• •••• Asynchronous or coincident read and write clocks
• •••• Programmable Almost-Empty and Almost-Full flags with default settings
• •••• Half-Full flag capability
• •••• Dual-Port zero fall-through time architecture
• •••• Output enable puts output data bus in high-impedence state
• •••• High-performance submicron CMOS technology
• •••• Available in a 64-lead thin quad flatpack (TQFP/STQFP) and plastic leaded chip carrier (PLCC)
• •••• Industrial temperature range (–40°°°°°C to +85°°°°°C) is available
• •••• Green parts available, see ordering information DESCRIPTION: The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high speed, low-power First-In, First-Out (FIFO) memories with clocked read and FUNCTIONAL BLOCK DIAGRAM INPUT REGISTER OUTPUT REGISTER RAM ARRAY 256 x 18, 512 x 18 1,024 x 18, 2,048 x 18 4,096 x 18 OFFSET REGISTER FLAG LOGIC READ POINTER READ CONTROL LOGIC WRITE CONTROL LOGIC WRITE POINTER EXPANSION LOGIC RESET LOGIC WCLK D0-D17 RCLK Q0-Q17 2766 drw 01 write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and another enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output. The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF), and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO is used in a single device configuration. These devices are depth expandable using a Daisy-Chain technique. The XI and XO pins are used to expand the FIFOs. In depth expansion configu- ration, First Load (FL) is grounded on the first device and set to HIGH for all other devices in the Daisy Chain. The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated using high-speed submicron CMOS technology.

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2013 PIN CONFIGURATIONS PLCC (J68-1, order code: J) TOP VIEW TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW VCC Q14 Q13 GND Q12 Q11 VCC Q10 GND VCC GND D14 D13 D12 D11 D10 VCC GND 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 2766 drw 02 D15 D16 VCC D17 GND RCLK REN LD OE RS GND EF V CC Q17 Q16 GND Q15 PAE FL WCLK WEN WXI VCC PAF RXI FF WXO/HF RXO GND VCC PIN 1 D16 D17 GND RCLK VCC GND Q17 Q16 GND Q15 VCC Q14 Q13 GND Q12 Q11 VCC Q10 GND GND VCC D D14 D13 D12 D11 D10 WCLK VCC GND 64 63 62 6160 59 58 57 56 5554 53 5251 50 49 17 18 19 20 21 22 2324 25 26 27 28 29 30 31 32 2766 drw 03

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2013 PIN DESCRIPTION Symbol Name I/O Description D0–D17 Data Inputs I Data inputs for a 18-bit bus. RS Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. WCLK Write Clock I When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full. WEN Write Enable I When WEN is LOW and LD is HIGH, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW. RCLK Read Clock I When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty. REN Read Enable I When REN is LOW, and LD is HIGH, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW. OE Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. LD Load I When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW. FL First Load I In the single device or width expansion configuration, FL is grounded. In the depth expansion configuration, FL is grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain. WXI Write Expansion I In the single device or width expansion configuration, WXI is grounded. In the depth expansion configuration, WXI is connected to WXO (Write Expansion Out) of the previous device. RXI Read Expansion I In the single device or width expansion configuration, RXI is grounded. In the depth expansion configuration, RXI is connected to RXO (Read Expansion Out) of the previous device. FF Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. PAE Programmable O When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default Almost-Empty Flag offset at reset is 31 from empty for IDT72205LB, 63 from empty for IDT72215LB, and 127 from empty for IDT72225LB/72235LB/72245LB. PAF Programmable O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset at Almost-Full Flag reset is 31 from full for IDT72205, 63 from full for IDT72215LB, and 127 from full for IDT72225LB/72235LB/ 72245LB. WXO/HF Write Expansion O In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the Out/Half-Full Flag depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the FIFO is written. RXO Read Expansion O In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last Out location in the FIFO is read. Q0–Q17 Data Outputs O Data outputs for an 18-bit bus. VCC Power +5V power supply pins. GND Ground Eight ground pins for the PLCC and seven gound pins for the TQFP/STQFP.

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2013 RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V Commercial/Industrial GND Supply Voltage 0 0 0 V V IH Input High Voltage 2.0 — — V Commercial/Industrial VIL(1) Input Low Voltage — — 0.8 V Commercial/Industrial TA Operating Temperature 0 — 70 °C Commercial TA Operating Temperature -40 ⎯ 85 °C Industrial NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. Symbol Rating Commercial Unit VTERM Terminal Voltage –0.5 to +7.0 V with respect to GND TSTG Storage –55 to +125 °C Temperature IOUT DC Output Current –50 to +50 mA Symbol Parameter (1) Conditions Max. Unit CIN(2) Input V IN = 0V 10 pF Capacitance COUT(1,2) Output V OUT = 0V 10 pF Capacitance CAPACITANCE (TA = +25°C, f = 1.0MHz) NOTES: 1. With output deselected, ( OE ≥ V IH). 2. Characterized values, not currently tested. IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB Commercial and Industrial (1) tCLK = 10, 15, 25 ns Symbol Parameter Min. Typ. Max. Unit ILI(2) Input Leakage Current (any input) –1 — 1 µA ILO(3) Output Leakage Current –10 — 10 µA VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — V VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 V ICC1(4,5,6) Active Power Supply Current — — 60 mA DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%V, TA = -40°C to +85°C) NOTES: 1. Industrial Temperature Range Product for the 15ns and the 25ns speed grades are available as a standard device. 2. Measurements with 0.4 ≤ V IN ≤ V CC. 3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 4. Tested with outputs disabled (I OUT = 0). 5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz. 6. For the IDT72205/72215/72225 the typical I CC1 = 1.81 + 1.12*f S + 0.02*C L*fS (in mA); for the IDT72235/72245 the typical I CC1 = 2.85 + 1.30*f S + 0.02*C L*fS (in mA) These equations are valid under the following conditions: VCC = 5V, T A = 25 °C, f S = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f S/2, C L = capacitive load (in pF). 7. All Inputs = V CC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz. ABSOLUTE MAXIMUM RATINGS NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ICC2(4,7) Standby Current — — 5 mA

Figure 1. Output Load

• Includes jig and scope capacitances.

1. Industrial temperature range product for the 15ns and the 25ns speed grades are available as a standard device. All other s peed grades are available by special order.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MARCH 2013 When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled; then a signal at this input can neither increment the write offset register pointer, nor execute a write. The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOW- to-HIGH transition of the read clock (RCLK). The act of reading the control registers employs a dedicated read offset register pointer. (The read and write pointers operate independently). A read and a write should not be performed simultaneously to the offset registers. FIRST LOAD ( FL) FL is grounded to indicate operation in the Single Device or Width Expansion mode. In the Depth Expansion configuration, FL is grounded to indicate it is the first device loaded and is set to HIGH for all other devices in the Daisy Chain. (See Operating Configurations for further details.) WRITE EXPANSION INPUT (WXI) This is a dual purpose pin. WXI is grounded to indicate operation in the Single Device or Width Expansion mode. WXI is connected to Write Expansion Out (WXO) of the previous device in the Daisy Chain Depth Expansion mode. READ EXPANSION INPUT (RXI) This is a dual purpose pin. RXI is grounded to indicate operation in the Single Device or Width Expansion mode. RXI is connected to Read Expansion Out (RXO) of the previous device in the Daisy Chain Depth Expansion mode. OUTPUTS: FULL FLAG( FF) When the FIFO is full, FF will go LOW, inhibiting further write operations. When FF is HIGH, the FIFO is not full. If no reads are performed after a reset, FF will go LOW after D writes to the FIFO. D = 256 writes for the IDT72205LB, 512 for the IDT72215LB, 1,024 for the IDT72225LB, 2,048 for the IDT72235LB and 4,096 for the IDT72245LB. The FF is updated on the LOW-to-HIGH transition of the write clock (WCLK). EMPTY FLAG/ (EF) When the FIFO is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. The EF is updated on the LOW-to-HIGH transition of the read clock (RCLK). PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full Flag ( PAF) will go LOW when FIFO reaches the Almost-Full condition. If no reads are performed after Reset (RS), the PAF will go LOW after (256-m) writes for the IDT72205LB, (512-m) writes for the IDT72215LB, (1,024-m) writes for the IDT72225LB, (2,048–m) writes for the IDT72235LB and (4,096–m) writes for the IDT72245LB. The offset “m” is defined in the FULL offset register. If there is no Full offset specified, the PAF will be LOW when the device is 31 away from completely full for IDT72205LB, 63 away from completely full for IDT72215LB, and 127 away from completely full for IDT72225LB/72235LB/ 72245LB. The PAF is asserted LOW on the LOW-to-HIGH transition of the write clock (WCLK). PAF is reset to HIGH on the LOW-to-HIGH transition of the read clock (RCLK). Thus PAF is asynchronous. PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) The ProgrammableAlmost-Empty Flag(PAE) will go LOW when the read pointer is "n+1" locations less than the write pointer. The offset "n" is defined in the EMPTY offset register. If there is no Empty offset specified, the Programmable Almost-Empty Flag (PAE) will be LOW when the device is 31 away from completely empty for IDT72205LB, 63 away from completely empty for IDT72215LB, and 127 away from completely empty for IDT72225LB/72235LB/72245LB. The PAE is asserted LOW on the LOW-to-HIGH transition of the read clock (RCLK). PAE is reset to HIGH on the LOW-to-HIGH transition of the write clock (WCLK). Thus PAE is asynchronous. WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF) This is a dual-purpose output. In the Single Device and Width Expansion mode, when Write Expansion In (WXI) and Read Expansion In (RXI) are grounded, this output acts as an indication of a half-full memory. Number of Words in FIFO IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB FF PAF HF PAE EF 00 0 0 0 H H H L L 1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) HH H LH (n + 1) to 128 (n + 1) to 256 (n + 1) to 512 (n + 1) to 1,024 (n + 1) to 2,048 H H H H H 256 512 1,024 2,048 4,096 L L L H H TABLE 1 — STATUS FLAGS NOTES: 1. n = Empty Offset (Default Values : IDT72205LB n=31, IDT72215LB n = 63, IDT72225LB/72235LB/72245LB n = 127) 2. m = Full Offset (Default Values : IDT72205LB m=31, IDT72215LB m = 63, IDT72225LB/72235LB/72245LB m = 127)

when the previous device reads from the last location of memory. 0-Q17 are data outputs for 18-bit wide data.

1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.

Figure 4. Reset Timing(2)

Figure 21. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous

1. The first device must be designated by grounding the First Load (FL)
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to

the Write Expansion In (WXI) pin of the next device. See Figure 21.

1. The Read Expansion Out (RXO) pin of each device must be tied to the

Read Expansion In (RXI) pin of the next device. See Figure 21.

1. All Load (LD) pins are tied together.
2. The Half-Full Flag (HF) is not available in this Depth Expansion
3. EF, FF, PAE, and PAF are created with composite flags by ORing

and PAF flags are not precise.

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San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com www.idt.com DATASHEET DOCUMENT HISTORY 10/02/2006 pgs. 1 and 16. 10/22/2008 pg. 16. 03/21/2013 pgs. 1, 12, 16 11/27/2017 Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018. XXXXX Device Type X Power XX Speed X Package X BLANK Clock Cycle Time (tCLK) Speed in Nanoseconds Process / Temperature Range 2766 drw24 Commercial Only Commercial (0°C to +70°C) Industrial (-40°C to +85°C)I(1) J PF TF Plastic Leaded Chip Carrier (PLCC, J68-1) Thin Plastic Quad Flatpack (TQFP, PN64-1) Slim Thin Plastic Quad Flatpack (STQFP, PP64-1) Commercial & Industrial Commercial & Industrial LB Low Power X G(2) Green 72205 256 x 18 Synchronous FIFO 72215 512 x 18 Synchronous FIFO 72225 1,024 x 18 Synchronous FIFO 72235 2,048 x 18 Synchronous FIFO 72245 4,096 x 18 Synchronous FIFO X BLANK Tube or Tray Tape and Reel NOTES: 1. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device. All other speed grade s are available by special order. 2. Green parts are available. For specific speeds and packages contact your sales office . LEAD FINISH (SnPb) parts are in EOL proc ess. Product Discontinuation Notice - PDN# SP-17-02

ORDERING INFORMATION

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