L99PD08 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 41
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin definitions and functions
- 2.1 ST -SPI: SCK, SDI, SDO, CSN
- 2.2 CLK_IN0, CLK_IN1
- 2.3 LHOMEN
- 2.4 Output 0 to 7 (OUT0 … OUT7)
- 2.5 Status/current sense inputs (ST0/CS0 … ST7/CS7)
- 2.6 Multiplexed status/current sense output (MUX_ST/CS)
- 2.7 VDDIO, VCORE3
- 2.8 GND (2 pins)
- 2.9 Faultn
- 2.10 SYNC
- 3 Device mode
- 4 Absolute maximum ratings
- 4.1 ESD protection
- 4.2 Operating junction temperature
- 5 Electrical characteristi cs
- 6 SPI
- 6.1 SPI timing parameter definition
- 6.2 Functional description of the SPI
- 6.2.1 Serial clock (SCK)
- 6.2.2 Serial data input (SDI)
- 6.2.3 Serial data output (SDO)
- 6.2.4 Chip select not (CSN)
- 6.3 SPI communication flow
Features
I 8 channel VIPower driver and diagnostics device I Supports analog and digital VIPower status readback I 8 independent PWM channels I Selectable PWM base clock (2 external, one internal) I Programmable PWM turn on phase shift I Programmable diagnostic thresholds (analog VIPower) I Programmable over temperature latch off for enhanced HSD short circuit reliability I Limp home safety mode I ST-SPI interface protocol for data communication I External enable pin for low power mode I Detailed and filtered diagnostic for each channel I Direct multiplexed VIPower status / current sense feedback I Supply voltage 3.3 or 5.0 V (two pins)
Applications
I Exterior and interior automotive light system
Description
The device has integrated several functions which save job load of the microcontroller and save necessary connections to the microcontroller. It’s possible to connect analog and digital high side drivers (HSD) to the device and control them via SPI interface. A synchronous detailed diagnostics feature is integrated. The device has 8 outputs to the HSD with the possibility to be driven either by steady state ON/OFF mode or by PWM. Two clock inputs used as base frequency to generate the PWM signal internally are provided. The outputs are fully independent and can also be driven with phase shift to improve characteristics of power net during the inrush phase. The device has 8 current sense (CS)/status (ST) pins connected to the HSD to run diagnostics. The index of ST/CS pin corresponds to the input connected to the same HSD channel (ST0/CS0 with OUT0, ST1/CS1 with OUT1 …). LQFP32 Table 1. Summary device
1 Block diagram
Figure 1. Application example block diagram
2 Pin definitions and functions
Table 2. Pin definition and function
1 CLK_IN0 PWM clock input 0
2 CLK_IN1 PWM clock input 1
5 FAULTN Failure on HSD or communication error
6 SYNC Output of OUT0-OUT7 signal s, selected by control register
7 MUX_ST/CS Output from ST/CS multiplexer
9 SCK ST -SPI – serial clock input
10 SDI ST -SPI – serial data input
11 SDO ST -SPI – serial data output
12 CSN ST -SPI – chip select input
14 EN Enable pin
16 LHOMEN Active mode pull-up supply – limp home
17 ST7/CS7 Input from HSD status / current sense pin
18 OUT7 Output to High side driver – channel 7
19 ST6/CS6 Input from HSD status / current Sense pin
20 OUT6 Output to high side driver – channel 6
21 ST5/CS5 Input from HSD status / current sense pin
22 OUT5 Output to high side driver – channel 5
23 ST4/CS4 Input from HSD status / current sense pin
24 OUT4 Output to high side driver – channel 4
25 ST3/CS3 Input from HSD status / current sense pin
26 OUT3 Output to high side driver – channel 3
27 ST2/CS2 Input from HSD status / current sense pin
28 OUT2 Output to high side driver – channel 2
29 ST1/CS1 Input from HSD status / current sense pin
30 OUT1 Output to high side driver – channel 1
31 ST0/CS0 Input from HSD status / current sense pin
32 OUT0 Output to high side driver – channel 0
Figure 2. Pinning of device in LQFP-32 package
2.1 ST-SPI: SCK, SDI, SDO, CSN
shifted out at SDO at the negative edge of SCK. A CSN timeout is implemented.
2.2 CLK_IN0, CLK_IN1
registers DUTY_CHx (Addr: hex10 – hex17) and PHASE_CHx (Addr: hex18 – hex1F).
L99PD08 Pin definitions and functions Doc ID 15872 Rev 3 9/41 The output PWM period is a factor of 256 of the frequency applied on CLK_INx signal. If the external clock signal is not available or is below fPWM(min) , the device will fallback to an internal PWM frequency generator fPWM of approximately 122Hz periode.
2.3 LHOMEN
This pin allows connecting the output pull-down resistor for LIMP HOME mode. This pin is pulled to VDDIO in normal mode and is pulled low in case of failure (RESET and FAIL SAVE mode). If power supply VDDIO is not connected, LHOMEN becomes weak low (LIMP HOME mode).
2.4 Output 0 to 7 (OUT0 … OUT7)
True open drain outputs are used to drive the High Side Driver inputs. These lines must have a pull-up resistor connected either to a separate supply or LHOMEN signal if LIMP HOME is supported. These outputs are high impedance during RESET, Fail Safe modes and during SW Reset.
2.5 Status/current sense in puts (ST0/CS0 … ST7/CS7)
Those inputs are used to take the status or current sense information from DIGITAL or ANALOG HSD and provide information to the internal diagnosis. Every output has to correspond to the same HSD channel like the ST/CS input (OUT0 with ST0/CS0, OUT1 with ST1/CS1, …). Status of digital channels have to have an external pull-up resistor (4.7 kOhm) and a series protection resistor of 4.7 kOhm to STx/CSx, current sense signals of analog channels have to be connected to STx/CSx pins through a 100 Ohm reverse battery protection resistor. The HSD type which is connected to the device (digital or analog) must be selected through the register DEV_TYPE (Addr: hex02).
2.6 Multiplexed status/current sense output (MUX_ST/CS)
The MUX_ST/CS Pin reflects the status or current sense information corresponding to the channel selected in the control register bits MUX_EN, MUX_A, B, C (Addr: hex00; Bit 7-4). This pin delivers up to 3 mA at 2.7 V. It is recommended to use a 1.6k to 2.7kOhm external resistor to ground for the maximum dynamic range. The best choice for the external resistor depends on the Rdson class of the analog current sense HSD and of the loads. If the multiplexer is disabled the MUX_ST/CS pin is in tristate condition.
2.7 VDDIO, VCORE3
The digital voltage supply of the device is internally limited to 3.3 V. In order to support also the 5 V supply voltages a linear internal voltage regulator can be used.
loads should be attached on VCORE3. (shorted) to the local supply. communications are possible.
2.8 GND (2 pins)
2.9 Faultn
low, while during reset it is left open. This pin has to be connected to a pull up resistor.
2.10 SYNC
SYNC pin is actively pulled low. Figure 3. Example for SYNC pin functionality
L99PD08 Pin definitions and functions Doc ID 15872 Rev 3 11/41 2.11 EN With this pin pulled high, the device leaves low power mode. An internal pull down resistor guarantees the OFF condition when not connected.
3 Device mode
both cases LHOME-bit is automatically reset) or setting this bit to ‘0’ via SPI access. When SDI is stuck to GND the device enters automatically FAIL SAVE. SAVE. A read of ROM address Addr.: hex3F is detected as stuck to logical high level. In FAIL SAVE the SYNC pin is logical high. Table 3. Device modes
- Max. sink current can only be guaranteed for VCORE3 VCORE3 min. Therefore an external pull down is recommended.
Figure 4. Device state diagram
4 Absolute maximum ratings
cause an irreversible damage of the integrated circuit.
4.1 ESD protection
4.2 Operating junction temperature
Table 4. Absolute maximum ratings Table 5. ESD protection Table 6. Operating junction temperature
5 Electrical characteristics
Table 7. Supply Table 8. Undervoltage detection Table 9. EN pin
Table 10. Output switches/fault pin
- Output switches read back only
Table 11. Current sense/status inputs
Table 13. Current MUX_ST/CS ratio
Table 13. Current MUX_ST/CS ratio (continued)
Figure 7. MUX_ST/CS ratio
Table 14. Current sense diagnostic thresholds Table 15. LHOMEN and SYNC pin
6 SPI
Table 16. DC characteristics Table 17. Dynamic characteristics
6.1 SPI timing parameter definition
Figure 8. SPI timing diagram
6.2 Functional description of the SPI
communicate with a microcontroller. Table 17. Dynamic characteristics (continued) Table 18. CSN timeout/CLK_INx timings
Figure 9. SPI frame structure
6.2.1 Serial clock (SCK)
shifted out at the falling edge of Serial Clock (SCK). unwanted activation of output stages by a wrong communication frame.
6.2.2 Serial data input (SDI)
This input is used to transfer data serially into the device. It receives the data to be written. Values are latched on the rising edge of Serial Clock (SCK).
6.2.3 Serial data output (SDO)
falling edge of Serial Clock (SCK).
6.2.4 Chip select not (CSN)
(SCK). A CSN timeout is implemented.
6.3 SPI communication flow
6.3.1 General description
containing the current of the addressed register (i. e. ‘In-frame-response’).
6.3.2 Command byte
Information>) and a 6 bit address. Table 19. Command byte
6.3.3 Operating code definition
e.g. write to control registers or read status information. all status registers at a time and reads back the <Configuration> byte. information such as the product family, product name, silicon version and register width.
6.3.4 Global status byte
Table 20. Operating code definition Table 21. Global status byte Table 22. Global status byte: description <Global Status Register> (initially set to '1'). does not match with the specified frame width.
Figure 10. SDO status therefore not cleared in case of a clear command. this case, the data in the Status Register is always the more actual data. Table 22. Global status byte: description (continued)
6.4 SPI – control and status register
Table 23. RAM memory map
Table 23. RAM memory map (continued) Table 24. ROM memory map (access with OC0 and OC1 set to ‘1’) Table 25. Control register, hex00 (RW-Type) Timeout occurs the device enters FAIL SAFE mode (LimpHome).
Table 26. ON_OFF register, hex01 (RW-Type)
1 Ox channel is switched on
Table 27. DEV_TYPE register, hex02 (RW-Type)
1 Analog device is connected to device output
Table 28. PWM_EN register, hex03 (RW-Type)
1 If OUTx in ON_OFF register is 1, OUTx is switched in PWM mode
Table 29. CLK_SEL register, hex04 (RW-Type)
limitation) or detecting ambiguous failure with OT_FAULT. activates the corresponding channel after clear according to setting.
1 The external clock source signal CLK_IN1 is selected for internal generation of
Table 30. ASDT register, hex05 (RW-Type)
1 Automatic shutdown of thermal cycling is switched on (default)
Table 31. DET_DIAG register, hex06 (RW-Type) CHx 0 Automatic detailed diagnosis is disabled.
time the diagnostics doesn’t report any failures. 0x00 with a ‘1’ (former state ‘0’ => OFF). connected to the device (see VIP specification). Table 32. BLK_TIME1 register, hex07 (RW-Type) Table 33. BLK_TIME2 register, hex08 (RW-Type) 0 0 The blank time is not active after activation of the related channel. set to 200ms (minimum) (default). Table 34. TD_SENSE register, hex09 (RW-Type) Table 35. CFR register, hex0A (RW-Type)
diagnostics and MUX_CS/ST signal current. Table 36. OLOVL_TH_1 register, hex0B (RW-Type) Open-load threshold values for ST/CS channels (ST4/CS4 … ST7/CS7). Overload threshold values for ST/CS channels (ST4/CS4 … ST7/CS7). Table 37. OLOVL_TH_2 register, hex0C (RW-Type) Open-load threshold values for ST/CS channels (ST0/CS0 … ST3/CS3). Overload threshold values for ST/CS channels (ST0/CS0 … ST3/CS3).
the write command. Be aware, that an unwanted PWM can be generated during this phase. power net characteristic during PWM mode. write command. Be aware, that an unwanted PWM can be generated during this phase. Table 38. DUTY_CH 0 – DUTY_CH 7 Registers, hex10 – hex17 (RW-Type) Table 39. PHASE_CH 0 - PHASE_CH7 Registers, hex18 – hex1F (RW-Type) Table 40. CHANNEL_FB Registers, hex2E (R-Type)
reflected in this register (channel is turned off if ASDT is selected). be removed and cleared in on-state.
2 If a digital device and no detailed diagnosis is selected, also ambiguous failures are
Table 41. AUX_STATUS Registers, hex2F (RC-Type) (f = 122 Hz). The warn bit does not set the global error flag. CLK_INx Warn 0 input clock frequency f CLK_INx > 7 kHz. generated PWM clock signal is used. CS_time50% this bit is set when 50% of the CS-timeout time is reached. Table 42. OT_FAULT Registers, hex30 (RC-Type) Table 43. OL_FAULT Registers, hex31 (RC-Type)
Table 44. STK_FAULT Registers, hex32 (RC-Type) Table 45. OVL_FAULT Registers, hex33 (RC-Type)
7 Package and packing information
7.1 ECOPACK ® packages
ECOPACK® is an ST trademark.
7.2 LQFP32 mechanical data
Figure 11. LQFP32 outline Table 46. LQFP32 mechanical data
7.3 LQFP32 packing information
page 1 for packaging quantities). Figure 12. LQFP32 tape and reel shipment (suffix “TR”) Table 46. LQFP32 mechanical data (continued)
Figure 13. LQFP32 tray shipment (no suffix)
8 Revision history
Table 47. Document revision history 16-Jun-2009 1 Initial release. Table 16: DC characteristics. 09-Apr-2010 3 Changed status device from target specification to datasheet.