L99MC6 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Introduction
- 1.1 Application diagram
- 1.2 Block diagram and pin description
- 2 Description
- 2.1 Dual power supply: V S and VCC
- 2.1.1 Channels
- 2.2 Standby mode
- 2.3 Inductive loads
- 2.4 Diagnostic functions
- 2.4.1 Direct input IN/PWM
- 2.4.2 Temperature warning and thermal shutdown
- 2.4.3 Open-load detection in off-state
- 2.4.4 Overload detection
- 2.5 Bridge mode
- 2.6 LED mode
- 2.7 Bulb mode (programmable soft start function to drive loads with higher
- 3 Absolute maximum ratings
- 4 ESD protection
- 5 Thermal data
- 5.1 Temperature warning and thermal shutdown
- 6 Electrical characteristi cs
- 6.1 Supply
- 6.2 Undervoltage detection
- 6.3 Channels
- 7 SPI electrical character istics
- 7.1 DC characteristics
Datasheet sections
- 13 Package and packing information
- 13.1 ECOPACK ®
- 13.2 PowerSSO-16 package information
- 13.3 Packing information
Features
■ 3 independently self configuring high-/low-side channels ■ 3 low-side channels ■ RON =0 . 7 Ω (typ) at Tj = 25 °C ■ Current limit of each output at min. 0.6 A ■ PWM direct mode ■ Bulb mode with recovery mode ■ LED mode with slew rate control ■ Bridge mode with crosscurrent protection ■ SPI interface for data communication ■ Temperature warning ■ All outputs overtemperature protected ■ All outputs short-circuit protected ■ Configurable open-load detection in off mode ■ VCC supply voltage 3.0 V to 5.25 V ■ Very low current consumption in standby mode 5 µA (typ) ■ Internal clamp diodes ■ HS switches operate down to 3 V crank voltage
Applications
■ Relay driver ■ LED driver ■ Motor driver ■ Mirror adjustment
Description
The L99MC6 IC is a highly flexible monolithic medium current output driver that incorporates 3 dedicated low-side outputs (channels 4 to 6) and 3 independently self configuring outputs (channels 1 to 3) that can be used as either low- side or high-side drivers in any combination. The L99MC6 can control inductive loads, incandescent bulbs or LEDs. The L99MC6 can be used in a half bridge configuration with crosscurrent protection. The channel 2 can be controlled directly via the IN/PWM pin for PWM applications. The IN/PWM signal can be applied to any other output. The integrated 16-bit standard serial peripheral interface (SPI) controls all outputs and provides diagnostic information: normal operation, open- load in off-state, overcurrent, temperature warning, overtemperature. PowerSSO-16 Table 1. Device summary
Table 47. Auto and mutual thermal resistance - 2 cm
1 Introduction
1.1 Application diagram
Figure 1. Application diagram
1.2 Block diagram and pin description
Figure 2. Block diagram
Table 2. Pin functions Direct input for channel 2. Other channels can be driven in PWM mode via SPI.
3 SRC1 Source of configurable channel 1
4 DRN1 Drain of self configurable channel 1, in HS mode also V S supply
5 DRN2 Drain of self configurable channel 2
15 SRC2 Source of self configurable channel 2
12 DRN3 Drain of self configurable channel 3
13 SRC3 Source of self configurable channel 3
2 DRN4 Drain of channel 4
16 DRN5 Drain of channel 5
14 DRN6 Drain of channel 6
(MSB, bit 7) is transferred first. remains in tristate, if the chip is not selected by the input CSN (CSN = high).
10 SCK
Figure 3. Configuration diag ram (top view) not in scale
2 Description
2.1 Dual power supply: V S and VCC
impedance) and the status registers are cleared (see Figure 4). Figure 4. Power-on reset
2.1.1 Channels
VCC is used to drive all channels. internally connected to the device GND. Caution: For any high-side configuration, channel 1 must be used as a high-side switch. charge pump current from the drain.
2.2 Standby mode
status registers are cleared and the control registers are reset to their default values. needed to switch the L99MC6 in normal mode.
2.3 Inductive loads
maximum provides for fast turn-off of inductive loads (Figure 5). The maximum clamping energy is specified in Chapter 10. Figure 5. Output voltage clamping
2.4 Diagnostic functions
are internally filtered and the condition has to be valid for at least 32 µs (open-load: typ. incandescent lamps, cold resistance of motors and heaters, Figure 7).
2.4.1 Direct input IN/PWM
The IN/PWM input allows channel 2 to be enabled without the use of SPI. The IN/PWM pin is OR-ed with the SPI command bit. This pin can be left open if the channel 2 is controlled only via the SPI. This input has an internal pull-down. The IN/PWM signal can also be applied to any other switches by the activation of the PWM mode. This input is suited for non-inductive loads that are pulse width modulated. This allows PWM control without further use of the SPI.
2.4.2 Temperature warning and thermal shutdown
If the junction temperature rises above Tj TW a temperature warning flag is set and is detectable via the SPI. If the junction temperature increases above the second threshold T jS D, the thermal shutdown bit is set and power DMOS transistors of all output stages are switched-off to protect the device. Temperature warning flag and thermal shutdown bits are latched. In order to reactivate the output stages, the junction temperature must decrease below T jS D- TjS DH Y S and the thermal shutdown bit has to be cleared by the microcontroller.
2.4.3 Open-load detection in off-state
The open-load detection monitors the load at each output stage in off mode. A current source of 150 µA (I OLD1-6, IOLS 1-3) is connected between drain and source or GND. An open-load failure is detected if the drain or source voltage reaches an internal VOLD/S (2.0 V) for at least 3 ms (tdOL typ.). The corresponding open-load bit is set in the status register. In LED mode the open-load detection is disabled and the current source is switched-off, which avoids a turn-on of the LEDs in off-state.
2.4.4 Overload detection
In case of an overcurrent condition, a flag is set in the corresponding status register. If the overcurrent signal is valid for at least t ISC = 32 µs, the overcurrent flag is set and the corresponding driver is switched-off to reduce the power dissipation and to protect the integrated circuit. If the overcurrent recovery bit of the output is zero the microcontroller has to clear the status bit to reactivate the corresponding driver.
2.5 Bridge mode
The L99MC6 can be configured as bridge driver. Up to three half bridges can be used. In Bridge mode the device is crosscurrent protected by an internal delay time. If one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge is automatically delayed by the crosscurrent protection time. After the crosscurrent protection time is expired the slew rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver starts to conduct. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs without external free-wheeling diodes.
the high-side drivers is turned on, may cause a destruction of the device. PWM mode on other channels is not possible. Figure 6. Example of bridge configuration
2.6 LED mode
current source (150 µA typ.) when the channel is switched-off. cycle (see Section 9.3.1: Channel configuration decoding).
2.7 Bulb mode (programmable soft start function to drive loads
reaches operating condition (Figure 6). Figure 7. Example of programmable soft start function for inductive loads and incandescent
3 Absolute maximum ratings
conditions above those indicated in the operating sections of this specification is not implied. cause an irreversible damage of the integrated circuit. Table 3. Absolute maximum ratings
- The device requires a minimum load impedance of 40 Ω to sustain a load dump pulse of 40 V according to
4 ESD protection
Table 4. ESD protection
- HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A
- HBM with all unzapped pins grounded
5 Thermal data
5.1 Temperature warnin g and thermal shutdown
For additional information, please refer to Chapter 12: Package and PCB thermal data. Table 5. Temperature warning and thermal shutdown
5.2.1 T jTW ON
5.2.2 T jTW OFF
5.2.3 T jTW HYS Temperature warning hysteresis - 5 K
5.2.4 T jSD ON
5.2.5 T jSD OFF
5.2.6 T jSD HYS Thermal shutdown hysteresis - 5 K
6 Electrical characteristics
VS =6V t o1 6V , VCC = 3.0 V to 5.3 V, Tj = -40 °C to 150 °C, unless otherwise specified.
6.1 Supply
6.2 Undervoltage detection
Table 6. Supply
6.1.1 V S
6.1.2 I S VS DC supply current
6.1.3 I VS VS quiescent supply current
6.1.4 V CC
6.1.6 VCC quiescent supply
Table 7. Undervoltage detection
6.3 Channels
Table 8. Channels
6.3.3 I SC1-6 Overcurrent protection
6.3.9 I QLD
6.3.10 I QLS
6.3.11 V OLD1-6
6.3.12 I OLD1-6
6.3.13 V OLS1-3
6.3.14 I OLS1-3
6.3.19 V DRN_CL1-6
6.3.20 V SRC_CL1-3
Table 8. Channels (continued)
7 SPI electrical characteristics
VS =6V t o1 6V , VCC = 3.0 V to 5.3 V, Tj = -40 °C to 150 °C, unless otherwise specified.
7.1 DC characteristics
7.2 AC characteristics
Table 9. DC characteristics Table 10. AC characteristics
7.3 Dynamic characteristics
Table 11. Dynamic characteristic
7.4 SPI timing parameter definition
Figure 8. Serial input timing Figure 9. Serial input timing
Figure 10. Output turn on/off delays and slew rates
8 Functional description of the SPI
8.1 Signal description
8.1.1 Serial clock (SCK)
shifted out at the falling edge of serial clock (see Figure 11). mode: CPOL = 0 and CPHA = 0 (see Figure 11).
8.1.2 Serial data input (SDI)
This input is used to transfer data serially into the device. It receives the data to be written. Values are latched on the rising edge of serial clock (SCK).
8.1.3 Serial data output (SDO)
falling edge of serial clock (SCK).
8.1.4 Chip select not (CSN)
start and stop on a low-level of serial clock (SCK). Figure 11. Clock polarity and clock phase
Figure 12. SPI frame structure
8.2 SPI communication flow
8.2.1 General description
(16 bit for the L99MC6) and the availability of additional features. is ‘In-frame-response’, see Figure 12).
8.2.2 Command byte
Device Information>) and a 6-bit address. Table 12. Command byte - general description Table 13. Data byte - general description Table 14. Command byte
that is write to control registers or read status information. address 3FH clears all status registers at a time. RAM address, the second byte is equal to 00H). information such as the product family, product name, silicon version and register width.
8.2.3 Global status register
Table 15. Operating code definition Table 16. Global status register Table 17. Global status register description
0 Unused Active high Always returns ‘0’
1 Overcurrent detected Active high Set by any overcurrent event
2 Open-load detected Active high Set by any open-load event
3 Temperature warning Active high -
4 Thermal shutdown / chip
5 Chip reset Active low
device (that is <Global Status Register>, [0:6]). Figure 13. Indication of the global error flag on DO when CSN is low and SCK is stable
- The last transferred SPI command is still valid in the input sh ift register. If SCK is stable (high or low) during a CSN low
pulse, at the rising edge of CSN the last transferred SPI command is still valid in the input shift register and is repeated. Therefore, it is recommended to send a complete SPI frame to monitor the status of the L99MC6. an unwanted activation of output stages by a wrong communication frame.
6 Communication error Active high
7 Global Error flag Active high Logic OR combination of all failures in the
Table 17. Global status register description (continued)
larger than the frame width, the data at DO is filled with ‘0’ bits. subsequent correct length transaction is necessary to correct this bit.
8.3 Write operation
The Write operation starts with a command byte followed by 1 data byte. Failures are indicated by activating the corresponding bit of the <Global Status> register. Note: The register definition for RAM address 00H is device specific. A register value of all 0 causes a device reset (interpreted as ‘Data-in short to GND’).
8.4 Read operation
the same frame (‘in-frame response’). The returned data byte represents the content of the register to be read. Failures are indicated by activating the corresponding bit of the <Global Status> register. Table 18. Command byte for Write mode Table 19. Command byte for Read mode
8.5 Read and Clear Status operation
The ‘Read and Clear Status’ operation starts with a command byte followed by 1 data byte. RAM address, the second byte is equal to 00H). The returned data byte represents the content of the register to be read. Failures are indicated by activating the corresponding bit of the <Global Status> register.
8.6 Read Device Information
All unused ROM addresses is read as ‘0’. entered (all internal registers are cleared). Table 20. Command byte for Read and Clear Status operation Table 21. Command byte for Read Device Information
9 SPI control and status register
9.1 RAM memory map
9.2 ROM memory map (access with OC0 and OC1 set to ‘1’)
9.3 Control and status registers
Table 22. RAM memory map Table 23. ROM memory map Table 24. Control register 0
Table 25. Control register 1 Table 26. Control register 2 Table 27. Status register 0 Table 28. Status register 1
9.3.1 Channel conf iguration decoding
9.3.2 Register description
Table 29. Channel configuration decoding
000 O f f (1) No - High Off
111 O f f (1) No - Low On
001 O n N o N o H i g h -
010 O n N o N oL o w -
011 O n N oY e s L o w -
101 I N / P W M
110 I N / P W M (2) Ye s N o L ow O n
- The state of the channel 2 is according to the IN/PWM signal
- The output state is according to the IN/PWM signal, note that bridge mode and PWM mode may not be activated at the
same time for channels 2 and 5. Table 30. Register description (1) EN Global device enable bit. If this bit is reset, the device goes in standby mode. Channel output configuration (see Figure 29). independently from the PWM configuration of other channels. deactivation after an undetected communication error. sure, that the corresponding OC bit remains cleared after a maximum heat up time of the load.
- Every output stage is protected against overtemperature and overcurrent. While still configured as ON, the output stage
registers have to be cleared by a specific SPI command.
9.4 Examples
9.4.1 Example 1:Switch on channel 1
Table 33 describe more in detail the data byte structure.
- DISCP = 0: Charge pump stays activated
- CH4[2:0] = 000b: Channel 4 is off, open-load detection in off-state disabled
- BRIDGE_1&4 = 0: Bridge mode disabled
- CH4[2:0] = 001b: Channel 1 is on, high slew rate, PWM not activated, overcurrent recovery deactivated.
Table 31. Command byte - example 1 Table 32. Data byte - example 1 Table 33. Data byte description - example 1
9.4.2 Example 2: Bridge mode configuration
Table 36 describe more in detail the data byte structure.
- ENCP = 1: Charge pump stays activated
- CH5[2:0] = 010b: Channel 5 is on, PWM disabled, overcurrent recovery mode disabled, low slew rate
- BRIDGE_2&5 = 1: Bridge mode for channel 2 and channel 5 activated
- CH2[2:0] = 000b: Channel 2 is off, open-load detection in off-state disabled From Table 37 and Table 38 follow that the value 0Ah is written at RAM address 02h (control register 2). Table 39 describe more in detail the data byte structure.
Table 34. Command byte 1 - example 2 Table 35. Data byte 1 - example 2 Table 36. Data byte description 1 - example 2 Table 37. Command byte 2 - example 2 Table 38. Data byte 2 - example 2
- DISCP = 0: Charge pump stays activated
- CH4[2:0] = 000b: Channel 4 is off, open-load detection in off-state disabled
- BRIDGE_1&4 = 1: Bridge mode for channel 1 and channel 4 activated
- CH4[2:0] = 010b: Channel 1 is on, PWM disabled, overcurrent recovery mode disabled, low slew rate
Figure 14. Bridge mode drawing Table 39. Data byte description 2 - example 2
9.4.3 Example 3: Open-load detection in off-state in bridge configuration
Table 42 describe more in detail the data byte structure.
- ENCP = 1: Charge pump stays activated
- CH5[2:0] = 111b: Channel 5 is off, open-load detection in off-state enabled
- BRIDGE_2&5 = 1: Bridge mode for channel 2 and channel 5 activated
- CH2[2:0] = 000b: Channel 2 is off, open-load detection in off-state disabled From Table 43 and Table 44 follow that the value 0Ah is written at RAM address 02h (control register 2). Table 45 describe more in detail the data byte structure.
Table 40. Command byte 1 - example 3 Table 41. Data byte 1 - example 3 Table 42. Data byte description 1 - example 3 Table 43. Command byte 2 - example 3 Table 44. Data byte 2 - example 3
- DISCP = 0: Charge pump stays activated
- CH4[2:0] = 000b: Channel 4 is off, open-load detection in off-state disabled
- BRIDGE_1&4 = 1: Bridge mode for channel 1 and channel 4 activated
- CH1[2:0] = 010b: Channel 1 is on, PWM disabled, overcurrent recovery mode disabled, low slew rate
Figure 15. Open-load in bridge mode drawing
- Case 1: The motor is connected, drain of channel 5 is pulled up by channel 1 (on) through the motor, then no open-load detected on channel 5
- Case 2: The motor is not connected and the drain voltage of channel 5 is below the open-load threshold, then open-load detected on channel 5
Table 45. Data byte description 2 - example 3
10 Maximum demagnetization energy
Figure 16. Configurable switch HSD - maximum turn-off current versus inductance
Figure 17. Configurable switch LSD - maximum turn-off current versus inductance
Figure 18. Fixed LSD switch - maximum turn-off current versus inductance
Figure 19. L99MC6 as driver for incandescent bulb, LEDs and high-side or low-side
Figure 20. L99MC6 as motor driver (f or example, for mirror adjustment)
Figure 21. L99MC6 as driver for unipolar stepper motor driver, relay and LEDs
12.1 PowerSSO-16 thermal data
Figure 22. PowerSSO-16 PC board (1)
- Layout condition of thermal resistance meas urements (PCB: double layer, thermal vias,
footprint dimension 2.5 mm x 4.2 mm ). Table 46. Auto and mutual thermal resistance - footprint Table 47. Auto and mutual thermal resistance - 2 cm 2 of Cu heatsink
Equation 1 represents ΔTj-amb calculation of a full loaded device for the HSD1 junction. Table 48. Auto and mutual thermal resistance - 8 cm 2 of Cu heatsink
13.1 ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
13.2 PowerSSO-16 package information
Figure 23. PowerSSO-16 package dimensions
Table 49. PowerSSO-16 mechanical data (1)
- Drawings dimensions include single and matrix versions.
- Dimensions D does not include mold flash protrusions or gate burrs.
Mold flash protrusions or gate burrs shall not exceed 0.15 mm in total (both side).
13.3 Packing information
Figure 24. PowerSSO-16 tube shipment (no suffix) Figure 25. PowerSSO-16 tape and reel shipment (suffix “TR”)
Table 50. Acronyms
Revision history
Table 51. Document revision history 18-Nov-2009 1 Initial release.