L99H01QF STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Block diagram and pin description
- 1.1 Pinout PowerSSO-36
- 1.2 Pinout LQFP32
- 2 Electrical specifications
- 2.1 Absolute maximum ratings
- 2.2 ESD protection
- 2.3 Thermal data
- 2.4 Electrical characteristics
- 2.5 SPI - electrical characteristics
- 3 Device description
- 3.1 Dual power supply: V S and VCC
- 3.2 Standby mode (EN)
- 3.3 H-bridge control (DIR, PWM, bit FW)
- 3.4 Resistive low
- 3.5 Diagnostic functions
- 3.6 Overvoltage and undervoltage detection
- 3.7 Charge pump
- 3.8 Temperature warning and thermal shutdown
- 3.9 Short-circuit detection / drain source monitoring
- 3.10 Programmable cross current protection
- 3.11 Current sense amplifier (CSA)
- 3.12 Thermal sensor interface / H-bridge switch-off input
- 3.12.1 EXT_TS-bit = low (active off)
- 3.12.2 EXT_TS-bit = high (thermal sensor interface)
- 3.13 Watchdog
- 4 Functional description of the SPI
- 4.1 Signal description
- 4.1.1 Serial clock (CLK)
- 4.1.2 Serial data input (DI)
Features
- Operating supply voltage 6 V to 28 V
- Central 2 stage charge pump
- 100% duty cycle
- Full RDSon down to 6 V (normal level MOSFETs)
- Control of reverse battery protection MOSFET
- Charge pump current limited
- PWM operation up to 30 kHz
- SPI interface
- Current sense amplifier / free configurable
- Zero adjust for end of line trimming
- Power management: programmable free wheeling
- Sensing circuitry of external MOSFETs with embedded thermal sensors
Applications
- Wiper
- Power door
- Seat belt tensioner
- Seat positioning
- Valve tronic
- Park break
- 2H motors
Description
The L99H01 is designed to control 4 external N-channel MOS transistors in bridge configuration for DC-motor driving in automotive applications. A free configurable current sense amplifier is integrated. The integrated standard serial peripheral interface (SPI) controls all outputs and provides diagnostic information. An interface pin for the thermal sensors of the external MOSFETs is implemented. PowerSSO-36 LQFP32 7x7mm Table 1. Device summary
6.6 LQFP32
Table 17. Thermal sense interface (4.5 V < V Table 37. Cross current protection time (t
1 Block diagram and pin description
Figure 1. Block diagram
1.1 Pinout PowerSSO-36
Table 2. Pin definitions and functions 1 GND Ground. Reference potential, connected to slug. 2 GNDD Digital ground. Reference potential. close as possible to GND is recommended. close as possible to GND is recommended. 5 EN Enable input. The enable input has a pull-down resistor. 7 PWM PWM input for H-bridge control. This input has a pull-down current.
by the input CSN (CSN = high). 13 CSO Current sense amplifier output: V CC compatible. 15 CSI1+ Current sense amplifier input: positive input 1, multiplexible. 16 CSI1- Current sense amplifier input: negative input 1, multiplexible. 17 CSI2+ Current sense amplifier input: positive input 2, multiplexible. 18 CSI2- Current sense amplifier input: negative input 2, multiplexible. 21 TS/ ACT_OFF Thermal sensor interface or input to switch all driver active off. 23 GL2 Gate driver for PowerMOS low-side switch in halfbridge 2. 24 SL2 Source of low-side switch in halfbridge 2. 25 GH2 Gate driver for PowerMOS high-side switch in halfbridge 2. 26 SH2 Source/drain of halfbridge 2. 27 SL1 Source of low-side switch in halfbridge 1. 28 GL1 Gate driver for PowerMOS low-side switch in halfbridge 1. 29 SH1 Source/drain of halfbridge 1. 30 GH1 Gate driver for PowerMOS high-side switch in halfbridge 1. 32 CP2+ Charge pump pin for capacitor 2, positive side. 33 CP2- Charge pump pin for capacitor 2, negative side. 34 CP1+ Charge pump pin for capacitor 1, positive side. 35 CP1- Charge pump pin for capacitor 1, negative side. Power supply voltage (external reverse protection required). Table 2. Pin definitions and functions (continued)
Figure 2. Pinning of device in PowerSSO-36 package
- The slug is connected to pin 1.
1.2 Pinout LQFP32
Table 3. Pin definitions and functions 1 CP2- Charge pump pin for capacitor 2, negative side. 2 CP1+ Charge pump pin for capacitor 1, positive side. 3 CP1- Charge pump pin for capacitor 1, negative side. Power supply voltage (external reverse protection required). 5 GND Ground. Reference potential, connected to slug. 6 GNDD Digital ground. Reference potential. close as possible to GND is recommended. close as possible to GND is recommended. 9 EN Enable input. The enable input has a pull-down resistor.
11 PWM PWM input for H-bridge control. This input has a pull-down current.
12 CSN
13 CLK
by the input CSN (CSN = high).
16 CSO Current sense amplifier output: V
17 CSI1+ Current sense amplifier input: positive input 1, multiplexible. 18 CSI1- Current sense amplifier input: negative input 1, multiplexible. 19 CSI2+ Current sense amplifier input: positive input 2, multiplexible. 20 CSI2- Current sense amplifier input: negative input 2, multiplexible. 22 TS/ ACT_OFF Thermal sensor interface or external off for all gate drivers. 23 GL2 Gate driver for PowerMOS low-side switch in halfbridge 2. 24 SL2 Source of low-side switch in halfbridge 2. 25 GH2 Gate driver for PowerMOS high-side switch in halfbridge 2. 26 SH2 Source/drain of halfbridge 2. 27 SL1 Source of low-side switch in halfbridge 1. 28 GL1 Gate driver for PowerMOS low-side switch in halfbridge 1. 29 SH1 Source/drain of halfbridge 1. 30 GH1 Gate driver for PowerMOS high-side switch in halfbridge 1. 32 CP2+ Charge pump pin for capacitor 2, positive side. Table 3. Pin definitions and functions (continued)
Figure 3. Pinning of device in LQFP-32 package
2 Electrical specifications
2.1 Absolute maximum ratings
conditions above those indicated in the operating sections of this specification is not implied.
2.2 ESD protection
Table 4. Absolute maximum ratings
4.1.2 Single pulse t max < 400 ms 40 V
4.3 DI, DO, CLK, CSN,
4.5 CSI1+, CSI1-,
4.6 GL2, GH2, GL1,
4.7 SL2, SH2, SL1, SH1 HV signal pins -6 to 40 V
Table 5. ESD protection
5.1 All pins ± 2 (1)
- - HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.
- HBM with all unzapped pins grounded.
5.2 V S versus GND ± 4 (1) kV
2.3 Thermal data
2.4 Electrical characteristics
VS = 6 V to 28 V, VCC = 3 V to 5.3 V, Tj = -40°C to 150°C, unless otherwise specified. Table 6. Operating junction temperature
6.1 T j Operating junction temperature -40 to 150 °C
Table 7. Temperature warning and thermal shutdown
7.1 T jTW ON
7.2 T jSD ON
7.3 T jSD OFF
Table 8. Packages thermal resistance
8.1 R thj-amb
Table 9. Supply
9.1 V S
9.2 V VS_OV1
9.3 VVS_OV1H
9.4 VVS_OV2
9.5 VVS_OV2H
9.6 V VS_UV
9.7 V VS_UVH
9.9 I SL
9.10 I CC VCC DC supply current VS =1 3V ; VCC =5V ;
9.11 I CC
9.12 I CCd VCCd supply current
Table 10. Undervoltage detection
10.3 V POR hyst
Table 11. Watchdog
11.1 T WDTO Watchdog time out — 50 60 100 ms
Table 9. Supply (continued)
Table 12. Inputs: CSN, CLK, PWM, DIR, EN and DI
12.5 I CLK in
12.8 I PWM in
12.9 R EN in
12.10 C in(1) Input capacitance at input
- Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 13. Charge pump output
13.2 I CP
13.3 V CP_LOW
13.5 T CP
Table 14. Gate drivers for external PowerMOS
14.1 I GHx(on)
14.2.2 VSHx = 0 V; IGHx = 50 mA;
14.3 V GHxH Gate on voltage Outputs floating V SHx +8V V SHx +1 0V V SHx +1 2V V
14.4 R GSHx
14.5 I GLx(on)
14.6.2 VSLx = 0 V; IGHx = 50 mA;
14.7 V GLxH Gate on voltage V SLx +8V V SLx +1 0V V SLx + 12 V V
14.8 R GSLx
- Indirect measurement, parameter measured dynamically us ing 100 nF load capacitor and evaluating the slew rate.
Table 15. Cross current protection time(1)
- Test conditions: V CC = 5 V, VS = 13.5 V
Table 16. Drain source monitoring Table 17. Thermal sense interface (4.5 V < VCC <5 . 3V )
17.1 I TS_bias Output bias current 200 250 300 µA
17.2 V th_TS TS threshold voltage
Table 18. Current sense amplifier(1)
18.1 V ICM
18.2 V IOFF50 Input offset voltage Gain = 50 -11 -4 3 mV
18.3 V IOFF20 Input offset voltage Gain = 20 -23 -8 7 mV
18.4 V IOFF10 Input offset voltage Gain = 10 -30 -10 10 mV
18.5 V IOFF-T50/ΔT Input offset voltage drift vs.
18.6 V IOFF-T20/ΔT Input offset voltage drift vs. 18.7 V IOFF-T10/ΔT Input offset voltage drift vs.
18.8 V IOFF-O_50
18.9 V IOFF-O_20
18.10 V IOFF-O_10
18.11 P SRR_50 Power supply rejection ratio Gain = 50 39 dB
18.12 P SRR_20 Power supply rejection ratio Gain = 20 31 dB
18.13 P SRR_10 Power supply rejection ratio Gain = 10 25 dB
18.14 CMRR Input common mode rejection T j = 25°C, DC 60 dB
18.16 Gain 20 Gain 19 20 21
18.18.2 I OUT = 200 µA VCC -
18.19.2 I OUT = -200 µA 15 50 mV
18.20 SRcso_10 CSO slew rate Gain = 10; RL = 1 kΩ,;
18.21 SRcso_20 CSO slew rate Gain = 20; RL = 1 kΩ,;
18.22 SRcso_50 CSO slew rate Gain = 50; RL = 1 kΩ,;
18.23 I CSI_10 CSI input current Gain = 10 -114 -102 -90 µA
18.24 I CSI_20 CSI input current Gain = 20 -80 -72 -64 µA
18.25 I CSI_50 CSI input current Gain = 50 -39 -33 -27 µA
- Test conditions: V S = 13 V, VCC = 5 V
- Not tested, guaranteed by design.
Table 18. Current sense amplifier(1) (continued)
2.5 SPI - electrical characteristics
Table 19. DI timing(1)
- DI timing parameters tested in production by a passed / failed test:
Tj = -40°C / +25°C: SPI communication @ 2 MHz. Tj = +125°C: SPI communication @ 1.25 MHz. Table 20. DO
20.1 V DOL
20.2 V DOH
20.3 I DOLK
20.4 C DO
- Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 21. DO timing Table 22. EN, CSN timing
Figure 10. SPI - timing of status bit 0 (fault condition)
3 Device description
3.1 Dual power supply: V S and VCC
The power supply voltage VS supplies the charge-pump. An internal charge-pump is used to drive the high-side switches and the low-side switches. The logic supply voltage VCC (3.3 V / 5 V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information is not lost, even if the supply voltage V S is switched-off. In case of power-on (VCC increases from undervoltage to VPOR OFF = 2.5 V, typical) the circuit is initialized by an internally generated power-on reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON =2 . 2V , typical), the outputs are switched-off and the status registers are cleared.
3.2 Standby mode (EN)
The L99H01 is activated with enable input high signal. For enable input floating (not connected) or V EN = 0 V the device is in standby mode. All latched data are cleared and the inputs and outputs are switched-off. In the standby mode the current at VS is less than 5 µA (1 µA) for CSN = high (DO in tristate). If VCC > VPOR OFF and EN = high the device enters the active mode. In the active mode the charge-pump and the diagnostic functions are active.
3.3 H-bridge control (DIR, PWM, bit FW)
The DIR and PWM inputs control the drivers of the external H-bridge transistors. The motor direction can be chosen with the DIR input, the duty cycle and frequency with the PWM input. With the SPI registers FW and FW-PAS 4 different free wheeling modes (2 active and 2 passive) can be selected using the high-side transistors or the low-side transistors. Unconnected inputs are defined by internal pull-down current.
Table 23. Truth table
- Only the halfbridge (low-side and high-side) where one MOSFET is in short-circuit condition is switched-off. Both MOSFET’S of the other halfbridge remain active and
Symbols:
- x: Don't care
- 1: Logic high or active
- 0: Logic low or not active
- H: Output in source condition
- L: Output in sink condition
- RL: Resistive low (see Section 3.4)
- T: Tristate
- FW: Free wheeling
- FW_PAS: Free wheeling passive
- CP_LOW: Charge pump low
- OV: Overvoltage
- UV: Undervoltage
- SC: Short-circuit
- TSD: Thermal shutdown
- GL_ER: Global error flag
3.4 Resistive low
The resistive output mode protects the L99H01 and the H-bridge in the standby mode and in some failure modes (internal and external thermal shutdown (TSD), charge pump low (CP_LOW), stucked reset (STK_RESET_Q) and power-on reset (PORES). When a gate driver changes into the resistive output mode due to a failure a sequence is started. In this sequence the concerning driver is switched in sink condition for 32 µs to 64 µs to ensure a fast switch-off of the H-bridge transistor. Afterwards the driver is switched in the resistive output mode (resistive path to source).
3.5 Diagnostic functions
The diagnostic functions (over load, power supply over- and undervoltage, charge pump low, watchdog, temperature warning and internal/external thermal shutdown) are internally filtered and the condition has to be valid for at least 64 µs (6 µs for a short-circuit) before the corresponding status bit in the status registers is set. The filters are used to improve the noise immunity of the device. The internal temperature warning function is intended for information purpose and does not change the state of the output drivers. On the contrary, the over load condition switches the corresponding halfbridge in sink condition. The internal thermal shutdown condition and charge pump low disable all drivers (resistive low). The external thermal shutdown, watchdog, over- and undervoltage condition switch all driver in sink condition. The microcontroller needs to clear the status bits to reactivate the drivers.
3.6 Overvoltage and undervoltage detection
If the power supply voltage VS rises above the overvoltage threshold VVS_OVH (typical 20 V / 30 V), all gate driver stages are switched in sink condition to protect the H-bridge and the load, setting the OV bit. Two values for the overvoltage threshold can be selected with the SPI. When the voltage V S drops below the undervoltage threshold
VVS_UV, all gate driver stages are switched in the sink condition to avoid driving the power devices without sufficient gate driving voltage (increased power dissipation), setting the UV bit. In both cases, overvoltage and undervoltage detection, the charge pump is disabled. If the supply voltage V S recovers from UV/OV to normal operating voltage range and if the OV_UV_RD is set to 0, then the charge pump is automatically enabled. In any case, regardless of the OV_UV_RD bit value, the microcontroller needs to clear the status register to reactivate the gate drivers.
3.7 Charge pump
The charge pump uses 2 external capacitors. The output of the charge pump has a current limitation. In standby mode and after overvoltage, undervoltage or a thermal shutdown has been triggered the charge pump is disabled. If the charge pump output voltage remains too low for longer than T CP , all gate drivers are switched-off (resistive output, see Section 3.4). The CP_LOW bit has to be cleared through a software reset to reactivate the gate drivers.
3.8 Temperature warning and thermal shutdown
If junction temperature rises above TjTWON the temperature warning flag TW is set and is detectable via the SPI. If junction temperature increases above the second threshold T jSDON, the thermal shutdown bit (TSD) is set. The gate drivers and the charge pump are switched-off to protect the device. The gates of the H-bridge are discharged by the resistive low mode (see Section 3.4). In order to reactivate the output stages the junction temperature must decrease below T jS DO F F and the thermal shutdown bit has to be cleared by the microcontroller.
3.9 Short-circuit detection / drain source monitoring
The drain - source voltage of each activated external MOSFET of the H-bridge is monitored by comparators to detect shorts to ground or battery. If the voltage drop over the external MOSFET exceeds the threshold voltage V SCd for longer than the short current detection time tSCd the corresponding gate driver switches the external MOSFET off and the corresponding drain source monitoring flag (DS_MON [3:0]) is set. Until this failure flag is reseted the corresponding half bridge is in sink condition. The DS_MON bits have to be cleared through a software reset to reactivate the gate drivers. The drain source monitoring has a filter time of 6 µs. This monitoring is only active when the corresponding gate driver is in source condition. The threshold voltage V SCd can be programmed in 4 steps between 0.5 V and 2 V with the SPI.
3.10 Programmable cross current protection
The external Power MOSFET’s transistors in H-bridge (two halfbridges) configuration are switched-on with an additional delay time t CCP to prevent cross current in the halfbridge. The cross current protection time tCCP can be programmed with the SPI.
3.11 Current sense amplifier (CSA)
The current sense amplifier (CSA) is specially designed for current shunt automotive applications. It is a bidirectional, single-supply difference amplifier for amplifying small differential voltages in a wide common mode voltage range (-4 V to (V CP - 8) V). It supports the current measurement at two shunts. The result of respective shunt can be multiplexed to the microcontroller compatible output voltage by a SPI command. A gain of 50, 20 or 10 is SPI programmable. The inputs (CSI1+ / CSI1- and CSI2+ / CSI2-) are build as a transconductance stage. Therefore a series resistor (for filtering etc.) should not exceed 50 Ω to keep the additional gain error below 1%. The output works at half scale: V CSO0 = (0,5 * VCC) V for VIDIFF = 0 V. An internal offset measurement is in normal mode available with the "OFF_CAL" SPI-bit. If this bit is set to logic "1" the input pins are disconnected from the amplifier and a virtual zero input differential voltage is selected.
3.12 Thermal sensor interface / H-bridge switch-off input
The TS/ACT_OFF pin is configurable by SPI with the EXT_TS bit. This pin could be used as temperature sensor interface for the H-bridge or external off for all gate drivers. The output bias current ITS_bias is on for EN = high.
3.12.1 EXT_TS-bit = low (active off)
The TS/ACT_OFF input is used as a logic driver control input, without filter delay and without latching the information. Pulling the TS/ACT_OFF pin below the programmed threshold all gate drivers are switched-off and the OT_EXT bit is set. Increasing the voltage at TS/ACT_OFF pin above the programmed threshold the device remains to the status set by DIR and PWM-pins and the OT_EXT bit is reseted. The threshold is programmable by SPI with the registers EXTTH_5:0.
3.12.2 EXT_TS-bit = high (thermal sensor interface)
With the thermal sensor interface external diodes can be used to control the temperature of the external H-bridge. When the diode forward voltage decreases below the reference voltage for longer than the internal filter time (64 µs) the OT_EXT bit is set and the driver switches in resistive low (see Section 3.4: Resistive low). In this mode the OT_EXT-status-bit has to be cleared to reactivate the gate drivers. The threshold is programmable by SPI with the registers EXTTH_5:0.
3.13 Watchdog
The tasks of the watchdog is to monitor the microcontroller during normal operation within a nominal trigger cycle of 60 ms. The microcontroller has to restart the watchdog timer by sending the watchdog restart bit via SPI repeatedly within the watchdog time T WDTO. If no correct watchdog service is sent from the microcontroller, all gate drivers switch in sink
condition and the watchdog time out bit (WDTO) is set. Once the watchdog times out, the gate drivers can only be reactivated by sending a software reset.
L99H01 Functional description of the SPI
4 Functional description of the SPI
4.1 Signal description
4.1.1 Serial clock (CLK)
This input signal provides the timing of the serial interface. Data present at serial data input (DI) is latched on the rising edge of serial clock (CLK). Data on Serial Data Out (DO) is shifted out at the falling edge of serial clock (CLK). The serial clock CLK must be active only during a frame (CSN low phase). Any other switching of CLK close to any CSN edge could generate setup/hold violations in the SPI logic of the device.
4.1.2 Serial data input (DI)
This input is used to transfer data serially into the device. Values are latched on the rising edge of serial clock (CLK).
4.1.3 Serial data output (DO)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial clock (CLK). DO also reflects the status of the <Global Error Flag> (<Global Status Byte>[7]) while CSN is low and no clock signal is present.
4.1.4 Chip select not (CSN)
When this input signal is high, the communication interface of the device is deselected and serial data output (DO) is high impedance. Driving this input low enables the communication. The communication must start and stop on a low-level of serial clock (CLK). The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For timing details and figures refer to Section 2.5.
4.2 General data description
The SPI communication is based on a SPI interface structure using CSN (chip select not), DI (serial data in), DO (serial data out/error) and CLK (serial clock) signal lines. Each DI communication frame consists of a <Command Byte> which is followed by 1 <Data Byte>. The data returned on DO within the same frame always starts with the <Global Status Byte>, which provides general status information about the device. This byte is followed by 1 <Data Byte> (‘In-frame-response’).
4.2.1 Command byte
<Read Device Information>) and a 6-bit address.
- OCx: Operating code
- Ax: Address
4.2.2 OpCode definition
The <Write Mode> and <Read Mode> operations allow access to the RAM of the device. Table 24. DI Table 25. DO Table 26. Command byte Table 27. Operating code definition
L99H01 Functional description of the SPI More detailed descriptions of the device information are available in Section 4.7 .
4.3.1 Control and stat us (RAM) address map
4.3.2 Device (ROM) address map (access with OC0 and OC1 set to ‘1’)
Table 28. Control and status (RAM) address map Table 29. Device (ROM) address map (access with OC0 and OC1 set to ‘1’) (see Table 30: STK_RESET_Q).
4.4 Global status byte
This byte is shifted out first at DO at every SPI access. The GL_ER bit is present at DO with the falling edge of CSN. This byte could be reseted with the command <clear status>.
- GL_ER: Global error flag. This signal is a logical OR among all the errors of all the channels of the device.
- FE: Frame error. If the number of clock pulses within the previous frame is not 16 the frame is ignored and this bit is set.
- STK_RESET_Q: If a stuck at ‘1’ on SPI_DI during any SPI frame occurs, or if a power-on reset occurs. STK_RESET_Q is reset (‘1’) with any SPI command. When STK_RESET_Q is active (‘0’), the gate drivers are switched-off (see Section 3.4: Resistive low). After a startup of the circuit the STK_RESET_Q is active because of the POR pulse and the gate drivers are switched-off. The Gate drivers can only be activated after the STK_RESET_Q has been reset with a SPI command.
- TSD: Thermal shutdown due to an internal sensor. All the gate drivers and the charge pump must be switched-off (see Section 3.4: Resistive low). The gate drivers can only be activated after the TSD has been reset with a SPI command.
- TW: Thermal warning
- UV: Logical OR among the filtered undervoltage signals.
- OV: Logical OR among the filtered overvoltage signals.
- WDTO: Watchdog time out. Failures of <Global Status Register>[8:14] are always linked to the <Global Error Flag>. The <Global Error Flag> is generated by an OR combination of all failure events of the device (<Global Status Register>[8:14]). The flag is reflected via the DO pin while CSN is held low and no clock signal is available. The flag remains as long as CSN is low. This operation does not cause the <communication error> bit in the <Global Status Byte> to be set.
Table 30. STK_RESET_Q
4.4.1 SPI clock monitor and watchdog
Figure 11. Global error flag diagram
- Writing a “1” to RWD - bit in ApplRegx restarts the internal watchdog counter.
<frame error> in the <Global Status Byte> is set.
4.5 Detailed byte description of status register (StatReg0)
out at DO within the same frame (‘in-frame response’). address and the content of the register.
- DS_MON[3:0]: If max drain source voltage exceeds the defined thresholds, the DS_MON are set and the corresponding drivers go to sink mode. The DS_MON bits have to be cleared through a software reset to reactivate the drivers.
- OT_EXT: Depending on EXT_TS bit following two meanings exist: – EXT_TS = low (active off): TS/ACT_OFF pin is used as input to switch the H-bridge in tristate and back. Details are discribed in Section 3.12.1. – EXT_TS = high (thermal sensor interface): TS/ACT_OFF pin is used as thermal sensor interface for external temperature diodes. Details are discribed in Section 3.12.2.
- CP_LOW: If a charge pump output voltage low occurs, all gate drivers must be switched-off (resistive low). The CP_LOW bit has to be cleared through a software reset to reactivate the gate driver.
Table 31. Address 0<00(hex)>:StatReg 0 - read only
- The errors of the status register are not linked to the <Global Error Flag>.
Table 32. DS_MON - drivers relations
4.6 Detailed byte description of application registers (ApplRegX)
The write/read operation starts always with a command byte followed by 1 data byte.
4.6.1 Description of the data byte
the logic levels during a reset phase.
- RWD: Restarts the watchdog counter
- FW_PAS: Enables passive free wheeling according to Table 23
- OFF_CAL: Offset calibration mode for CSA
- OVT: Overvoltage threshold
- CLK_SPCTR: Switch the clock to the charge pump – 0: 125 Khz (50% duty cycle) – 1: pulses train (max = 8 µs, min = 2 µs) to optimize power spectrum
- OV_UV_RD: Over/undervoltage recovery disabled. – 0: If V S recovers from OV/UV condition to normal operating voltage range, the charge pump is automatically enabled; – 1: If V S recovers from OV/UV condition to normal operating voltage range, the charge pump remains disabled; In both cases the microcontroller has to clear the status register to enable the gate drivers
- DIAG[1:0]: Drain source monitoring threshold voltage
Table 33. Address 1 <01(hex)>:ApplReg1-read/write Table 34. Overvoltage threshold of the Vs monitoring Table 35. DIAG monitoring of source voltages
01 V SCD2 = 1 V
11 V SCD4 = 2 V
- RWD: Restarts the watchdog counter
- COPT[2:0]: Filter time to protect the two external halfbridges against cross current.
- FW: Selects high-side or low-side free wheeling
- MCSA: Multiplexer for current sense amplifier.
- GCSA[1:0]: Gain of the current sense amplifier.
Table 36. Address 2 <02(hex)>: ApplReg2 – read/write Table 37. Cross current protection time (tCCP) Table 38. Multiplexer for current sense amplifier
0 CSA2 (CSI2+ / CSI2-)
1 CSA1 (CSI1+ / CSI1-)
Table 39. Gain of current sense amplifier
- RWD: Restarts the watchdog counter
- EXT_TS: The bit select the mode of the input pin TS/ACT_OFF: – EXT_TS = low (active off): TS/ACT_OFF pin is used as input to switch the H-bridge in tristate and back. Details are discribed in Section 3.12.1. – EXT_TS = high (thermal sensor interface): TS/ACT_OFF pin is used as thermal sensor interface for external temperature diodes. Details are discribed in Section 3.12.2.
- EXTTH[5:0]: Determines the threshold of the external thermal shutdown/warning
Table 40. Address 3 <03(hex)> : ApplReg3 – read/write Table 41. External threshold voltage, factor n Table 42. External threshold voltage, factor m
series). With factor m the level of the threshold voltage can be fine tuned.
4.7 Read device information (ROM)
- FAM[1:0]: Family identifier, FAM[1:0] = [0:1] stands for ASSPs.
- NR_PI[5:0]: Number of product information bytes. The <Product Code 1 and 2> represents a unique identifier of the device and version.
Table 43. Read device information (ROM) device enters a fail-safe state (see Table 30: STK_RESET_Q). Table 44. Address 0 <00(hex)> : ID-header - read only(1)
- Addressable only through a r ead device information command.
Table 45. Address 1 <01(hex)>: product ID (LSB) - read only(1)
- Addressable only through a r ead device information command.
3 bytes) and the availability of ‘burst mode read’ option.
- BR: Burst mode read. Not supported
- AR5: Address width reduction. Not supported
- AR4: Address width reduction. Not supported
- AR3: Address width reduction. Not supported
- 32 bits: 32 bits frame width. Not supported
- 24 bits: 24 bits frame width. Not supported
- 16 bits: 16 bits frame width, 8 bits command and 8 bits data
- 8 bits: 8 bits frame width. Not supported
Table 46. Address 2 <02(hex)>: product ID (MSB) - read only(1)
- Addressable only through a r ead device Information command.
Table 47. Address 3 <03(hex)>: SPI frame ID - read only(1)
- Addressable only through a Read Device Information command.
5 Packages thermal data
Figure 12. PowerSSO-36 Rthj-amb vs. PCB copper area in open free air condition
- Layout condition of R th and Zth measurements (PCB: double layer, thermal vias,
Copper areas: from minimum pad layout to 8 cm 2).
Package and packing information L99H01
6 Package and packing information
6.1 ECOPACK ®
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
6.2 PowerSSO-36 package information
Figure 13. PowerSSO-36 package dimensions
Table 48. PowerSSO-36 mechanical data
- “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm
6.3 Packages thermal data
Figure 14. LQFP32 Rthj-amb vs. PCB copper area in open box free air condition
- Layout condition of Rth and Zth measur ements (PCB: double layer, thermal vias,
6.4 LQFP32 package information
Figure 15. LQFP32 package dimensions
Table 49. LQFP32 mechanical data
- LQFP stands for low profile quad flat pachage.
6.5 PowerSSO-36 packing information
Figure 16. PowerSSO-36 tube shipment (no suffix) Figure 17. PowerSSO-36 tape and reel shipment (suffix “TR”)
6.6 LQFP32 packing information
Figure 18. LQFP32 tape and reel shipment (suffix “TR”) Figure 19. LQFP32 tray shipment (no suffix)
7 Revision history
Table 50. Document revision history 17-Apr-2009 1 Initial release. Table 18: Current sense amplifier. Updated Table 23: Truth table. 19-Sep-2013 6 Updated disclaimer.