L99DZ70XPTR STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 47
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specifications
- 2.1 Absolute maximum ratings
- 2.2 ESD protection
- 2.3 Thermal data
- 2.4 Electrical characteristics
- 2.4.1 Outputs OUT1 - OUT11, ECV
- 2.5 SPI - Electrical characteristics
- 3 Application information
- 3.1 Dual power supply: VS and VCC
- 3.2 Wake up and active mode / standby mode
- 3.3 Charge pump
- 3.4 Diagnostic functions
- 3.5 Overvoltage and undervoltage detection at V
- 3.6 Overvoltage and undervoltage detection at V CC
- 3.7 Temperature warning and thermal shutdown
- 3.8 Inductive loads
- 3.9 Open load detection
- 3.10 Over-load detection
- 3.11 Current monitor
- 3.12 PWM inputs
- 3.13 Cross-current protection
- 3.14 Programmable soft-start function to drive loads with higher inrush current
- 3.15 Controller for electrochromic glass
- 4 Functional description of the SPI
- 4.1 General description
- 4.1.1 Chip Select Not (CSN)
- 4.1.2 Serial Data In (DI)
Features
■ One full bridge for 6 A load (Ron = 150 mΩ) ■ Two half bridges for 3 A load (Ron = 300 mΩ) ■ Two half bridges for 0.75 A load (Ron = 1600 mΩ) ■ One highside driver for 6 A load (Ron =9 0m Ω) ■ Two configurable highside drivers for up to 1.5 A load (Ron =5 0 0mΩ) or 0.4 A (Ron = 1800 mΩ) ■ Two highside drivers for 0.5 A load (Ron = 1600 mΩ) ■ Programmable softstart function to drive loads with higher inrush currents as current limitation value ■ Very low current consumption in standby mode S <6µ A t y p ; Tj ≤ 85 °C; ICC < 5 µA typ; Tj ≤ 85 °C) ■ Current monitor output for all highside drivers ■ Device contains temperature warning and protection ■ Openload detection for all outputs ■ Over-current protection for all otputs ■ Separated half bridges for door lock motor ■ PWM control of all outputs ■ Charge pump output for reverse polarity protection ■ STM standard serial peripheral interface (ST- SPI 3.0) ■ Control block for electrochromic element
Applications
■ Door actuator driver with 6 bridges for double door lock control, mirror fold and mirror axis control, highside driver for mirror defroster, bulbs and LEDs (replacement for L9950). Control block with external MOS transistor for charging / discharging of electrochromic glass.
Description
The L99DZ70XP is a microcontroller driven multifunctional door actuator driver for automotive applications. Up to five DC motors and five grounded resistive loads can be driven with six half bridges and five highside drivers. An electrochromic mirror glass can be controlled using the integrated SPI-driven module in conjunction with an external MOS transistor. The integrated SPI controls all operating modes (forward, reverse, brake and high impedance). Also all diagnostic information is available via SPI read. PowerSSO-36 Table 1. Device summary
1 Block diagram and pin description
Figure 1. Block diagram Table 2. Pin definition and functions Ground: reference potential. output is over-current protected.
10 Watt
connected. The output stage of both switches is a power DMOS transistor. output is over-current protected. Power supply voltage (external reverse protection required). (MSB, bit 23) is transferred first.
9 CM/
Current monitor output/PWM2 input. PWM input for the outputs OUT5, OUT8 and OUT10.
10 CSN
Chip Select Not input / Testmode.
12 VCC
13 CLK
Halfbridge outputs 4,5,6: see OUT1 (pin 3).
25 ECDR
Electrocromic driver output. an external MOSFET, otherwise it remains in high-impedance state. as long as the electrochome mode is not enabled via SPI. MOS used for reverse polarity protection (see Figure 1.). Table 2. Pin definition and functions (continued)
27 PWM1
and OUT11 and ECV by an external PWM signal. Highside driver outputs 7,8: see OUT9.
32 ECV
Electrochrome voltage input and lowside driver output. This input senses voltage in electrocrome mode for charge monitoring. can be used 'stand alone' as lowside switch beside electrocromic mode.
33 OUT9
output is over-current and open load protected.
34 OUT10
Highside driver output 10: see OUT9. on setting bit1 for electrocromic control mode with higher priority.
Figure 2. Configuration diagram (top view) Note: All pins with the same name must be externally connected.
2 Electrical specifications
2.1 Absolute maximum ratings
Program and other relevant quality document.
2.2 ESD protection
Table 3. Absolute maximum ratings Table 4. ESD protection
- HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A.
- HBM with all unzapped pins grounded.
2.3 Thermal data
2.4 Electrical characteristics
VS = 8 to 16V, VCC= 4.5 to 5.3V, Tj = - 40 to 150°C, unless otherwise specified. Table 5. Operating junction temperature Table 6. Temperature warning and thermal shutdown Table 7. Supply
7.1 VS Operating voltage
7.3 VS quiescent supply
- This parameter is guaranteed by design.
Table 8. Overvoltage and under voltage detection
8.6 V SOV hyst VS OV-hysteresis V SOV OFF - VSOV ON 1V
8.9 V POR hyst
Table 9. Current monitor output CM / PWM 2
9.1 V CM
Table 7. Supply (continued)
2.4.1 Outputs OUT1 - OUT11, ECV
- FS (full scale)= IOUTmax * ICM,r .
Table 10. Charge pump output CP
10.2 V S = 10V, ICP = -80µA V S+8 V S+13 V
10.3 V S >=12V, ICP = -100µA V S+10 V S+13 V
10.4 I CP
Table 9. Current monitor output CM / PWM 2 (continued) Table 11. On-resistance and switching times
11.13 On-resistance to
11.18 VOUT= 0V,
Table 11. On-resistance and switching times (continued)
11.20 VOUT= 0V,
11.22 VOUT= 0V,
11.23 Switched-off output
11.24 VOUT= VS,
- Rload = 16 Ω at OUT1, 6 and 7,8 in low on-resistance mode.
- Rload = 64 Ω at OUT2, 3, 9, 10, ECV and 7, 8 in high On-resistance mode.
- t cc is the switch-on delay time if complement in half bridge has to switch-off.
Table 12. Current monitoring
12.12 IIOLD1I,
12.13 IIOLD2I,
12.14 IIOLD4I,
12.15 IIOLD9I,
12.16 II OLD11 I 30 150 300 mA
12.19 IIOLDECVI Under-current
Table 13. Electrochrome control
13.3 DNL Differential non linearity -1 1 LSB (2)
13.4 IdV ECVI
13.7 V ECDRmin_high
Table 12. Current monitoring (continued)
Figure 3. Electrochrome control block diagram
2.5 SPI - Electrical characteristics
13.11 R ecdrdis
13.12 I QECDR Quiescent current VECDR = VS;
- Bit 7 to 2 = ‘1’ control register 1: ECV voltage, where II ECDR can change sign.
- 1 LSB (Least Significant Bit)= 23.8 mV.
Vtarget is set by bit 7 to 2 of control register 1 and bit 0 of control register 2; tested for each individual bit. Table 13. Electrochrome control (continued)
Table 14. Delay time from standby to active mode set bit 0=1 of control register 0. Table 15. Inputs: CSN, CLK, PWM1/2 and DI
15.3 V in Hyst Input hysteresis V CC = 5V 500 mV
15.4 R CSN in CSN pull up resistor VCC = 5V
15.5 R CLK in CLK pull down resistor VCC = 5V
15.6 R DI in DI pull down resistor VCC = 5V
15.7 R PWM1 in PWM1 pull down resistor VCC = 5V
15.8 C in
- Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 16. SDI timing (1)
- DI timing parameters tested in production by a passed / failed test:
Tj= -40°C / +25°C: SPI communication @ 2MHz. Tj= +125°C SPI communication @ 1.25 MHz. Table 17. DO
17.3 I DOLK
17.4 C DO
- Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 18. DO timing Table 16. SDI timing (continued) (1)
Figure 4. SPI - Transfer timing diagram Figure 5. SPI - Input timing Table 19. CSN timing
0.8 VCC
0.2 VCC
Figure 6. SPI - DO valid data delay time and valid time Figure 7. SPI - DO enable and disable time
0.5 VCC
Figure 8. SPI - driver turn on/of f timing, minimum CSN HI time
Application information L99DZ70XP 24/47 Doc ID 15162 Rev 4
3 Application information
3.1 Dual power supply: V S and VCC
The power supply voltage VS supplies the half bridges and the highside drivers. An internal charge-pump is used to drive the highside switches. The logic supply voltage VCC is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage.
3.2 Wake up and active mode / standby mode
After power up of VS and Vcc the device operates in standby-mode. Pulling the signal CSN to low level wakes the device up and the analog part will be activated (active mode). After at least 10µs, the first SPI communication is valid and bit 0 of the Control Register 0 can be used to set the EN-mode. If bit 0 is not set to 1, the device doesn't remain in the active mode. After at least 256µs all latched data will be cleared and the inputs and outputs are switched to high impedance. In standby mode the current at V S (VCC) is less than 6 µA (5 µA) for CSN = high (DO in tristate).
3.3 Charge pump
In standby mode the chargepump is turned off. After enabling the device by SPI command (bit0=1 Control Register 0) the oscillator starts and the voltage begins to increase. The output drivers are enabled after at least 256 µs after CSN went to high.
3.4 Diagnostic functions
All diagnostic functions (over/under-current, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered. The condition has to be valid for at least 32 µs (open load: 1ms) before the corresponding status bit in the status registers is set. The filters are used to improve the noise immunity of the device. The under-current and temperature warning functions are intended for information purpose and will not change the state of the output drivers. On contrary, the over-current condition disables the corresponding driver and thermal shutdown disables all drivers. Without setting the over- current recovery bits in the input data register, the microcontroller has to clear the over- current status bits to reactivate the corresponding drivers.
3.5 Overvoltage and undervoltage detection at V S
If the power supply voltage VS rises above the overvoltage threshold VSOV OFF (typical
21 V), the outputs OUT1 to OUT11, ECDR and ECV are switched to high impedance state
to protect the load. When the voltage VS drops below the undervoltage threshold V SUV OFF (UV-switch-OFF voltage), the output stages are switched to high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage V S recovers (control register 3: bit 4=0) to normal operating voltage then the outputs stages return to the programmed state. If the undervoltage/overvoltage recovery disable bit is set (control register 3: bit 4=1), the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers. It is recommended to set bit1 control register 3 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage.
3.6 Overvoltage and undervoltage detection at V CC
In case of power-on (VCC increases from undervoltage to VPOR OFF = 2.9 V) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases below the minimum threshold (V POR ON = 2.0 V), the outputs are switched to tristate (high impedance) and the status registers are cleared.
3.7 Temperature warning and thermal shutdown
If the junction temperature rises above Tj TW, a temperature warning flag is set after at least 32 µs and it can be read via the SPI. If the junction temperature increases above the second threshold T jS D, the thermal shutdown bit is set and the power DMOS transistors of all output stages are switched off to protect the device after at least 32 µs. The temperature warning and thermal shutdown flags are latched and the bits must be cleared by the microcontroller. This is possible only if the temperature has decreased below trigger temperature. If the thermal shutdown bit has been cleared the output stages are reactivated.
3.8 Inductive loads
Each half bridge is built by internally connected highside and lowside power DMOS transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT6 without external free-wheeling diodes. The highside drivers OUT7 to OUT11 are intended to drive resistive loads. Therefore only a limited energy (E<1mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L>100µH) an external free-wheeling diode connected between GND and the corresponding output is required. The low side driver at ECV does not have a freewheel diode built into the device.
Application information L99DZ70XP 26/47 Doc ID 15162 Rev 4
3.9 Open load detection
The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.
3.10 Over-load detection
In case of an over-current condition a flag is set in the status register in the same way as during open load detection. If the over-current signal is valid for at least t ISC(typ) = 55 µs, the over-current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero, the microcontroller has to clear the status bits to reactivate the corresponding driver.
3.11 Current monitor
The current monitor output sources a current image at the current monitor output which has two fixed ratios of the instantaneous current of the selected highside driver. Outputs with a resistance of 500 mΩ and higher have a ratio of 1/2000 and those with a lower resistance of 1/10000. The signal at output CM is blanked after switching on the driver until correct settlement of the circuitry (at least for 64 µs). The bits 0 to 3 of the control register 3 define which of the outputs are multiplexed to the current monitor output CM/PWM2. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example it can be used to detect the motor state (starting, free-running, stalled). Moreover, it is possible to control the power of the defroster more precisely by measuring the load current. The current monitor output is bidirectional (PWM inputs).
3.12 PWM inputs
Each driver has a corresponding PWM enable bit, which can be programmed by the SPI interface. If the PWM enable bit is set in control registers 2 or 3, the output is controlled by the logically AND-combination of the PWM signal and the output control bit in Control Registers 0 and 1. The outputs OUT1-4, 6, 7, 9, OUT11 are controlled by the PWM1 input and the outputs OUT5, 8 and OUT10 are controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be used to dim two lamps independently by external PWM signals. In case of switching off a high/low side switch in PWM mode a minimum off time of appr. (256 µs – td on+ tdoff) is predefined by the state machine, to avoid switching on the high/low side again during the negative slope. For a PWM frequency of 100Hz this means the maximum duty cycle is about 98%. Larger duty cycles can be realized by applying pulse skipping.
3.13 Cross-current protection
off before the opposite driver starts to conduct.
3.14 Programmable soft-start function to drive loads with higher
bridge output, if the associated high-side driver has been used in recovery mode before. Figure 9. Example of programmable soft -start function for inductive loads
Application information L99DZ70XP 28/47 Doc ID 15162 Rev 4
3.15 Controller for electrochromic glass
The voltage of an electrochromic element connected at pin ECV can be controlled to a target value, which is set by the bits 7 down to 2 of control register 1. Setting bit 1 of control register 1 enables this function. An on-chip differential amplifier and an external MOS source follower, with its gate connected to pin ECDR and which drives the electrochrome mirror voltage at pin ECV, form the control loop. The drain of the external MOS transistor is supplied by OUT10. A diode from pin ECV (anode) to pin ECDR (cathode) has been placed on the chip to protect the external MOS source follower. A capacitor of at least 5 nF has to be added to pin ECDR for loop-stability. The target voltage is binary coded with a full scale range of 1.5V. If Bit 0 of control register 2 is set to '1', the maximum controller output voltage is clamped to 1.2V without changing the resolution of bits 7-2 of control register 1. When setting the target voltage to 0V and programming the ECVLS driver to on-state, the voltage at pin ECV is pulled to ground by a 1.6 Ohm low-side switch (fast discharge). The status of the voltage control loop is reported via SPI. Bit 0 in the status register 2 is set, if the voltage at pin ECV is higher, whereas Bit 1 in the same status register is set, if the voltage at pin ECV is lower than the target value. Both status bits are valid, if they are stable for at least 150 µs. Since OUT10 is the output of a high-side driver, it contains the same diagnose functions as the other high-side drivers (e.g. During an over current detection, the control loop is switched off). In electrochrome mode OUT10 cannot be controlled by PWM mode. For EMS reasons the loop capacitor at pin ECDR as well as the capacitor between ECV and GND have to be placed to the respective pins as close as possible.
L99DZ70XP Functional description of the SPI Doc ID 15162 Rev 4 29/47
4 Functional description of the SPI
4.1 General description
Standard ST-SPI Interface Version 3.0. The SPI communication is based on a Serial Peripheral Interface interface structure using CSN (Chip Select Not), DI (Serial Data In), DO (Serial Data Out/Error) and CLK (Serial Clock) signal lines.
4.1.1 Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) is in high impedance state. A low signal wakes up the device and a serial communication can be started. The state when CSN is going low until the rising edge of CSN will be called a communication frame.
4.1.2 Serial Data In (DI)
The input pin is used to transfer data serially into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal.
4.1.3 Serial Clock (CLK)
This input signal provides the timing of the serial interface. The Data Input (DI) is latched at the rising edge of Serial Clock CLK . The SPI can be driven by a micro controller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. Data on Serial Data Out (DO) is shifted out at the falling edge of the serial clock (CLK). The serial clock CLK must be active only during a frame (CSN low). Any other switching of CLK close to any CSN edge could generate set up/hold violations in the SPI logic of the device. The clock monitor counts the number of clock pulses during a communication frame (while CSN is low). If the number of CLK pulses does not correspond to the frame width indicated in the <SPI-frame-ID> (ROM address 03H) the frame is ignored and the <frame error> bit in the <Global Status Byte> is set. Note: Due to this safety functionality, daisy chaining the SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.
4.1.4 Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the global status bit 7 (Global Error Flag). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
4.1.5 SPI communication flow
SPI frame length (24 bit) and the availability of additional features. Each communication frame consists of a command byte which is followed by 2 data bytes. Byte. It provides general status information about the device. It is followed by 2 data bytes (i. Figure 10. Write and read SPI
4.2 Command byte
are unused but are reserved.
4.2.1 Operation code definition
The <Write Mode> and <Read Mode> operations allow access to the RAM of the device. Table 20. SPI frame Table 21. Operation code definition
4.3 Global status byte
- GL_ER : Global Error Flag. Failures of Bits 0-6 are always linked to the Global Error Flag. This flag is generated by an OR combination of all failure events of the device. It is reflected via the DO pin while CSN is held low and no clock signal is available. The flag will remain as long as CSN is low. This operation does not cause the Communication Error bit in the <Global Status> to be set. The signal TW bit3 and OL bit1can be masked.
- CO_ER : Communication Error. If the number of clock pulses within the previous frame is not 24 the frame is ignored and this bit is set.
- C_RESET : Chip RESET. If a stuck at ‘1’ on input DI during any SPI frame occurs, or if a Power On Reset (VCC monitor) occurs. C_RESET will be reset (‘1’) with any SPI command. When STK_RESET_Q is active (‘0’), the Gate drivers are switched off (resistive path to source). After a startup of the circuit the STK_RESET_Q is active because of the POR pulse and the Gate drivers are switched off. The Gate drivers can only be activated after the STK_RESET_Q has been reset with a SPI command.
- TSD : Thermal shutdown due to an internal sensor. All the gate drivers and the charge pump must be switched off (resistive path to source). The TSD bit has to be cleared through a software reset to reactivate the gate drivers and the charge pump.
- TW : Thermal Warning. This bit is maskable by configuration register.
- UOV_OC : Logical OR among the filtered under-/over-voltage signals and over-current signals.
- OL : Open Load. Logical OR among the filtered under-current signals. This bit is maskable by configuration register.
- NR : Not Ready. After switching the device from standby mode to active mode an internal timer is started to allow chargepump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished.
Table 22. Global status byte
Figure 11. Global error flag definition
4.4 Address mapping
Table 23. RAM memory map Table 24. ROM memory map
5 SPI - control and status registers
5.1 Control register 0
Table 25. Control register 0 (read/write)
15 OUT1 – HS
simultaneously in order to avoid a high internal current from Vs to GND.
14 OUT1 – LS
13 OUT2 – HS
12 OUT2 – LS
11 OUT3 – HS
10 OUT3 – LS
9 OUT4 – HS
8 OUT4 – LS
7 OUT5 – HS
6 OUT5 – LS
5 OUT6 – HS
4 OUT6 – LS
cleared, the device enters standby mode and all bits are cleared.
5.2 Control register 1
Table 26. Control register 1 (read/write)
15 OUT7 – HS1
14 OUT7 – HS2
11 O f f
13 OUT8 – HS1
12 OUT8 – HS2
00 O f f
11 OUT9 – HS
to avoid a high internal current from VS to GND.
10 OUT10 – HS
9 OUT11 – HS
8 ECV – LS on/off
7 EC bit 5
Reference value for difference voltage amplifier at pin ECV is binary coded. at pin ECV, if the ECV – LS on/off bit is set to '1'..
6 EC bit 4
5 EC bit 3
4 EC bit 2
3 EC bit 1
2 EC bit 0
1 EC switch
VS to the load at ECV can be monitored.
5.3 Control register 2
Table 27. Control register 2 (read/write)
15 OUT1 – OCR
a programmable duty cycle (bit 5 of control register 3). (bit1=1 control register 1).
14 OUT2 – OCR
13 OUT3 – OCR
12 OUT4 – OCR
11 OUT5 – OCR
10 OUT6 – OCR
9 ECV – OCR
7 OUT1 PWM1
by PWM2 input, all other outputs are controlled by PWM1 input.
6 OUT2 PWM1
5 OUT3 PWM1
4 OUT4 PWM1
3 OUT5 PWM2
2 OUT6 PWM1
1 ECV PWM1
0 ECV-low voltage
resolution of the DAC. This is the default mode.
5.4 Control register 3
Table 28. Control register 3 (read/write)
15 OUT7-OCR enable In case of an over-current event the over-current status bit (Status
14 OUT8-OCR enable
13 OUT9-OCR enable
12 OUT10-OCR enable
11 OUT11-OCR enable
10 OUT7 PWM1 enable
9 OUT8 PWM2 enable
8 OUT9 PWM1 enable
7 OUT10 PWM2 enable
6 OUT11 PWM1 enable
4 OV/UVR disable If this bit is set the microcontroller has to clear the status register
after undervoltage/overvoltage event to enable the outputs.
3 CM select bit 3
CM/PWM2 output (see table below). Other combinations deactivate the current monitor.
2 CM select bit 2
1 CM select bit 1
0 CM select bit 0
5.5 Status register 0
Table 29. Status register 0 (read)
15 OUT1 – HS OC
PWM modulated current with a programmable duty cycle. the over-current bit to reactivate the output driver.
14 OUT1 – LS OC
13 OUT2 – HS OC
12 OUT2 – LS OC
11 OUT3 – HS OC
10 OUT3 – LS OC
9 OUT4 – HS OC
8 OUT4 – LS OC
7 OUT5 – HS OC
6 OUT5 – LS OC
5 OUT6 – HS OC
4 OUT6 – LS OC
5.6 Status register 1
Table 30. Status register 1 (read)
15 OUT1 – HS UC Maskable by the
13 OUT2 – HS UC
mechanical/electrical state of the loads.
12 OUT2 – LS UC
11 OUT3 – HS UC
10 OUT3 – LS UC
9 OUT4 – HS UC
8 OUT4 – LS UC
7 OUT5 – HS UC
6 OUT5 – LS UC
5 OUT6 – HS UC
4 OUT6 – LS UC
5.7 Status register 2
Table 31. Status register 2 (read)
15 OUT7 – OC
PWM modulated current with a programmable duty cycle. over-current bit to reactivate the output driver. mechanical/electrical state of the loads.
14 OUT7 – UC
13 OUT8 – OC
12 OUT8 – UC
11 OUT9 – OC
10 OUT9 – UC
9 OUT10 – OC
8 OUT10 – UC
6 OUT11 – UC
4 ECV – UC
1 ECV voltage not
not assigned to the Global Error Flag.
0 ECV voltage
5.8 Configuration register
Table 32. Configuration register (read/write)
5 Mask for bit 15 of
considered in openload bit 1 of global status register.
4 Mask for bit 14 of
considered in openload bit 1 of global status register.
3 Mask for bit 3 of
1 Mask for bit 1 of
6 Packages thermal data
Figure 12. Packages thermal data
7 Package and packing information
7.1 ECOPACK ® packages
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
7.2 PowerSSO-36 package information
Figure 13. PowerSSO-36 package dimensions
Table 33. PowerSSO-36 mechanical data
- “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm
7.3 PowerSSO-36 packing information
Figure 14. PowerSSO-36 tube shipment (no suffix) Figure 15. PowerSSO-36 tape and reel shipment (suffix “TR”)
8 Revision history
Table 34. Document revision history 12-Nov-2008 1 Initial release. 22-Sep-2013 4 Updated Disclaimer.