L9960 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 95
Technical content
Datasheet sections
- 1 Block diagram and pin descripti on
- 1.1 Block diagram
- 1.2 Pin description
- 1.2.1 PowerSSO36 package
- 2 Application description
- 2.1 Application circuit
- 2.2 Bill of materials
- 3 General electrical characteris tics
- 3.1 Absolute maximum ratings
- 3.2 Thermal ratings
- 3.3 Range of functionality
- 3.4 Electrical characteristics
- 3.5 Timing characteristics
- 4 Functional description
- 4.1 Device supply
- 4.1.1 Functional State
- 4.1.2 Vps power supply
- 4.1.3 VDD5 regulated voltage supply
- 4.1.4 VDDIO voltage supply
- 4.1.5 Device supply electrical characteristics
- 4.2 Power on reset (POR) and SW reset
- 4.2.1 Power on reset (POR) electrical characteristics
- 4.3 System clock electrical characteristics
- 4.4 Hardware self check (HWSC) and LBIST
- 4.4.1 HWSC test procedure
- 4.4.2 HWSC/LBIST electrical characteristics
- 4.5 Digital input controls
- 4.5.1 Bridge functional modes
- 4.5.2 Disable inputs DIS and NDIS
- 4.5.3 Control inputs DIR and PWM
- 4.5.4 Digital inputs control elec trical characteristics
Features
AEC-Q100 qualified Flexible driving strategy via configurable pins PWM/DIR (IN1/IN2) RDSon < 400 mΩ (full path at Tj =150° C) Operating battery supply voltage from 4.5 V up to 28 V Operating VDD5 supply voltage from 4.5 V to 5.5 V Input switching frequency up to 20 kHz Built in charge pump supporting 100% duty cycle Logic levels compatible to 3.3 V and 5 V Monitoring of VDD5 supply voltage with bidirectional switch-off pin Current limitation SPI-adjustable in four steps. Output stage current limitation with dependence on temperature 2 Programmable voltage and current slew rate control Short circuit and programmable thermal warning and shutdown thresholds Open Load diagnosis in ON condition All I/O pins can withstand up to 19 V SPI interface for configuration and diagnosis Two independent enable/disable pins NDIS and DIS and SOPC (Switch-off Path Check) available Spread Spectrum function for EMI reduction Available in single (L9960) and Twin (L9960T) option, both in PSSO36 package
Description
The device is an integrated H-Bridge for resistive and inductive loads for automotive applications. Target application includes throttle control actuators, exhaust gas recirculation control valves and general purpose DC motors such as turbo, flap control and electric pumps. The driving strategy is enhanced by configurable PWM / DIR pins and IN1/IN2. The H-Bridge contains integrated free-wheel diodes. In case of freewheeling condition, the low-side only is switched on in parallel of its diode to reduce power dissipation. The integrated Serial Peripheral Interface (SPI) makes it possible to adjust device parameters, to control all operating modes and read out diagnostic information. GAPGPS00337 PowerSSO-36 Table 1. Device summary
L9960, L9960T Contents 4.7.3 Short-circuit to battery: ov er-current detection in low-side transistors . . 57 4.7.4 Short-circuit to ground: o ver-current detection in high-side transistor . . 58
4.8 Diagnostics and registers descriptions in case of validity b it configuration 60
1 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram for L9960
1.2 Pin description
1.2.1 PowerSSO36 package
Figure 2. Pin connection of L9960 version (top view) Figure 3. Pin connection of L9960T version (top view)
Table 2. Pin definition (PSSO36twin die) and function
1 PGND1 Power Ground GND
2 SCLK1 SPI Serial Clock I nput (internal pull-up) I
3 SDI1 SPI Data In Inpu t (internal pull-up) I
7 NDIS1 Bidirectional Enable pin: open drain output pulled low in case of VDD
8 AGND1 Analog Ground pin GND
9 VDD5 Regulated 5V supply I
10 NC Not connected pin
28 NC Not connected pin -
33 CP1 Charge Pump output O
34 DIS1 Disable pin: if it is pull ed high Out1-2 are in tri-state (internal pull-up) I
35 NCS1 SPI Chip Select I nput (internal pull-up) I
- For L9960 version in PSSO36, the pins from 11 to 26 are not c onnected.
Table 2. Pin definition (PSSO36twin die) and function (continued)
2 Application description
Generic DC or Stepper motors driving. requirements) and an over-voltage protection diode (optional).
2.1 Application circuit
Figure 4. Application circuit
2.2 Bill of materials
Table 3. Application circuit - BOM
3 General electrical characteristics
3.1 Absolute maximum ratings
Note: Test circuit according to HBM (EIA/JESD22-A114-B) and CDM (EIA/JESD22-C101-C). Table 4. Absolute maximum ratings
3.2 Thermal ratings
3.3 Range of functionality
Currents are positive into and negative out of the specified pin. Table 5. Thermal ratings Table 6. Range of functionality
- The device is qualified accord ing to mission profile covering 1300 hrs at Tj = 170 °C.
Figure 5. Example of VDD5 slopes
3.4 Electrical c haracteristics
Tj = -40°C to 150°C unless otherwise specified. VDD5 = 4.5V to 5.5V unless otherwise specified. Vps = 4V to 28V unless otherwise specified. All voltages refer to GND. Currents are positive into and negative out of the specified pin. Table 7. Bridge output drivers
3.5 Timing characteristics
Table 8. Timing characteristics
4 Functional description
4.1 Device supply
VDDIO, the supplying SDO output buffer voltage.
4.1.1 Functional State
rate, current limitation and overcurrent thresholds, OT warning thresholds). without dedicated fault recovery procedure. or undervoltage on VDD5, the H-bridge is set to tri-state with NDIS low. Note: Please review the dedicated Section 4.8.1: Diagnostic Reset strategy in application note.
4.1.2 Vps power supply
the EMC requirements, and an over-voltage protection diode can also be added (optional). Figure 6. External power supply circuitry
of functionality (Vps and temperature ranges). current delivered to the load and the High-Side Power MOS supply consumption. "Tvps_uv", the bridge is disabled (SPI communication is still working). glitches when Vps increases as well as decreases. necessary to restart the H-bridge if the condition is disappeared. The info is available in position R0 of the answer frame 8a. The information is also readable by VPS_UV_REG bit which is latched. The info is available in position R5 of the answer frame 8a. Table 9. VPS_UV
0 Vps > Vps_uv longer than Tvps_uv Default value
1 Vps < Vps_uv longer than Tvps_uv -
Table 10. VPS_UV_REG
Tj = -40 °C to 150 °C, VDD5 = 4.5 V to 5.5 V, Vps = 4 V to 28 V unless otherwise specified. All voltages refer to GND. Currents are positive into and negative out of the specified pin. is set to 1 and the bridge is disabled. Note: (-) available in position D3 of the SPI command frame 4. Note: (-) available in position R3 of the SPI answer frame 7b. Table 11. VPS electrical characteristics Table 12. UV_PROT_EN
0 Counter and disabling protecti on are not enabled Reset value
1 Counter and disabling protection are enabled -
Table 13. UV_PROT_EN_echo
0 Echo counter and disabling pr otection not enabled Reset value
1 Echo counter and disab ling protection enabled -
Note: (-) available in position D0 of the SPI command frame 4. Note: (-) available in position R0 of the SPI answer frame 7b. Note: (-) available in position R5 of the SPI answer frame 8c. bridge, when the battery level is below “vps_uv threshold”. time frame defined by UV_WIN. been enabled via UV_PROT bit, the H-bridge keeps on switching between On-state and tri-state. Figure 7. Battery voltage monitoring – case1 Table 14. UV_WIN
0 UV_WIN window is set to 20 µs Reset value
1 UV_WIN window is set to 40 µs -
Table 15. UV_WIN_echo
0 Echo: UV_WIN window is s et to 20 µs Reset value
1 Echo: UV_WIN windo w is set to 40 µs -
Table 16. UV_CNT_REACHED
0 No VS under voltage events clo ser than UV_WIN Default Value
1 Two VS under voltage eve nts closer than UV_WIN -
Figure 8. Battery voltage monitoring – case2 bridge is set in Disable condition consequently.
4.1.3 VDD5 regulated voltage supply
corresponding L9960 digital I/O's. parametric table with condition VDD5 <0.7V. thresholds, however, the absolute maximum rating is defined up to 19 V DC. "VDD5_uv_th" longer than a filter "TVDD5_uv1", the bridge is switched to disable. pin NDIS, NDIS pin is pulled to LOW. was hold at least for a minimum time “Thold_ndis”. (latched) and VDD_UV (unlatched).
Note: (-) available in position R1 of the SPI answer frame 8a. Note: (-) available in position R0 of the SPI answer frame 12b. Figure 9. VDD5 under voltage monitoring to LOW after the filter time “TVDD5_ov ”. Table 17. VDD_UV_REG
0 Latched Vdd > Vdd_uv longer than Tvdd_uv1 Default Value
1 Latched Vdd < Vdd_uv longer than Tvdd_uv1 -
Table 18. VDD_UV
0 Vdd > Vdd_uv longer than Tvdd_uv1 Default Value
1 Vdd < Vdd_uv longer than Tvdd_uv1 -
Note: (-) available in position R2 of the SPI answer frame 8a. Note: (-) available in position R1 of the SPI answer frame 12b. condition is removed (hysteresis as well as TVDD5_ov filtering implemented). Figure 10. VDD5 over voltage monitoring A counter is available to inform about the overvoltage event length (guaranteed by scan). The counter starts as soon as VDD5_OV event occurs. when the VDD5_OV condition is removed. The VDD5_OV length information is readable in a latched 3 bits word called VDD5_OV_L. Table 19. VDD_OV_REG
0 Latched Vdd < Vdd_ov_th long er than Tvdd_ov Default Value
1 Latched Vdd > Vdd_ov_th longer than Tvdd_ov -
Table 20. VDD_OV
0 Vdd < Vdd_ov_th longer than Tvdd_ov Default value
1 Vdd > Vdd_ov_th longer than Tvdd_ov -
Note: (-) available in positions R11/R10/R9 of the SPI answer frame 12a. event length is shorter than the value defined in VDD5_OV_L. condition is removed or the counter itself has reached its max value. Table 21. VDD_OV_L[2:0]
001 No VDD_OV event - default value
010 T_vdd_ov 10 ms -
Tj = -40 °C to 150 °C, VDD5 = 4.5 V to 5.5 V, Vps = 4 V to 28 V unless otherwise specified. All voltages refer to GND. Currents are positive into and negative out of the specified pin.
4.1.4 VDDIO voltage supply
dedicated to supply the output buffer of SDO. The overall current consumption on VDDIO is "IVDDIO". Table 22. VDD5 voltage monitoring Electrical characteristics
- Extended range of temperature (150, 170 °C)
4.1.5 Device supply elec trical characteristics
Tj = -40 °C to 150 °C, VDD5 = 4.5 V to 5.5 V, Vps = 4 V to 28 V unless otherwise specified. All voltages refer to GND. Currents are positive into and negative out of the specified pin.
4.2 Power on reset (POR) and SW reset
input has a hysteresis to avoid unstable behaviors during ramp up and down of VDD5. The POR is active for VDD5 from 0V to [Vpor + Vpor_hys] (POR threshold + hysteresis). When RESET state is active, the bridge is switched to tri-state. implemented), the L9960 starts with all the settings reset to their default values. In Figure 11 is shown an example of POR timing diagram. Table 23. Device supply electrical characteristic
to Normal Mode after the first PWM transition. Figure 11. POR timing diagram Note: (-) available in positions D10/D9 of the SPI command frame 2. The SW reset lasts 2-clock periods. This reset is asynchronous, with a synchronous release. cleared by read back via SPI. Once cleared, this bit indicates a further Power On Reset. Note: (-) available in the R11 bit position in SPI answer frame 7e. Table 24. SW reset [1:0]
01 SW reset command -
Table 25. POR status
0 After SPI reading (not su bmitted to DIAG_CLR_EN) -
4.2.1 Power on reset (POR) e lectrical characteristics
Tj = -40 °C to 150 °C, VDD5 = 4.5 V to 5.5 V, Vps = 4 V to 28 V unless otherwise specified. All voltages refer to GND. Currents are positive into and negative out of the specified pin.
4.3 System clock electr ical characteristics
Tj = -40 °C to 150 °C, VDD5 = 4.5 V to 5.5 V, Vps = 4 V to 28 V unless otherwise specified. All voltages refer to GND. Currents are positive into and negative out of the specified pin. is a reduction on emission peak values by spreading the energy in the frequency domain. Note: (-) available in the R2 position in SPI answer frame 4. Note: (-) available in the R2 position of the SPI answer frame 7b. Table 26. POR electrical characteristics Table 27. System clock electrical characteristics Table 28. NSPREAD
0 Spread Spectrum Activate Reset value
1 Spread Spectrum Disable -
Table 29. NSPREAD_echo
4.4 Hardware self check (HWSC) and LBIST
The target of the LBIST is to cover the disable path of the device, for safety aspects. HWSC/LBIST_done = "0") the bridge outputs remain disabled in tri-state. passed, it cannot be triggered again and the SPI answer remains the same. HWSC/LBIST can be re-triggered only in case of FAIL result, or SW reset. MISO response in case of SW reset and for HWSC trigger.
4.4.1 HWSC test procedure
At the same time, the filters “Thwsc_fil”, “Thwsc_ref” and “Thwsc_dur” are started. "Thwsc_dur" indicates the duration of the LBIST test. “Thwsc_fil” has expired the HWSC status bits are set to indicate that the test has failed. voltage returns back to the VDD5 over voltage disable threshold “Vdd_ov_th”. VDD5 over voltage threshold. Table 30. HWSC/LBIST Trigger
0 HWSC/LBIST not requested Reset value
Figure 12. HWSC timing diagram set to "1", independently of the HWSC result. In case the HWSC has failed or is not done, all outputs are disabled. Note: (-) available in the R8/R7/R6 positions in SPI answer frame 8a. Table 31. HWSC/LBIST_status
100 HWSC/LBIST done - HWSC FAIL/LBIST FAIL
101 HWSC/LBIST done - HWSC running/LBIST PASS
110 HWSC/LBIST done - HWSC FAIL/LBIST PASS
111 HWSC/LBIST done - HWSC PASS/LBIST PASS
Figure 13. HWSC state diagram
4.4.2 HWSC/LBIST elect rical characteristics
Tj = -40 °C to 150 °C, VDD5 = 4.5 V to 5.5 V, Vps = 4 V to 28 V unless otherwise specified. All voltages refer to GND. Currents are positive into and negative out of the specified pin. Table 32. HWSC/LBIST electrical characteristics
6.1 VDD5_ov_hw VDD5 over-voltage disable
6.2 Thwsc_ch_ov Analog settling time for changing
6.3 Thwsc_dur HWSC duration time (guaranteed through scan) 100 160 µs
6.4 Thwsc_fil HWSC filter time ( guaranteed through scan) 40 70 µs
6.5 Thwsc_ref HWSC reference time (guaranteed through scan) 80 130 µs
4.5 Digital input controls
technologies, but must also withstand up to 19V.
4.5.1 Bridge functional modes
L9960 is in Normal Mode when the PWM / DIR control interface is selected. In the below example it is showed the case of LS active freewheeling. Figure 14. Bridge STATE diagram 3). This mode is used to drive valves in Forward or Reverse mode.
Figure 15. Bridge STATE diagram in VVL mode Note: (-) available in the D10 bit position in SPI command frame 5. Note: (-) available in the R11 bit position in SPI answer frame 7c. time “Tvvl” from 0us to 26ms by the register defined below. Table 33. VVL_MODE
0 No VVL mode Reset value
1 VVL mode -
Table 34. VVL_MODE echo Table 35. TVVL[3:0] (µs)
Note: (-) available in the D9/D8/D7/D6 bit position in SPI command frame 5. Note: (-) available in the R10/R9/R8/R7 bit position in SPI answer frame 7c. This mode changes the meaning of PWM/DIR and allows driving directly the half-bridge.
- Program a dedicated SPI r egister (configuration2: IN1_IN2_if) set to '1'.
- PWM/DIR (IN1/IN2) inputs mus t be low to latch and apply the configuration (see Note).
set to '0' to latch and apply the configuration. Table 35. TVVL[3:0] (µs) (continued) Table 36. TVVL_echo[3:0]
Figure 16. Bridge STATE diagram in IN1/IN2 mode
4.5.2 Disable inputs DIS and NDIS
The pin DIS is internally pulled-up and high active. the next PWM rising edge before being released from disable (see Note). The pin NDIS is internally pulled down and high active. reset and SPI communication with the MCU is still possible. edge on driving control pins. Table 37. BRIDGE_EN
0 Bridge disabled Default value
1 Bridge Enabled -
Note: (-) available in the R9 bit position in SPI answer frame 8a. Note: (-) available in the R11 bit position in SPI answer frame 8a. Note: (-) available in the R10 bit position in SPI answer frame 8a.
4.5.3 Control inputs DIR and PWM
the relative command acknlowdgement by internal logic. Table 38. NDIS_status
0 NDIS pin = '0' -
1 NDIS pin = '1' -
Table 39. DIS_status
0 DIS pin = '0' -
1 DIS pin = '1' -
Table 40. Normal mode H-bridge input
111001 F o r w a r d
010110 R e v e r s e
Table 41. IN1/IN2 mode H-bridge input
the relative command acknlowdgement by internal logic. IN1/IN2). The total delay may be related to the switching Current slew rate selected by SPI. Note: (-) available in the D2 bit position in SPI command frame 3.
- It is advised against using this recirculation option in IN1/IN2 mode as L9960 is not safely protected against
Table 41. IN1/IN2 mode H-bridge input (continued) Table 42. VVL mode H-bridge input Table 43. TSW_low_current
0 Tsw activated on i_gate_fb only -
1 Tsw activated on the last event between i_gate_fb or i_out_on R eset value
Note: (-) available in the R3 bit position in SPI answer frame 7a. DIR = 0, the current flows from OUT2 to OUT1. Figure 17. 4 cases of high-side/low-side activation (normal mode) Table 44. TSW_low_current_echo
Figure 18. 4 cases of high-side/low-side activation (IN1/IN2 mode) This should lead to a power dissipation decrease when driving inductive loads. freewheeling is automatically set back to LS drivers. freewheeling) on low-side drivers only. GAPGPS02335Note: Please refer to warning message.
4.5.4 Digital inputs contro l electrical characteristics
Tj = -40 °C to 150 °C, VDD5 = 4.5 V to 5.5 V, Vps = 4 V to 28 V unless otherwise specified. All voltages refer to GND. Currents are positive into and negative out of the specified pin. Table 45. Digital inputs control electrical characteristics
- Extended range of temperature (150, 170°C).
4.6 Driver configuration
the application requirements and also to the type of load.
4.6.1 Slew rate control
trade-off between conducted/radiated EMI and power dissipation during switching.
4.6.2 Current slew rate
The current slew rate can be set in real time by SPI. The corresponding read/write bit is "ISR". No external component is needed to select the current slew rate range. Note: (-) available in the D7 bit position in SPI command frame 3. conditions (ILIM_REG, overcurrent or Tj) as defined in the table below. Table 46. ISR Table 47. Range current slew rate
Note: (-) available in the R8 bit position in SPI answer frame 7a.
4.6.3 Voltage slew rate
The voltage slew rate on HS FETs can be set in real time by SPI. freewheeling are adjustable, the two others are controlled with a preset slew rate. Note: (-) available in the R6 bit position in SPI command frame 3. bit/conditions (ILIM_REG, overcurrent or Tj (and TDSR)) as defined in the table below. The voltage SR setting is reported by bit "VSR_echo". Note: (-) available in the R7 bit position in SPI answer frame 7a. Table 48. ISR_echo Table 49. VSR Table 50. Voltage slew rate Table 51. VSR_echo
by a faster SR when Tj > OTwarn, ILIM_REG = 1, NOC = 0 or NOSR bit is set. Note: (-) available in the D8 bit position in SPI command frame 3. Note: (-) available in the R9 bit position in SPI answer frame 7a. TDSR='0' the current SR mode is kept as selected during OTwarn condition. Note: (-) available in the D10 bit position in SPI command frame 6. Table 52. NOSR
0 NOSR mode NOT allowed Reset value
1 NOSR mode allowed -
Table 53. NOSR_echo
0 Echo NOSR mode NOT allowed Default value
1 Echo NOSR mode allowed -
Table 54. TDSR
0 TDSR mode NOT allowed condition Default value
1 TDSR mode allowed -
Table 55. TDSR_ECHO
corresponds to a freewheeling phase. Figure 19. Ideal waveforms of switching with slew rate control A and B refer to Figure 19). dIout/dt due to the transconductance of the output stage (no closed loop control).
4.6.4 Current limitation
mainly to protect the actuator and also reduce the power dissipation inside the L9960. previously (SPI, DIS, RESET). Note: (-) available in the R3 bit position in SPI answer frame 8a. will be set to "1". Tdiag2 timing starts and overcurrent control is now enabled. diagnosis bits (OCH0,OCH1,OCL0,OCL1) according to the 4 MOS overcurrent thresholds data. The value of the blanking time depends on a Vps threshold Vps_norm. Table 56. ILIM_REG
0 Latched I < Ilim_H and Tof f > Toffmin default value
1 Latched I > Ilim_H and Tdiag2 expired -
Figure 22. Current limitation schemes Note: See also Figure 21: Slew rate switching strategy. application. The default value is set to Range 1. The low threshold "Ilim_L" is based on the high threshold (Ilim_L = Ilim_H – 0.5 (TYP)).
Note: (-) available in the R10,R9 bit positions in SPI command frame 3. Note: (-) available in the R11,R10 bi t position in SPI answer frame 7a. Figure 23. Effect of the temperature diagram Table 57. CL[1:0]
00 Range 0 -
01 Range 1 reset value
10 Range 2 -
11 Range 3 -
Table 58. CL_echo[1:0]
00 Echo Range 0 config -
01 Echo Range 1 config reset value
10 Echo Range 2 config -
11 Echo Range 3 config -
threshold is dynamically adjusted. dot A to dot B like as showed in Figure 24: Thermal current limitation adjustment. hyst, then the Ilim_H consequently would increase staying always on C-B or B-A line. response as showed in the following tables. Note: (-) available in the R6,R5,R4 bit position in SPI command frame 4. Note: (-) available in the R6,R5,R4 bi t position in SPI answer frame 7b. Table 59. OTwarn_thr_var Table 60. OTwarn_thr_var_echo
Note: (-) available in the R9,R8,R7 bit position in SPI command frame 4. Note: (-) available in the R9,R8,R7 bi t position in SPI answer frame 7b. Table 61. OTsd_thr_var Table 62. OTsd_thr_var_echo
Table 63. Electrical characteristics
and with resistive load (6 Ω). and pure resistive load (6 Ω).
247 V / µ s
- Application note will include SR trend with different battery voltage and resistive/inductive load.
Table 63. Electrical characteristics (continued)
4.7 Driver protections
4.7.1 Over-temperature protection
stored on both latched and unlatched bits called NOTSD_REG and NOTSD. indicated in a bit called NOTSD. latches the fault until cleared. Note: (-) available in the R3 bit position in SPI answer frame 8b. Note: (-) available in the R2 bit position in SPI answer frame 8b. thermal warning (cool down) is reached. independently of the status of OTSDcnt counter or NOTSD_REG bit. Table 64. NOTSD
0 Tj>Otsd Disabled -
1 Tj<Otsd Active Default value
Table 65. NOTSD_REG
0 Latched if Tj>Otsd Disabled -
1 Latched if Tj<Otsd Active Default value
Figure 24. Thermal current limitation adjustment when temperature exceeds the OTwarn. Ilim_H is reduced letting the device working on B-D line. limitation will be adjusted according to line from dot B to D. Note: (-) available in the 0 (LSB) bit position in SPI command frame 5. Note: (-) available in the 0 (LSB) bit position in SPI answer frame 7c. information is stored and latched in a bit called OTWARN_REG. Table 66. OTWARN_TSEC_EN
0 OTWARN_TSEC_EN not enabled Default value
1 OTWARN_TSEC_EN enabled -
Table 67. OTWARN_TSEC_EN_echo
0 Echo OTWARN_TSEC_EN not enabled Default value
1 Echo OTWARN_TSEC_EN enabled -
and thus the junction temperature. Note: (-) available in the R4 bit position in SPI answer frame 8b. Note: (-) available in the R5 bit position in SPI answer frame 8a.
4.7.2 Over-temperature monitor ing electrical characteristics
Table 68. OTWARN Table 69. OTWARN_REG
0 Latched if Tj < OTwarn Default value
1 Latched if Tj > OTwarn -
Table 70. Over-temperature monitoring electrical characteristics
4.7.3 Short-circuit to battery: over-current detection in low-side transistors
Figure 25. Example of low-side transistor low impedance short circuit to battery bridge is switched to disable. This information is stored and latched in bits called "OCL_x". DIAG_CLR_EN=1 only), or by DIS level change (falling edge) or by RESET. Table 70. Over-temperature monitoring electrical characteristics (continued)
4.7.4 Short-circuit to ground: o ver-current detection in high-side transistor
DIAG_CLR_EN=1, or by DIS level change (falling edge) or by RESET. Figure 26. Over-current detection
4.7.5 Load in short-circuit
Bits are to be stored when validity bit is set.
4.7.6 Over-current detection electrical characteristics
for temperatures between -40°C and +170°C, the current values are interpolated. Table 71. Over-current detection electrical characteristics
4.8 Diagnostics and re gisters descriptions in case of validity bit
A detailed diagnostic of the H-bridge is available through SPI communication. H-bridge HWSC test result. diagnostic is to provide the information “diagnostic done” OR “diagnostic NOT done”.
4.8.1 Diagnostic Reset strategy
case of SPI read, no additional action on DIS is needed. Table 71. Over-current detection electrical characteristics (continued)
4.8.2 Diagnostic reset bit
register can be cleared by the three possibilities described in the previous section. until a transition from "high" to "low" on DIS pin or RESET condition. Note: (-) available in the R0 bit position in SPI command frame 3. Note: (-) available in the 1st bit position in SPI answer frame 7a. becomes the new status of the diagnostic register (new information must not be lost). Table 72. DIAG_CLR_EN
0 OC and OT diagnostic status bi ts not cleared by SPI reading -
1 Clear of diagnostic status bi ts by SPI reading Reset value
Table 73. DIAG_CLR_EN_echo
0 OC and OT diagnostic statu s bits not cleared by SPI -
1 Clear of diagnostic status bits by SPI reading Default value
Table 74. Status bits description Table 75. Diagnostics bits description
- In case of SPI interrogation for HWSC/LBIST in between test e xecution, the answer could be "0xx".
Table 75. Diagnostics bits description (continued)
4.8.3 Global Failure Bit NGFAIL definition
more present and the latched version of the failure bit is cleared), the bit is de-asserted. toggle of DIS pin is performed. There is no failure considered on Vps undervoltage, despite the bridge goes in OFF-state. Note: (-) available in the R4 bit position in SPI answer frame 8a. Table 76. NGFAIL
4.8.4 Diagnostic of "Over -current" in on-state
Note: (-) available in the R1 0,R9,R7,R6,R4,R3,R1,R0 bit position in SPI answer frame 1. First bit is overcurrent and second bit is load short detection. Note: OCxx[1:0] = 2’b01 is not a possible condition. Figure 27. Example of correct Overcurrent detection Table 77. Diagnostic of "Over-current" in on-state
2 Bits status by MOS
Figure 28. Example of NO Overcurrent detection by Tdiag2 or IN1!=IN2), the timing "Tdiag1" starts. Vps_norm thresholds on Table 63). Both are digital filters and guaranteed through scan. are set to "00", which means "OVER-CURRENT ". "10" which means "NO OVER-CURRENT". "10" which means "NO OVER-CURRENT" (current limitation reached). Toc_hs(ls), then "OCxx1:0" are set to "10" which means "NO OVER-CURRENT". the device is still protected by an automatic shut-off after Timer expiration.
Figure 29. Current diagnostic state diagram for each MOS signal or after SPI reading. Table 78. Error_count[3:0]
0000 Default value
Table 79. TDIAG1 (µs)
Note: (-) available in the R6,R5,R4 bit position in SPI command frame 3. Note: (-) available in the R6,R5,R4 bi t position in SPI answer frame 7a. belonging to the free wheel). Diagnostic register read by SPI (in case bit "DIAG_CLR_EN" = 1). Table 79. TDIAG1 (µs) (continued) Table 80. TDIAG1_echo[2:0]
4.8.5 Diagnostic of "Open Load" in on-state
PWM/DIR and IN1/IN2 mode when the recirculation is performed through LS drivers. Note: (-) available in the D9 bit position in SPI command frame 6. (drain voltage below ground in case of current recirculation). Note: (-) available in the R1,R0 in SPI answer frame 8b. In case OL_ON bit = “0” (Diag function disabled), the OL_ON_STATUS=[00]. to come back to Normal mode (bridge directly switch to Normal operating). Table 81. OL_ON
0 Open Load in on-state disabled Reset value
1 Open Load in on-state enabled -
Table 82. OL_ON_STATUS [1:0]
00 OL disabled - -
01 No diag done Low Default value
10 OL / Diag done High -
11 No OL / Diag done Medium -
Figure 30. Open load timing diagram
4.8.6 On-state diagnostics el ectrical characteristics
Tj = -40 °C to 150 °C, VDD5 = 4.5 V to 5.5 V, Vps = 4 V to 28 V unless otherwise specified. All voltages refer to GND. Currents are positive into and negative out of the specified pin. freewheeling; this may lead to not fully operating Open Load diagnostic in ON state. Table 83. Open Load in ON-state electrical characteristics
4.8.7 Off-state diagnostic
Note: (-) available in the D0 bit position in SPI command frame 9. the same SPI command “OFF STATE diagnosis”. of the bridge or after reset state only in case of DIS activation. only when the source of failure is from OFF state diagnostics itself. Figure 31. Structure and detection criteria Thz is started on DIS rising edge event or reset (POR/SW) event only. Table 84. TRIG
0 OFF-state diagnosis not triggered Reset value
1 Trigger OFF-state diagnosis -
diagnosis input is stable during Tstable_off, the diag is performed and the failure is latched. time is re-triggered on each edge of the diagnosis input. Here below the OpenLoad in Offstate diagram, showing two application cases. Figure 32. Open load off state diagnosis diagram Note: (-) available in the R2/R1/R0 bit position in SPI answer frame 9.
- Normal operation, no failure 2. Steady State Open Load failure
Table 85. DIAG_OFF[2:0]
000 Not used - -
001 Open Load / Diag done 6(Highest) -
010 Short circuit to BAT 5 -
011 Short circuit to GND 4 -
100 No failure / Diag done 3 -
101 No Diag triggered / incorrect state (active state or vps_uv
110 No Diag triggered / Thz not expired 1 -
111 No Diag done / Diag sequence (tdiag_del + tstable) on
4.8.8 Off-state diagnostic electrical characteristics
Tj = -40 °C to 150 °C, VDD5 = 4.5 V to 5.5 V, Vps = 4 V to 28 V unless otherwise specified. All voltages refer to GND. Currents are positive into and negative out of the specified pin.
4.9 SPI
communication between the L9960 and the MCU. provides NCS and SCLK to L9960. As far as MSB/LSB order is concerned, MSB is sent first. Table 86. Off-state diagnostic electrical characteristics
4.9.1 Protocol description
A command sent by the µcontroller during transfer N is answered during transfer N+1. Figure 33. SPI SDO update at 2nd SPI command SDO is clocked on SCLK rising edge. Figure 34. SPI SDO is clocked on SCLK rising edge SDI is sampled on falling edge. SCLK is guaranteed to be at '0' when NCS rises and falls (guaranteed by application). latch whose address was decoded from the SPI shift register command bits. A command is executed after 16 SCLK cycles (or a multiple of 16) and NCS goes high. returned to the µcontroller. The answer of last command is sent during next transfer. Figure 35. In case of no SCLK edge when NCS=0
4.9.2 SPI command and response words format
diagnostic, output state, etc. 1st response after reset is 0000 0000 0000 0000. clocks not multiples of 16) the following response is sent: 0000 0000 0000 0000. Command Chip Select (NCS) LOW without clock is ignored. Table 87. SPI command word format Table 88. SPI response word format
Table 89. Supplier ID code Table 90. Silicon version identifier
4.9.3 Read ASIC traceability number
Figure 36. Wafer XY coordinate Die coordinate and wafer number bits are defined by specification. Table 91. Wafer coordinate Table 92. Traceability code and wafer number
Functional description L9960, L9960T 78/95 DS11115 Rev 10
4.9.4 Read Logic HW version
Logic HW version can be read back after the following command word “Logic HW version request“: Response to command word “Logic HW version request”
4.9.5 Parity bit
The LSB (Least Significant Bit i.e. the last sent bit) of the word sent by the MCU to the L9960 is the parity bit. ODD parity is being used. No parity bit generation is used in response words for the slave device. Address D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 parity_bit 1 1 1 1 00000000010 0 A d d r e s s R 1 1 R 1 0 R 9R 8R 7R 6R 5R 4R 3R 2R 1R 0 1 1 1 1 Code_version[7:0]
4.9.6 SPI communication mode (Pa rallel and Daisy chain mode)
Figure 37. Daisy chain operation example Software constraint: daisy chain is only possibly for ASICs using the same SPI protocol.
4.9.7 Communication check
bridge is put into tri-state. first communication, Tcc for the next communications. In case the timer has expired (time-out), a status bit is registered CC_latch. Note: Available in D9 bit position in SPI answer frame 7e. The communication check can be disabled by SPI via dedicated bit Config_CC. Note: (-) available in D7 bit position in SPI answer frame 2. The status of config register is inverted in a status bit. Note: (-) available in the R10 bit position in SPI answer frame 7e. Table 93. CC_latch
0 Communication Check Fail -
1 Communication Check Pass or Disable Default value
Table 94. Config_CC
0 Disable communication check -
Table 95. Config_CC_state_echo7
4.9.8 Electrical characteristics
Vpor (Max frequency define in parameter fSCLK). Positive current is flowing into pin. Table 96. Electrical characteristics serial data output
Table 97. SPI electrical characteristics
- Application relevant: VHDL design needs at least 4 clock cycles (e.g. System Clock 5MHz) to process assertion of NCS
Figure 38. SPI timings
Table 98. SPI communication command and answer words
- Command frame '0' is not used.
- In command frames 1, 2, 4 and 5 the bitfileds set to '0' must be respected otherwise internal logic will discard the command.
- D[1] BITFIELD IN SPI COMMAND #3 must be kept at 1.
- D[1] bitfield in SPI command #4 must be kept at 0.
mirrored in bitfield R[9]..R[1] in answer frame #7d.
- Frame 10a, 10b and 11 are reserved SPI command frames for ATE . If sent by, the SDO response will be the error frame 0x0000h.
Table 98. SPI communication command and answer words (continued)
Table 99. SPI communication configuration
0 Configuration
Table 99. SPI communication configuration (continued)
5 Package information
specifications, grade definitions and product status are available at: www.st.com.
5.1 PowerSSO-36 (exposed pa d) package mechanical data
Figure 39. PowerSSO-36 (exposed pad) package mechanical drawing
Table 100. PowerSSO-36 (exposed pad) package mechanical data
- Dimensions D and E1 do not inc lude mold flash or protrusions. Allowable mold flash or protrusions is ‘0.25
Table 100. PowerSSO-36 (exposed pad) package mechanical data (continued)
Reference document L9960, L9960T 92/95 DS11115 Rev 10
6 Reference document
7 Revision history
Table 101. Document revision history 22-Jun-2015 1 Initial release. 25-Jun-2015 2 Updated CDM results in Section Table 4.. – Table 71: Over-current detection electrical characteristics. concerning HBM for OUTx and VPS). (added note for SPI command frame #3, #4 and #6). updated Word ID “#6” from 0 to X; updated note “5”. answer to #7d# (R9-R1 from 0 to X; updated note “1”. and 22 for Tdiag2 and ILIM_REG references. – Section 4.8.7: Off-state diagnostic. Added Section 6: Reference document.
– Table 96: Electrical characteristics serial data output. – Section 2: Application description. – Section 2.2: Bill of materials. – Table 98: SPI communication command and answer words. Table 101. Document revision history (continued)