L9951_10 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 36
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specifications
- 2.1 Absolute maximum ratings
- 2.2 ESD protection
- 2.3 Thermal data
- 2.4 Temperature warning and thermal shutdown
- 2.5 Electrical characteristics
- 2.6 SPI - electrical characteristics
- 3 Application information
- 3.1 Dual power supply: VS and VCC
- 3.2 Standby - mode
- 3.3 Inductive loads
- 3.4 Diagnostic functions
- 3.5 Over-voltage and under-voltage detection
- 3.6 Temperature warning and thermal shutdown
- 3.7 Open-load detection
- 3.8 Over load detection
- 3.9 Current monitor
- 3.10 PWM input
- 3.11 Cross-current protection
- 3.12 Programmable softstart function to drive loads with higher inrush current
- 4 Functional description of the SPI
- 4.1 Serial Peripheral Interface (SPI)
- 4.2 Chip Select Not (CSN)
- 4.3 Serial Data In (DI)
- 4.4 Serial Data Out (DO)
- 4.5 Serial clock (CLK)
- 4.6 Input data register
- 4.7 Status register
Features
■ One half bridge for 7.4 A load (Ron = 150 mΩ) ■ Two half bridges for 5 A load (Ron = 200 mΩ) ■ Two highside drivers for 1.25 A load (Ron =8 0 0 mΩ) ■ Programmable softstart function to drive loads with higher inrush currents (i.e.current > 7.4A, >5A, >1.25A) ■ Very low current consumption in standby mode S < 3µA, typ. Tj ≤ 85°C) ■ All outputs short circuit protected ■ Current monitor output for all highside drivers ■ All outputs over temperature protected ■ Open-load diagnostic for all outputs ■ Overload diagnostic for all outputs ■ Programmable PWM control of all outputs ■ Charge pump output for reverse polarity protection
Applications
■ Rear door actuator driver with bridges for door lock and safe lock and two 5W or 10W - light bulbs.
Description
The L9951 and L9951XP are microcontroller driven, multifunctional rear door actuator drivers for automotive applications. Up to two DC motors and two grounded resistive loads can be driven with three half bridges and two hide side drivers. The integrated standard serial peripheral interface (SPI) controls all operation modes (forward, reverse, brake and high impedance). All diagnostic information is available via the SPI. Type Outputs (1) 1. See block diagram. Ron (2) 2. Typical values. IOUT VS L9951 L9951XP OUT1 OUT2 OUT3 OUT4 OUT5 150 mΩ 200 mΩ 200 mΩ 800 mΩ 800 mΩ 7.4 A 1.25 A 1.25 A 28 V PowerSO-36 PowerSSO-36 Table 1. Device summary
1 Block diagram and pin description
Figure 1. Block diagram
Table 2. Pin definitions and functions
36 GND
GND must be externally connected. Power supply voltage (external reverse protection required). VS must be externally connected. output). This output is over-current and open-load protected. OUT1 must be externally connected. bit (LSB, bit 0) is transferred first. Current monitor output/PWM input. to provide a PWM input for all outputs.
10 CSN
Chip select not input / Testmode . CSN pin the L9951 will be switched into a test mode.
13 CLK
Figure 2. Configurati on diagram (top view) Half-bridge output 2 (see OUT1 - pin 3, 4). OUT2 must be externally connected. Half-bridge output 3 (see OUT1 - pin 3, 4). OUT3 must be externally connected. MOS used for reverse polarity protection (see Figure 1). High side driver output 4, 5 . drain-diode). The output is over-current and open-load protected. Table 2. Pin definitions and functions (continued)
2 Electrical specifications
2.1 Absolute maximum ratings
2.2 ESD protection
2.3 Thermal data
Table 3. Absolute maximum ratings Table 4. ESD protection
- HBM according to CDF-AEC-Q100-002.
- HBM with all unzapped pins grounded.
Table 5. Thermal data
2.4 Temperature warnin g and thermal shutdown
2.5 Electrical characteristics
VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified. Table 6. Temperature warning and thermal shutdown Table 7. Supply
Table 8. Overvoltage and undervoltage detection Table 9. Current monitor output Table 7. Supply (continued)
Table 10. Charge pump output Table 11. OUT 1 - OUT 5
Table 11. OUT 1 - OUT 5 (continued)
2.6 SPI - electrical characteristics
Note: Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 12. Delay time from standby to active mode Table 13. Inputs: CSN, CLK, PWM1/2 and DI Table 14. DI timing (1)
Tj= -40°C/+25°C: SPI communication @2MHZ. Tj= +125°C: SPI communication @1.25MHZ.
- See Figure 3 and Figure 4
Table 14. DI timing (1) (continued) Table 15. DO
- Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 16. DO timing (1)
- See Figure 5 and Figure 6.
Figure 3. SPI - transfer timing diagram Figure 4. SPI - input timing Table 17. EN, CSN timing (1) sending first SPI frame, i.e.
0.8 VCC
0.2 VCC
Figure 5. SPI - DO valid data delay time and valid time Figure 6. SPI - DO en able and disable time
0.5 VCC
L9951 / L9951XP Application information Doc ID 14173 Rev 8 19/36
3 Application information
3.1 Dual power supply: V S and VCC
The power supply voltage VS supplies the half bridges and the high side drivers. An internal charge-pump is used to drive the high side switches. The logic supply voltage VCC (stabilized 5V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-on (VCC increases from under voltage to VPOR OFF = 4.0V, typical) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON =3.6V, typical), the outputs are switched to tristate (high impedance) and the status registers are cleared.
3.2 Standby - mode
The standby mode of the L9951 is activated by switching the EN input do GND. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at V S (VCC) is less than 3 µA (1µA) for CSN = high (DO in tristate). If EN is switched to 5V the device will enter the active mode. In the active mode the charge- pump and the supervisor functions are activated.
3.3 Inductive loads
Each half bridge is built by an internally connected high side and a low side power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The high side drivers OUT4 to OUT5 are intended to drive resistive loads. Hence only a limited energy (E<0.5mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L > 50µH) an external free-wheeling diode connected to GND and the corresponding output is needed.
3.4 Diagnostic functions
All diagnostic functions (over/open-load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32µs (open-load: 1ms, respectively) before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Open- load and temperature warning function are intended for information purpose and will not change the state of the output drivers. On contrary, the over load and thermal shutdown condition will disable the corresponding driver (over load) or all drivers (thermal shutdown), respectively. Without setting the over-current recovery bit in the Input Data Register to logic high, the microcontroller has to clear the over-current status bit to reactivate the corresponding driver. Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switch-on the outputs again after a short recovery time. The duty cycle in over-current condition can be programmed by the SPI interface (12% or 25%). With this feature the device can drive loads with start-up currents higher than the over- current limits (e.g. inrush current of lamps, cold resistance of motors and heaters).
Application information L9951 / L9951XP 20/36 Doc ID 14173 Rev 8
3.5 Over-voltage and un der-voltage detection
If the power supply voltage VS rises above the over-voltage threshold VSOV OFF (typical 21V), the outputs OUT1 to OUT5 are switched to high impedance state to protect the load and the internal charge-pump is turned-off. When the voltage V S drops below the undervoltage threshold VSUV OFF (UV-switch-OFF voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage V S recovers to normal operating voltage the output stages return to the programmed state (input register 0: bit 12=0). If the undervoltage / overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers.
3.6 Temperature warnin g and thermal shutdown
If junction temperature rises above Tj TW a temperature warning flag is set and is detectable via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device. In order to reactivate the output stages the junction temperature must decrease below T jSD - TjSD HYS and the thermal shutdown bit has to be cleared by the microcontroller.
3.7 Open-load detection
The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for at least 1 ms (t dOL) the corresponding open-load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads.
3.8 Over load detection
In case of an over-current condition a flag is set in the status register in the same way as open-load detection. If the over-current signal is valid for at least t ISC=32µs, the over-current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.
3.9 Current monitor
The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected high side driver. The bits 9, 10 and 11 of the input data register 0 control which of the outputs OUT1 to OUT5 will be multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example this can be used to detect the motor state (starting, free-running, stalled). Moreover, it is possible to regulate the power of the defroster more precise by measuring the monitor current.
3.10 PWM input
3.11 Cross-current protection
before the opposite driver will start to conduct.
3.12 Programmable softstart functi on to drive loads with higher
the bulb) until the load reaches operating condition. Figure 9. Example of programmable so ftstart function for inductive loads
Functional description of the SPI L9951 / L9951XP 22/36 Doc ID 14173 Rev 8
4 Functional description of the SPI
4.1 Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins and one input pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device without the need of a full SPI- communication cycle. Note: In contrast to the SPI-standa rd the least significant bit (LSB) will be transferred first (see Figure 3).
4.2 Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN will be called a communication frame. If the CSN-input pin is driven above 7.5V, the L9951 will go into a test mode. In the test mode the DO will go from tristate to active mode.
4.3 Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 16 bit shift register. At the rising edge of the CSN signal the contents of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame. Note: Due to this safety functionality a daisy chai ning of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.
L9951 / L9951XP Functional description of the SPI Doc ID 14173 Rev 8 23/36
4.4 Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
4.5 Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal.
4.6 Input data register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of the two input registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected input data register only if a frame of exact 16 data bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO during the current communication frame. Bit 1-8 control the behavior of the corresponding driver. The bits 9,10 and 11 are used to control the current monitor multiplexer. Bit 15 is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the current communication frame (rising edge of CSN).
4.7 Status register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a fault bit and is a logical-NOR combination of bits 1-14 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPI- communication cycle (see Figure 8.). If one of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers.
4.8 Test mode
The test mode can be entered by rising the CSN input to a voltage higher than 7.5V. In the test mode the inputs CLK, DI, PWM and the internal 2MHz CLK can be multiplexed to data output DO for testing purpose. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower current. The internal logic prevents that the Hi-Side and Low-Side driver of the same half-bridge can be switched-on at the same time. In the test mode this combination is used to multiplex the desired signals to the CM output according to table 18 and 19.
Table 18. Test mode Table 19. SPI - Input data and status register 0
15 Reset bit
14 Disable open-
the outputs are deactivated. event to enable the outputs.
10 Not ready bit
8 OUT5 - HS
output driver is switched on.
7 OUT4 - HS
6 OUT3 - HS
5 OUT3 - LS
4 OUT2 - HS
3 OUT2 - LS
2 OUT1 - HS
1 OUT1 - LS
load status will be ignored. Table 19. SPI - Input data and status register 0 (continued)
000 O U T 1
001 O U T 2
010 O U T 3
011 O U T 4
100 O U T 5
Table 20. SPI - Input data and status register 1
15 Not used Always 1
14 Not used V
the outputs are deactivated.
13 Not used V
the outputs are deactivated.
12 Not used Thermal
11 Not used Temperature
10 OUT5 OC
9 OUT4 OC
8 OUT3 OC
7 OUT2 OC
6 OUT1 OC
5 OUT5 PWM
4 OUT4 PWM
3 OUT3 PWM
2 OUT2 PWM
1 OUT1 PWM
Table 20. SPI - Input data and status register 1 (continued)
5 Packages thermal data
Figure 10. Packages thermal data
6 Package and packing information
6.1 ECOPACK ® packages
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
6.2 PowerSO-36™ package information
Figure 11. PowerSO-36™ package dimensions Table 21. PowerSO-36™ mechanical data
Table 21. PowerSO-36™ mech anical data (continued)
6.3 PowerSSO-36™ package information
Figure 12. PowerSSO-36™ package dimensions Table 22. PowerSSO-36™ mechanical data
6.4 PowerSO-36™ packing information
Figure 13. PowerSO-36 TM tube shipment (no suffix) Table 22. PowerSSO-36™ mechanical data (continued)
Figure 14. PowerSO-36 TM tape and reel shipment (suffix “TR”)
6.5 PowerSSO-36™ packing information
Figure 15. PowerSSO-36 TM tube shipment (no suffix) Figure 16. PowerSSO-36 TM tape and reel shipment (suffix “TR”)
7 Revision history
Table 23. Document revision history Jul-2005 3 Updated Figure 1.: Block diagram . Updated Figure 10.: Packages thermal data. Feb-2006 5 Updated Table 4.: ESD protection. Document restructured and reformatted.