L9950 STMICROELECTRONICS | Alldatasheet
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Technical content
2 APPLICATIONS
driver for mirror defroster and four 5W-light bulbs. All diagnostic informations are available via SPI. Figure 2. Block Diagram Figure 1. Package Table 1. Order Codes
3.1 Dual Power Supply: VS and VCC
The power supply voltage VS supplies the half bridges and the highside drivers. An internal charge-pump is used to drive the highside switches. The logic supply voltage VCC (stabilized 5 V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-on (VCC increases from und- ervoltage to VPOR OFF = 4.2 V) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON = 3.4 V), the outputs are switched to tristate (high impedance) and the status registers are cleared.
3.2 Standby-Mode
The standby mode of the L9950 is activated by clearing the bit 23 of the Input Data Register 0. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC ) is less than 6 µA (50µA) for CSN = high (DO in tristate). By switching the VCC voltage a very low quiescent current can be achieved. If bit 23 is set, the device will be switched to active mode.
3.3 Inductive Loads
Each half bridge is built by an internally connected highside and a lowside power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT6 without external free-wheeling diodes. The highside drivers OUT7 to OUT11 are intended to drive resistive loads. Hence only a limited energy (E<1mJ) can be dissipated by the internal ESD-diodes in free- wheeling condition. For inductive loads (L>100µH) an external free-wheeling diode connected to GND and the corresponding output is needed.
3.4 Diagnostic Functions
All diagnostic functions (over/open load, power supply over-/undervoltage, temperature warning and ther- mal shutdown) are internally filtered and the condition has to be valid for at least 32 µs (open load: 1ms, respectively) before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Open load and temperature warning function are intended for information purpose and will not change the state of the output drivers. On contrary, the overload and ther- mal shutdown condition will disable the corresponding driver (overload) or all drivers (thermal shutdown), respectively. Without setting the over-current recovery bits in the Input Data Register, the microcontroller has to clear the over-current status bits to reactivate the corresponding drivers.
3.5 Overvoltage and Undervoltage Detection
If the power supply voltage V S rises above the overvoltage threshold VSOV OFF (typical 21 V), the outputs OUT1 to OUT11 are switched to high impedance state to protect the load. When the voltage VS drops below the undervoltage threshold VSUV OFF (UV-switch-OFF voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (in- creased power dissipation). If the supply voltage V S recovers to normal operating voltage the outputs stag- es return to the programmed state (input register 0: bit 20=0). If the undervoltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deacti- vated. The microcontroller needs to clear the status bits to reactivate the drivers. It is recommended to set bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery volt- age.
3.6 Temperature Warning and Thermal Shutdown
If junction temperature rises above T j TW a temperature warning flag is set and is detectable via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device. In order to reacti- vate the output stages the junction temperature must decrease below T j SD - Tj SD HYS and the thermal shutdown bit has to be cleared by the microcontroller.
3.7 Open Load Detection
The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL ) the corresponding open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.
3.8 Over Load Detection
In case of an over-current condition a flag is set in the status register in the same way as open load de- tection. If the over-current signal is valid for at least t ISC = 32 µs, the over-current flag is set and the cor- responding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.
3.9 Current monitor
The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. The bits 18 and 19 of the Input Data Register 0 control which of the outputs OUT1, OUT4, OUT5, OUT6 and OUT11 will be multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example this can be used to detect the motor state (starting, free-running, stalled). Moreover, it is possible to regulate the power of the de- froster more precise by measuring the load current. The current monitor output is bidirectional (c.f. PWM inputs).
3.10 PWM inputs
Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit is set, the output is controlled by the logically AND-combination of the PWM signal and the output control bit in Input Data Register. The outputs OUT1-OUT8 and OUT11 are controlled by the PWM1 input and the outputs OUT9/10 are controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be used to dim two lamps independently by external PWM signals.
3.11 Cross-current protection
The six half-brides of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time. After the cross-current protection time is expired the slew-rate limited switch-off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behaviour it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver will start to conduct.
3.12 Programmable Softstart Function to drive loads with higher inrush currrent
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switch-on the outputs again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to be about 12% or 25%. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first 50ms. After clearing the recovery bit the output will be automatically disabled if the overload condition still exits
Figure 4. Pin Connection
31 OUT8
Table 2. Pin Description
2.35 OUT11 Highside-driver-output 11:
diode). The output is over-current and open load protected. from GND to output). This output is over-current and open load protected. For this input a ceramic capacitor as close as possible to GND is recommended. The input requires CMOS logic levels and receives serial data from the microcontroller. signal to provide a second PWM input for the outputs OUT9 and OUT10.
10 CSN Chip Select Not input / Testmode :
11 DO Serial data output:
12 VCC Logic supply voltage:
For this input a ceramic capacitor as close as possible to GND is recommended.
13 CLK Serial clock input:
This input controls the internal shift register of the SPI and requires CMOS logic levels.
26 CP Charge Pump Output:
27 PWM1 PWM1 input:
diode). The output is over-current and open load protected.
Table 3. Absolute Maximum Ratings Table 4. Esd Protection
- HBM with all unzapped pins grounded
Table 5. Thermal Data Table 6. Temperature warning and thermal shutdown
Figure 5. Thermal Data Of Package Table 7. ELECTRICAL CHARACTERISTICS
Table 7. ELECTRICAL CHARACTERISTICS (continued)
4 FUNCTIONAL DESCRIPTION OF THE SPI
4.1 Serial Peripheral Interface (SPI)
crocontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. changed from the high to low transition of CLK. without the need of a full SPI-communication cycle. Note: In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see FIGURE 6).
4.2 Chip Select Not (CSN)
DO will go from tri-state to active mode.
4.3 Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the CSN signal the contents of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong com- munication frame. Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.
4.4 Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
4.5 Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sam- pled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal.
4.6 Input Data Register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of the two Input Registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected Input Data Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO during the current communication frame. Bit 1-17 controls the behaviour of the corresponding driver. If bit 23 is zero, the device will go into the standby-mode. The bits 18 and 19 are used to control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the current communication frame (rising edge of CSN).
4.7 Status Register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPI-communication cycle (see FIGURE 11). If one of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers.
4.8 Test Mode
The Test Mode can be entered by rising the CSN input to a voltage higher than 7.0V. In the test mode the inputs CLK, DI, PWM1/2 and the internal 2MHz CLK can be multiplexed to data output DO for testing pur- pose. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower current. For EWS testing a special test pad is available to measure the internal bandgap voltage, the TW and TSD thresholds. The internal logic prevents that the Hi-Side and Lo-Side driver of the same half-bridge can be switched- on at the same time. In the testmode this combination is used to multiplex the desired signals according to following table 8:
Table 9. SPI - Input Data and Status Register
23 Enable Bit If Enable Bit is set the device
low or high is not a valid frame.
22 Reset Bit If Reset Bit is set both status
status register 0 is not set).
21 OC Recovery Duty
20 Overvoltage/
event to enable the outputs.
19 Depending on combination of
to avoid a thermal shutdown.
18 Current Monitor
events (e.g. measuring filter times).
Table 9. SPI - Input Data and Status Register (continued)
17 OUT11 – HS on/off If a bit is set the selected
programmable duty cycle (Bit 21). reactivate the output driver.
16 OUT10 – HS on/off OUT10 – HS over-
15 OUT9 – HS on/off OUT9 – HS over-
14 OUT8 – HS on/off OUT8 – HS over-
13 OUT7 – HS on/off OUT7 – HS over-
12 OUT6 – HS on/off OUT6 – HS over-
11 OUT6 – LS on/off OUT6 – LS over-
10 OUT5 – HS on/off OUT5 – HS over-
9 OUT5 – LS on/off OUT5 – LS over-
8 OUT4 – HS on/off OUT4 – HS over-
7 OUT4 – LS on/off OUT4 – LS over-
6 OUT3 – HS on/off OUT3 – HS over-
5 OUT3 – LS on/off OUT3 – LS over-
4 OUT2 – HS on/off OUT2 – HS over-
3 OUT2 – LS on/off OUT2 – LS over-
2 OUT1 – HS on/off OUT1 – HS over-
1 OUT1 – LS on/off OUT1 – LS over-
bits 1 to 22 in both status registers.
23 Enable Bit If Enable Bit is set the device will be
22 OUT11 OC
the outputs are deactivated.
21 OUT10 OC
20 OUT9 OC
19 OUT8 OC
18 OUT7 OC
17 OUT6 OC
After 50ms the bit can be cleared. each activated output stage. activation of the outputs (e.g. electrical state of the loads.
16 OUT5 OC
15 OUT4 OC
14 OUT3 OC
13 OUT2 OC
12 OUT1 OC
11 OUT11 PWM1
10 OUT10 PWM2
Table 10. SPI - ELECTRICAL CHARACTERISTICS referred to GND and currents are assumed positive, when the current flows into the pin). Note: 1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
- DI timing parameters tested in production by a passed/failed test:
Table 10. SPI - ELECTRICAL CHARACTERISTICS (continued)
- Value of input capacity is not measured in production test. Parameter guaranteed by design
Figure 6. SPI - TRANSFER TIMING DIAGRAM Figure 7. SPI - INPUT TIMING
0.8 VCC
0.2 VCC
Figure 8. SPI - DO VALID DATA DELAY TIME AND VALID TIME Figure 9. SPI - DO ENABLE AND DISABLE TIME
0.8 VC C
0.2 VC C
0.5 VCC
Figure 12. PowerSO36 Mechanical Data & Package Dimensions Note: “D and E1” do not include mold flash or protusions.
- Critical dimensions are "a3", "E" and "G".
Table 11. Revision History June 2004 2 Changed Maturity from Product Preview to Final. Changed values in the Table 4 ESD Protection.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States L9950