L9912 STM | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Compatibility to 24 V system and the LIN/ BSS function
- 2 Application schematics
- 3 Block diagram
- 4 Pin description
- 5 Electrical specifications
- 5.1 Absolute maximum ratings
- 5.1.1 EEPROMs parameters
- 5.2 Thermal data
- 5.3 Electrical characteristics
- 5.3.1 Pin "A+/B+"
- 5.3.2 Pin "SENSE"
- 5.3.3 Pin “IGNIT”
- 5.3.4 Pin “PROT_SEL”
- 5.3.5 Pin “LIN/BSS”
- 5.3.6 Pin "DFM"
- 5.3.7 Pin "PH"
- 5.3.8 Pin "AUX_IN"
- 5.3.9 Pin "GATE"
- 5.3.10 Pin "DRAIN" and "SOURCE"
- 5.3.11 Pin "F"
- 5.3.12 Pin "CSA_IN"
- 5.3.13 Pin "L"
- 5.3.14 Pin "GHS" and "GLS"
- 5.3.15 Pin "LHC"
- 5.3.16 Pin "RC"
- 5.3.17 VREF_ADC
- 5.3.18 Pin "PH_OUT"
- 5.3.19 Charge pump output
- 5.3.21 Reset output (nRST_SP)
Datasheet sections
- 13.4.8 WATCHDOG / THERMAL SHUTDOWN RESET COUNT register [0x14]
- 13.4.9 DEVICE ID register [0x1F]
- 13.4.10 SYSTEM / UNLOCK register [0x01]
- 13.4.11 SYSTEM OPERATION register [0x02]
- 13.4.12 External POWER MOS register [0x03]
- 13.4.13 WAKE-UP sources and DFM GEN setup re gister [0x04]
- 13.4.14 DFM PWM DUTY CYCLE register [0x05]
- 13.4.15 WATCHDOG CONFIG register [0x06]
- 13.4.16 CP-SPREAD-SPECTRUM & LIN SETTING register [0x08]
- 13.4.17 DRV SETTINGS register [0x09]
- 13.4.18 TEST MODE STATUS register [0x0B]
- 13.4.19 WATCHDOG REFRESH register [0x0F]
- 13.5 SPI sequence example
- 14 Package information
- 15 Order codes
- 16 Revision history
Features
AEC-Q100 qualified System in package smart power alternator regulator and 8-bit microcontroller (non- monolithic approach) Protected high/low side field pre-driver for external MOS Field short circuit protection Regulated voltage driven by ECU (programmable protocol driven) Regulated voltage thermally compensated (without protocol) Lamp driver (wake up and warning detection) Self start function Load response control (LRC) Field monitor (FM) output Thermal shutdown Package TQFP44EP (10 x 10 mm)
Description
The L9912 is a controlled multifunctional alternator regulator intended to be used in cars, commercial and agricultural vehicles. It supports 12 V system. The control can be achieved through different communication protocols: RCV, PCM, C_term. It is a System-In-Package solution with smart power alternator regulator IC coupled with a 8-bit microcontroller (non-monolithic approach). It includes the control section, fault diagnostic circuit which drives a warning lamp, and the protection against short circuits. This device regulates in closed loop the output of an automotive generator by controlling the field winding current by means of a Pulse-Width Modulation (PWM) of an external high side or low side driver at fixed frequency. TQFP44EP '!0'03
1 Compatibility to 24 V system and the LIN/BSS function
device version selected: L9912, L9912L, L9924, and L9924L. Table 1. Summary of the information related to 24 V and LIN/BSS present in this
2 Application schematics
Figure 1. Low-side configuration 12 V Figure 2. High-side configuration 12 V
3 Block diagram
Figure 3. Block diagram
4 Pin description
Figure 4. Pin connection diagram Table 2. Pin function
1 LIN_TX LIN transmitter (µC output)
2 LIN_RX LIN receiver (µC input)
3 PD7/TLI/GPIO1 General purpose Inpu t/output (PD7) / Top level interrupt
5 PA1/GPIO2 General purpose Input/output (PA1)
6 VSS / VSSIO_1 Digital ground / I/O ground
9 VDD Digital power supply
10 VDDIO I/O power supply
11 VDDA Analog power supply (connect to 100nF//1uF for decoupling)
12 VSSA Analog ground
14 SENSE Battery sensing with dedicated wire
15 A+ /B+ Battery sense / Device power supply
16 IGNIT Ignition terminal
17 DFM Field Monitor (PWM signal going to ECU)
18 LIN/BSS LIN / BSS (coming from ECU)
19 AUX_IN Auxiliary input
20 PH Phase sense input
21 PH_OUT Filtered Phase signal
22 L Key sensing and Warning Lamp terminal output
23 GND Regulator ground
24 GLS Gate driver of ext Low Side MOS used for Lamp
25 LHC Key sensing and Warning Lamp terminal output in case of ext MOS
26 GHS Gate driver of ext High Side MOS used for Relay
27 F Field activity monitor (for High side and low side configuration)
28 SOURCE External MOS Source
29 DRAIN External MOS Drain
30 GATE External MOS Gate
31 RC C-Terminal / PCM (PWM signal input coming from ECU)
32 CP1- Charge pump pin for capacitor 1, negative side
33 CP1+ Charge pump pin for capacitor 1, positive side
34 CP2- Charge pump pin for capacitor 2, negative side
35 CP2+ Charge pump pin for capacitor 2, positive side
36 CP Charge pump output
37 PROT_SEL Protocol selection
38 VDD_CAP 5V capacitor(5V regulator output)
40 LIN_RX_SP LIN receiver (smart power output)
41 LIN_TX_SP LIN transmitter (smart power input)
42 PD1/SWIM/GPIO3 Single Wire Interface Module (for µC programming)
Table 2. Pin function (continued)
As shown in the picture, the following pin groups must be connected through external wiring.
43 PD2/EXC_IN Excitation input: connect to PD3/PD4/EXC_OUT
44 PD3/PD4/EXC_OUT Exci tation output: connect to PD2/EXC_IN
Table 3. Group of pins externally connected
5 Electrical specifications
5.1 Absolute maximum ratings
Tj = -40 to 155 °C, unless otherwise specified. Table 4. Absolute maximum ratings Table 5. Maximum ratings
6 VSS / VSSIO_1 - - - V
12 VSSA - - - -
14 SENSE - -20 +48 V
15 A+/B+ Reverse battery voltage @
16 IGNIT - -20 +48 V
18 LIN/BSS - -20 +40 V
19 AUX_IN - -20 +48 V
20 PH - -20 +48 V
23 GND - - - -
27 F - -2 +48 V
28 SOURCE - -2 +48 V
30 GATE - V(SOURCE)-
42 PD1/SWIM/GPIO
44 PD3/PD4/EXC_O
Table 5. Maximum ratings (continued)
5.1.1 EEPROMs parameters
5.2 Thermal data
5.3 Electrical characteristics
5.3.1 Pin "A+/B+"
Table 6. Flash program memory
4 Retention T amb = 55 °C 20 Years
Table 7. Data memory
4 Retention T amb = 55 °C 2 Years
Table 8. Thermal data
Figure 5. Internal resistor ladder on pin A+ initialized by a Power-On Reset (PORn). Table 9. Pin "A+/B+" electrical characteristics
appropriate actions (lamp on, drivers off, etc.). pass filter, is forwarded to µC pin AIN5. Figure 6. VB overvoltage protection
5.3.2 Pin "SENSE"
depending on the device operating mode (12 V or 24 V [13.4.11]). Figure 7. Internal resistor ladder on pin SENSE
A similar block is used to bring A+ pin voltage to AIN5 microcontroller analog input.
5.3.3 Pin “IGNIT”
not used this pin must be tied to GND.
5.3.4 Pin “PROT_SEL”
Table 10. Electrical characteristics pin "SENSE" Table 11. Electrical characteristics pin “IGNIT”
3 IGNIT pull-dw Pull-down current 28 V<(IGNIT) ≤ VIGNITdet2 - 20 250 µA
Table 12. Electrical characteristics pin “PROT_SEL”
4 RPSEL Pull-up/pull-down resistor
5.3.5 Pin “LIN/BSS”
PROT_SEL pin, RC pin and control internal pull-up resistor by bit 4 of SPI register 0x08. should be left open and the “wake-up by LIN” function must be disabled by SPI. Speed communication up to 20 kbit/s (100 kbit/s for Flash). LIN 2.1 compliant (SAEJ2602 compatible) transceiver. Functional range from +40 V to -18 V DC at LIN/BSS pin. GND disconnection fail safe at module level. Off mode: does not disturb network. GND shift operation at system level. Micro controller interface with CMOS compatible I/O pins. bus interface offers an ultra low current consumption.
5 IPSEL PU Pull-up current
6 IPSEL PD Pull-down current
Table 12. Electrical characteristics pin “PROT_SEL” (continued) Table 13. Electrical characteristics pin PROT_SEL and RC pin protocol
Pins involved in both LIN and BSS protocols management are: LIN_RX_SP: smart power output, which stands for RxD LIN_TX_SP: smart power input, which stands for TxD LIN/BSS: transceiver bus from ECU LIN_RX: µC input to be connected to LIN_RX_SP LIN_TX: µC output to be connected to LIN_TX_SP LIN Error Handling The device provides the following 3 error handling features which aren't described in the LIN Spec. V2.1, but implemented in several stand-alone LIN transceivers/microcontrollers to switch the application back to normal operation mode. Dominant TxD time out In case TxD is in dominant state (i.e. low level) for more than tdom(TXD)=12ms (typical value) the transmitter will be disabled. The status won't be latched and can be read through bit 12 (read only) of 0x12 SPI register. The transmitter remains disabled until TxD changes to recessive state (i.e. high level) for more than 12µs. This error detection can be enabled by setting bit 1 of 0x08 SPI register. Permanent recessive LIN/BSS bus In case TxD changes to dominant (i.e. low level) state and RxD signal does not follow within t rec(LIN) = 40 µs (typical value) the transmitter will be disabled. The status bit won't be latched and can be read through bit 11 (read only) of 0x12 SPI register. The transmitter remains disabled until TxD changes to recessive state (i.e. high level) for more than 12 µs. Permanent dominant LIN/BSS bus In case the bus state is dominant (i.e. LIN/BSS at low level) for more than tdom(LIN) = 12 ms (typical value) a permanent dominant status will be detected. The status won't be latched and can be read through bit 13 (read only) of 0x12 SPI register. The transmitter will not be switched off. This error detection can be enabled by setting bit 1 of 0x08 SPI register. Note: a normal wake up caused by a message on the bus will start the voltage regulator and the microcontroller to switch the application back to normal operation mode. Wake-up by LIN/BSS bus In power standby mode the device can receive a wake-up from LIN/BSS bus. Two different conditions can be differentiated: Normal wake-up A normal wake-up occurs when the device was previously asked to enter Power Stand- by mode while LIN/BSS bus was in recessive (i.e. high level) state. A level at LIN bus crossing VThwkup longer than tlinbus = 5 µs (typical value) will switch the device into Active mode and will turn the LIN/BSS receiver on as well to process coming message frames. An event is generated at the RxD pin. Wake-up from LIN/BSS bus in short-to-GND condition This wake-up condition isn't supported by the device and must be carefully avoided into application. In case the device was asked to enter Power Stand-by mode while LIN/BSS bus was recognized in dominant (i.e. low level) state, the command must be preceded by the LIN/BSS wake-up disable command (bit 12 in 0x04 SPI register).
LIN/BSS wake-up can be restored. Compatible to LIN 2.1 for Baud rates up to 20 kBit/s (Up to 100 kbit/s for Flash Mode). Table 14. Electrical characteristics pin "LIN/BSS"
5 ITXDPD
10 V Thhys
11 V Thcnt
12 V Thwkup
15 Ibus_PAS_do
16 Ibus_PAS_No
17 I bus_PAS_rec
18 I bus_NO_GND
0 V < V(LIN/BSS) < 33 V 0-2 m A
19 I bus
20 V LINdom
21 V LINrec
22 R LINup
23 SRf LIN/BSS bus slew rate
123 V / µ s
Table 14. Electrical characteristics pin "LIN/BSS" (continued)
28 D1 Duty cycle 1
29 D2 Duty cycle 2
30 D3 Duty cycle 3
31 D4 Duty cycle 4
Figure 8. LIN/BSS transmit, receive timing
5.3.6 Pin "DFM"
Table 15. DFM output configuration Table 16. Electrical characteristics pin "DFM"
5.3.7 Pin "PH"
to the µC to compute the rotor speed. (bit 12 of SPI register 0x13 is set [13.4.7]). The device exits the stand-by mode when an activity is detected on PH pin (i.e. V(PH)>VPHTh) independently on the status of other wake-up sources.
5.3.8 Pin "AUX_IN"
used, AUX_IN pin must be tied to ground. It's forbidden to replace AUX_IN pin with PH pin. Table 17. Electrical characteristics pin "PH" Table 18. Electrical characteristics pin "AUX_IN"
5.3.9 Pin "GATE"
current to turn-on and turn-off the external power MOS. The gate-source-voltage of the external power MOS is limited by the driver circuit. switches the external power MOS off, activating a fast gate discharging current. Table 19. Electrical characteristics pin "GATE"
10 R GSHx
5.3.10 Pin "DRAIN" and "SOURCE"
short circuit protection to the external Power MOS. the µC needs to read (and then clear) the diagnostic bit. Figure 9. External MOS short circuit protection corresponding gate driver is in source condition. Table 20. Electrical characteristics pin "DRAIN" and "SOURCE"
5.3.11 Pin "F"
field is compared to a threshold VFdet and forwarded to a µC timer port. The F signal behavior is related to the system configuration (low side or high side).
5.3.12 Pin "CSA_IN"
The rotor current can be measured by means of an external sense resistor. The current sense amplifier output is connected to the µC AIN0 analog input. CSA_IN A+/B+ EPONA pins as short as possible. Figure 10. High-side configuration. Table 20. Electrical characteristics pin "DRAIN" and "SOURCE" (continued) Table 21. Electrical characteristics pin "F"
Table 22. Electrical characteristics pin "CSA_IN"
0.4 VDD -V
6 R CSA_IN series resistance - - 36 - k Ω
5.3.13 Pin "L"
Figure 11. L interface in lamp drive mode The device exits the stand-by mode when the switch "Key" (see Figure 11) is closed (i.e. by an internal high-side N-channel MOSFET. The maximum power dissipation allowed is Pretry. respecting the max power dissipation over a retry period.
Figure 12. Lamp driver overcurrent protection function and bit 3 of SPI read register 0x12 is set [13.4.6]. off-state (high-side recirculation is not possible). key status is verified every twait time intervals within a tchk,to time window. longer active, the L voltage cannot increase and remains to VLsat voltage level. switch-on procedure", see below example Figure 13.
Figure 15. Fault indicator lamp drive in alarm condition and key engaged Table 23. Electrical characteristics pin "L"
12 VL LTh
14 ILRVC,limLS (2)
19 IL OVCHS
Table 23. Electrical characteristics pin "L" (continued)
5.3.14 Pin "GHS" and "GLS"
Figure 16. External high current lamp pre-driver circuitry external MOSs' gates providing the necessary current. The gate-source-voltage of the external Power-MOS is limited by the driver circuit.
22 VL revHS
- In Power Stand-by mode the pull-up current is -5µA,min.
- In case of L pin used for RVC protocol (RVC drive mode) I(L)= 20mA,max.
- The microcontroller application software must take care to respect the value in item #17
been activated and it is working properly, otherwise they cannot be guaranteed. Table 24. Electrical characteristics pin "GHS" and "GLS"
5.3.15 Pin "LHC"
switched off and bit 0 of SPI read register 0x12 is set [13.4.6]. register 0x12 is set [13.4.6]. than VGHsTh parameter for high side MOS. Table 25. Electrical characteristics pin "LHC"
system recognizes that the lamp is connected to L pin and not to LHC pin.
10 VLHC
11 VLHC HS2
12 VGLS Th
13 VGHS Th
Table 25. Electrical characteristics pin "LHC" (continued)
5.3.16 Pin "RC"
Figure 17. RC pin connection on alternator Figure 18. Squared signal possible protocols that can be managed by regulator.
5.3.17 VREF_ADC
Figure 19. Internal voltage reference for ADC Table 26. Electrical characteristics pin "RC"
- VRC HThx and VRCLThx parameters are in tracking
Table 27. Electrical characteristics “VREF_ADC”
5.3.18 Pin "PH_OUT"
must withstand 48V as absolute voltage.
5.3.19 Charge pump output
limitation. In both standby mode and thermal shutdown the charge pump is disabled. Table 28. Electrical characteristics pin "PH_OUT"
1 VPHO L
3 VPHO H
Table 29. Charge pump output electrical characteristics
Table 29. Charge pump output electrical characteristics (continued) Table 30. 5-V (VDD) voltage regulator electrical characteristics
5.3.21 Reset output (nRST_SP)
suitable microcontroller startup phase when the system is switched on.
0.5 V → 1 V
- If short-to-ground time exceeds t VDDFAIL then VDD regulator is permanently kept off and only a Power-On Reset (PORn)
Table 30. 5-V (VDD) voltage regulator electrical characteristics (continued) Table 31. Reset output (nRST_SP) electrical characteristics
5.3.22 Temperature sensor
resolution of 10.5 mV ±1 mV/ºK. Figure 20. Temperature sensor output voltage vs. temperature silicon and the environment around the application board. Table 31. Reset output (nRST_SP) electrical characteristics (continued) Table 32. Temperature sensor (TEMP_OUT)
6 Warning, alarms and faults
restore procedure or to keep the system in a safe status.
6.1 System error flags
Table 33. System error flags
Warning, alarms and faults L9912
6.2 Lamp
The dashboard lamp (L or LHC) is used to notify faulty events to the driver. At start-up the lamp driver is, by default, switched on and must be switched off just after crank. The lamp must be activated if one or more of the following conditions are present: Excitation overcurrent (signaled in register 0x12) Battery overvoltage (signaled in register 0x12) Discrepancy between the applied excitation and the effective field excitation. A short to battery is not signaled by any flag of SPI registers but can be detected by comparing the two excitations [5.3.11] Phase error: persistent absence of phase signal [13.4.7] Phase regulation error: a persistent phase regulation request [13.4.7] Any of the above condition, before causing a lamp warning, must be confirmed for a lamp confirmation time (hundreds of milliseconds). When all above error conditions disappear, after a lamp-off confirmation time (hundreds of microseconds), the lamp is switched off.
7 Watchdog
not powered or doesn't work at all. the unit switches the power stage off and, if suitably configured, resets the microcontroller. Figure 21. Timing diagram of watchdog Once the watchdog has been correctly refreshed the above sequence restarts.
The following picture illustrates a typical watchdog refresh sequence. Figure 22. Typical watchdog refresh sequence
7.1 Power stage w atchdog handling
conditioned by L_KEY status. conditioned by LHC_KEY status.
7.2 Watchdog error
On startup the system has 500 ms to configure or to disable the watchdog before an error. The configuration is accomplished by writing the relevant SPI register. entering the stand-by mode; this choice makes easier test and debug activities.
7.3 Watchdog freeze
7.4 Persistent watchdog failure
the system, if possible, it is necessary to do a power on reset. watchdog error occurrences VDD is released and a new 5 trials sequence is applied. Figure 23. Persistent watchdog failure diagram The watchdog reset count can be read and cleared through the relevant SPI register.
8 Thermal shutdown
junction temperature reaches 200 degrees. control the junction temperature and take the appropriate actions. Figure 24. Thermal shutdown diagram Table 34. Thermal shutdown electrical characteristics
1 Tsd Thermal shutdown Guaranteed by design 185 200 215
2 Thyst Hysteresis - 3 6 9
9 Turbo mode
During alternator and/or regulator production test it could be useful to reduce the system timings in order to save time; for this reason it is possible to set system in TURBO MODE status [see 5.3.6]. In this condition the application SW should reduce or cancel internal timeouts (e.g. lamp alarm) thus accelerating the test procedures.
10 Communication configurations
protocol, L pin for RVC protocol and RC pin for PCM and C-TERM protocols. SPI bit settings; besides, LIN is available or not according to the device option. Table 35. How to configure the system
- PROT_SEL pin has an internal 100k pull-up resistor.
11 ADC channels
status; this chapter outlines some details about voltage ranges. Table 36. ADC channels
Microcontroller non volatile memories L9912
12 Microcontroller non volatile memories
STM8AF6268 microcontroller embedded into EPONA has two non-volatile memories: Flash Program Memory (32k bytes): it is used to store the application code and calibration parameters (if any). EEPROM Data Memory (1k bytes): it can be used to store calibration data (if any) or some other data that need to be preserved. The main parameters that characterize EEPROMs is the retention time and the maximum number of erase/write cycles: after the minimum guaranteed retention time and above the maximum number of erase/write cycles, the data stored in the memory are no longer guaranteed; for this reason, the program memory is trimmed to maximize the data retention time at the expense of erase/write cycles' number whereas the data memory is trimmed to maximize the erase/write cycles' number without compromising the retention time.
13 SPI interface
SPI interface is the communication channel between the microcontroller (Master) and the Smart Power (Slave). It consists of an input shift register, an output shift register and four control signals. MOSI (Master Output Slave Input) is the data input line for the Smart Power input shift register. MISO (Master Input Slave Output) is the data output line from the Smart Power output shift register. SCK is the clock source input while CSN is the active low chip select input.
13.1 SPI protocol
All SPI communications are executed in exact 24 bit increments. The EPONA contains a data validation method through the SCK input to avoid transmission with a bit number not equal to 24 bits from being written to the device. The SCK input counts the number of received clocks and should the clock counter exceed or count fewer than 24 clocks, the received message is discarded without changes to internal registers. The general format of the 24-bit transmission frame for SPI interface is shown here below: Data to the device (i.e. MOSI) consists of: Data returned from the device (i.e. MISO) consists of: The communications is controlled through CSN, enabling and disabling communication. When CSN is at logic high, all SPI communication I/O is tri-stated and no data is accepted. On the falling edge of CSN the data to be transmitted on MISO are latched and therefore the Bit Position 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GSW RPAR Data Bits MISO R/W ADDR RESERVED WPAR Data Bits MOSI R/W Read/Write selection bit ADDR [4-0] Register address bits RESERVED - WPAR Parity bit DATA [13-0] In write operation these bit are the data to be written to the destination register; in read operation these bits define a key (0x0A5) to enable the read and clear feature of some bits GSW Global Status word RPAR Parity bit DATA [13-0] Data bit read from the addressed register
data are up-dated. The MOSI pin receives serial data from the master with MSB first. See next paragraphs for further details.
13.2 SPI electrical characteristics
13.2.1 CSN input
13.2.2 SCK, MOSI input
Table 37. CSN input electrical characteristics
4 RCSN pu CSN pull-up resistor
Table 38. SCK, MOSI input electrical characteristics
13.2.3 MISO output
13.3 SPI timing
All electrical characteristics are valid for the following conditions unless otherwise noted. Table 39. MISO output electrical characteristics Table 40. SPI timing characteristics
18 T intfrm SPI inter-frame time De sign Information 15 µs
Figure 25. SPI timing diagram
13.4 SPI registers
status and configuration information. Status bits in read register contain the latched status of the relevant information. system status and configuration information. Status bits in read register contain the latched status of the relevant information. word transmitted by the microcontroller to the Smart Power is 0x0A5. and parameters and to activate/deactivate system outputs. A write operation returns the previous register value. In some read/write registers there are read only bits. Some registers are locked and a write access must be preceded by an unlock operation. Table 41. SPI register
13.4.1 Register read operation
Table 41. SPI register (continued) Table 42. Register read operation
14 Parity (odd) - -
13.4.2 Register write operation
The parity bit is computed to give an odd number of bit set to 1 in the 24 bits message. any register resets the lock status.
13.4.3 GSW: global status word
Table 43. Register write operation Table 44. GSW: global status word
13.4.4 SPI errors
The PREV_SPI_FAILED bit of GSW notifies an error in the previous received SPI frame.
13.4.5 WAKEUP SOURCE register [0x11]
Table 44. GSW: global status word (continued) Table 45. WAKEUP SOURCE register [0x11]
13 RESERVED - -
12 IGNIT_KEY (1) - 0: IGNIT input OFF
11 L_KEY (1) -
10 LHC_KEY (1) - 0: LHC input OFF
9 VDD_UV 0 (RC) The previous µC reset has been caused by a
8 RESERVED - -
7 WDG_FAIL_SWT_OFF_PWR_STG 0 (RC)
6 WDG_FAIL_RESET_UP 0 (RC) When 1 notifies that the system reset has
5 WKUP_BY_L 0 (RO)
relevant input pin after a system wake-up.
4 WKUP_BY_LHC
3 WKUP_BY_IGNIT
2 WKUP_BY_PH
1 WKUP_BY_RC
0 WKUP_BY_LIN (2)
- These bits report the current status of the relevant input without any latch logic.
- If the wakeup is triggered by a protocol line edge it is possible that the microcontroller loses the first data
node must take into account this eventuality. Table 45. WAKEUP SOURCE register [0x11] (continued)
13.4.6 LAMP LIN GENERAL STATUS register [0x12]
Table 46. LAMP LIN GENERAL STATUS register [0x12]
13 LIN_PERM_DOM 0 (RC) LIN Permanent Dominant
12 LIN_TXD_DOM 0 (RC) LIN Dominant TXD
11 LIN_PERM_REC 0 (RC) LIN Permanent Recessive
- A driver is immediately switched off at the occurrenc e of an overcurrent event and remains “locked” until
[13.4.12]) has not yet been set. clear option after a suitable time interval.
6 APLUS_UV 0 (RC) Undervoltage A+
5 THSD 0 (RC) Overtemperature
- The over-temperature condition auto matically causes a power off (thermal shutdown): the THSD bit can be
that the previous power off was caused by an over-temperature occurrence.
1 LHC_HS_OC (1) 0 (RC) LHC High side driver overcurrent
0 LHC_LS_OC (1) 0 (RC) LHC Low side driver overcurrent
13.4.7 PH-SENSE register [0x13]
signals) is (are) suitably filtered and processed. Table 47. PH-SENSE register [0x13]
13 PH-Sense Measurement Timed -
12 PHASE_REGULATION_REQUEST 1
threshold for at least 4 periods.
11 Reserved - -
measurement expressed into 64 us units. Table 48. Example in a system with 6 pole pairs at 3000 rpm
giving a maximum input signal frequency of roughly 8.3 kHz. values lead to wrong results.
13.4.8 WATCHDOG / THERMAL SHUTDO WN RESET COUNT register [0x14]
If needed, at system boot the SW can read the register to know the system history. Table 49. RPM ranges corresponding to different pole pairs values Table 50. WATCHDOG / THERMAL SHUTDOWN RESET COUNT register [0x14]
4 TURBO_MODE 0 (RO)
13.4.9 DEVICE ID register [0x1F]
13.4.10 SYSTEM / UN LOCK register [0x01]
Table 51. DEVICE ID register [0x1F]
12 Reserved - -
11 LIN_PROT_DENIED_OTP RO 0: LIN available
10 APPL_24V_DENIED_OTP RO 0: 24V supported
9 ProtSel RO PROT_SEL pin image
Table 52. SYSTEM / UNLOCK register [0x01]
12 UNLOCK_SEL24V_EN 0 (WO Write 1 to enable the write access to
10 UNLOCK WDG Config REG_06 0 (WO) Write 1 to enable the write access to the
9 UNLOCK WDG: Init Time-Out
8 UNLOCK_WDG_FAIL_REST_µC 0 (WO)
4 UNLOCK EPONA Cfg-REGs SW
0 UNLOCK_SYST_POWER_OFF 0 (WO)
access to a locked bit will have no effect.
13.4.11 SYSTEM OPERATION register [0x02]
Table 53. SYSTEM OPERATION register [0x02]
13 Reserved -
12 SEL24V_EN (LOCKED) 0
11 Reserved -
10 Reserved -
9 WDG_INIT_ENABLE (LOCKED) 0/1 (1)
- On power on reset the value of these bit is 0, on wakeup the bits maintain the last programmed values (if
any); these bits are not cleared by the SW reset command.
8 WDG_FAIL_REST_uC
4 Apply EPONA Cfg-REGs SW
- After a SW reset the Watchdog is also initialized and, if not previously disabled, must be programmed and
refreshed to avoid a watchdog error occurrence. RESET) corresponding to the reset status. read and read and clear bits.
0 POWER_OFF (LOCKED) (3)
- The POWER_OFF command is ignored if at least one, among the enabled wake-up sources (see register
0 Writing 1 the system enters standby mode if
13.4.12 External POWE R MOS register [0x03]
Table 54. EXTERNAL POWER MOS register [0x03]
11 CP_Enable (1)(2) 0 To ensure low current in standby coming
10 UV_DIS 0
9 VCLTH_SEL 0 RC Protocol V Low Level Threshold
8 EXTP_LS 0 Excitation Low Side configuration selection
13.4.13 WAKE-UP sources and DFM GEN setup register [0x04]
disable the wake-up sources.
- Charge pump is not activated if an overvoltage/undervoltage condition is present.
- Charge pump typically takes about 30 us to reach an active level; the application SW should monitor the
CP_LOW condition to verify the effective status of the circuitry. Table 54. EXTERNAL POWER MOS register [0x03] (continued) Table 55. WAKE-UP sources and DFM GEN setup register [0x04]
12 WKUP_SOURCE_LIN_DISABLE 0 When set this bit prevent the LIN/BSS
11 WKUP_SOURCE_RC_DISABLE 0 When set this bit prevent the RC
10 WKUP_SOURCE_IGNIT_DISABLE 0 When set, this bit inhibits pin IGNIT to
9 WKUP_SOURCE_LHC_DISABLE 0 When set, this bit inhibits pin LHC to
8 WKUP_SOURCE_L_DISABLE 0 When set, this bit inhibits pin L to
7 Reserved - -
available on register 0x11, but can drive the lamp output. the relevant wake-up disable bit.
6 DFM_polarity 1
Table 55. WAKE-UP sources and DFM GEN setup register [0x04] (continued)
13.4.14 DFM PWM DUTY CYCLE register [0x05]
This register is used to configure DFM duty cycle [5.3.6]. effective duty cycle of 36.9%. Table 56. DFM PWM DUTY CYCLE register [0x05] Table 57. Duty cycle resolution changes according to the frequency
13.4.15 WATCHDOG CONFIG register [0x06]
Table 58. WATCHDOG CONFIG register [0x06]
13.4.16 CP-SPREAD-SPECTRUM & LIN SETTING register [0x08]
Table 59. CP-SPREAD-SPECTRUM & LIN SETTING register [0x08]
12 WOBBLE_MODE_DIS 0
11 WOBBLE_FREQUENCY 0
4 LIN_PU_DIS 0
2 SPI_LINRX_ONLY 0
1 SPI_LINTX_TOUT (1)
- In order to establish LIN traffic and related erro r handling it is mandatory LIN_IN_USE=1: write 0x0008 '
In this case: write 0x000A ' [0x08] register, SPI TX frame 0xA0400A.
0 LINFLASH 0
13.4.17 DRV SETTINGS register [0x09]
13.4.18 TEST MODE ST ATUS register [0x0B]
could read this register to check if the device is working in a correct condition. Table 60. DRV SETTINGS register [0x09]
12 CSA_ENABLE (1)
- Current Sense Amplifier CANNOT be enabled befor e EXTP_LS (bit 8 of [0x03] register) has been
7 L_LHC_PULLDW_DIS (2)
- If this bit is active any standby request will be ignored.
0 L/LHC active pull down disable
5 L_HS_EN (3)
- High Side drivers need charge pump activation.
4 L_LS_EN (4)
- After power-up, the Smart power logic will automatically activates the line (L or LHC) corresponding to the
effective status of the relevant the input that can be understood reading the wakeup source register. or vice versa, it is necessary to switch both the drivers off and then to activate the desired driver. on without waiting any SW command. is off even if the bit is 1.
3 LHC_HS_EN (3) 0 Turn on LHC-High side
2 LHC_LS_EN (4) 1 Turn on LHC-Low side
0 VLHC_LS1_SEL 0 Over current threshold selection Low side
13.4.19 WATCHDOG REFRESH register [0x0F]
13.5 SPI sequence example
Table 61. WATCHDOG REFRESH register [0x0F] specified by bits 13 and 12 of watchdog config register. The counter is cleared on watchdog error occurrence. Table 62. SPI sequence examples
Table 62. SPI sequence examples (continued)
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 26. TQFP44 (10x10x1.0 mm exp. pad down) package outline
Figure 27. TQFP44 (6X6 pad size) PCB soldering pad footprint Table 63. TQFP44 (10x10x1.0 mm exp. pad down) package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits.
15 Order codes
Note: The device is distributed through EBV. Table 64. Device summary
Table 65. Document revision history 10-Oct-2016 1 Initial release. paragraph below the Table 13.