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Document overview
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- PDF pages: 25
Technical content
Datasheet sections
- 1 Block diagrams and pins configur ation
- 1.1 Block diagram (option A)
- 1.2 Option B features
- 1.3 Option C features
- 2 Absolute maximum ratings
- 3 Functional description
- 3.1 Voltage regulator
- 3.2 Reset
- 3.3 NMI and RESET driver delay
- 3.4 RESET adjustable threshold
- 3.5 Watchdog
- 4 VDD regulated voltage
- 5 VDD_LOW (option C)
- 6 Device options
- 6.1 Option A
- 6.2 Option B
- 6.3 Option C
- 7 Electrical and thermal characteristics
- 8 Package information
- 9 Revision history
Features
■ Operating DC supply voltage range 5.6 V to 31 V ■ Low current consumption (110 µA typ @ Iout = 0) ■ High precision output voltage (2 %) ■ Low dropout voltage ■ VDD tracking regulator switchable on/off by VDD_EN pin ■ Reset circuit sensing the output voltage down to 1 V. ■ Double reset function ■ Adjustable reset threshold ■ External capacitor to set NMI/ reset power up delay and watchdog frequency ■ Over temperature protection ■ Wide temperature range (TJ = -40 °C to 150 °C) ■ Short circuit proof ■ Suitable for use in automotive electronics
Description
The L9777 is a monolithic integrated low drop regulator which can supply up to 200 mA, available in the PowerSSO-12 package. It is designed to supply microprocessor systems under severe conditions of automotive applications and therefore equipped with additional protection functions against over load, short circuit and over temperature. Of course the L9777 can also be used in other applications where a regulated voltage is required. PowerSSO-12 (exposed DIE Pad) Table 1. Device summary
1 Block diagrams and pins configuration
1.1 Block diagram (option A)
Figure 1. Block diagram (option A)
1.2 Option B features
- VDD can sustain short to 40 V regardless of VI battery voltage
- Current capability of VDD scaled down to 50 mA with dropout of 1.5 V (Max.)
- In default condition, VDD and WD functions are disabled using 2 pull down current on VDD_EN and WD_EN pin
- Standby current consumption reduced to 100 µA (Typ.)
Figure 2. Package pin configuration (options A and B)
Figure 3. Block diagram (option B) Figure 4. Block diagram (option C)
1.3 Option C features
- VDD can sustain short to 40 V regardless of VI battery voltage
- Current capability of VDD scaled down to 50 mA with dropout of 1.5V (Max.)
- In default condition, VDD and WD functions are disabled using 2 pull down current on VDD_EN and WD_EN pin
- Double reset function removed and pin RESET used to detect undervoltage condition on VDD regulated voltage (VDD_LOW pin) watchdog VIVbatt WD D CD TIMING NMI WD_EN GND VCC CVCC IVCC=200mA Voltage Reference Low Voltage Reset Start up R VOFF +_ 1.26V RESET IWD_EN RADJ Delay VDD_EN VDD RNMI RRESET RWD VD CTIMING IVDD= 50 mA CVDD VMUXTH IVDD_EN watchdog VIVbatt WD D CD NMI WD_EN GND VCC CVCC IVCC=200mA Voltage Reference Low Voltage Reset Start up R VOFF +_ 1.26V VDD_LOW IWD_EN RADJ VDD_EN VDD RNMI RVDD_LOW RWD VD IVDD = 50mA CVDD VMUXTH IVDD_EN Low Voltage Reset 300mV
Figure 5. Package pin configuration (option C) Table 2. Pin description
1 O RESET/VDD_LOW
frequency of WD signal is too low. voltage detector and the time response of the watchdog monitor.
4 I VDD_EN
10 O VDD
Output regulated voltage switched on/off by VDD_EN pin.
11 GND Ground
12 I RADJ
possible to set the VCC under voltage threshold. Table 2. Pin description (continued)
2 Absolute maximum ratings
Table 3. Absolute maximum ratings
Table 3. Absolute maximum ratings (continued)
3 Functional description
3.1 Voltage regulator
= 5.6 V to 31 V) and temperature range (TJ = -40 °C to 150 °C). A short circuit protection to GND is provided (see Figure 6). Figure 6. VCC versus output current IVCC
3.2 Reset
output voltage stays lower than VCCUN for a filter time TRR, then NMI goes low. according to the depth of spike on output voltage (see following picture). Figure 7. Filter time between VCC and NMI pin RADJ, there is only a constant filter time (TRRADJ) of 1 µs min value.
3.3 NMI and RESET driver delay
internally limited of value respectively INMIL and IRESL. slope linearly dependent on external capacitance. approximation using this expression. Figure 10. RESET and NMI drivers fall time
3.4 RESET adjustable threshold
where: VRADJTH=1.2V (typ) and VCCUN_ext is the reset threshold. internal under voltage threshold value is 0.94*VCC (typ.). Figure 11. Resistor divider to adjust the under voltage threshold
3.5 Watchdog
oscillator and external WD input signal. low and WD edges are masked, so the TWOL reset time is fully guaranteed. The Watchdog operation is not active only if WD_EN input pin is set low.
guaranteed even in this condition. Figure 12. Watchdog timing waveforms
VDD regulated voltage L9777 16/25 Doc ID 13496 Rev 2
4 VDD regulated voltage
L9777 provides a second regulated voltage in tracking with VCC main regulator capable to source load with up to 100 mA output current capability. VDD tracking regulator function is controlled by VDD_EN input pin. If pin is set high VDD voltage becomes available. If pin is set low or left floating regulator is disabled. Note that VDD regulator will be disable also in case of undervoltage condition on VCC main regulator, so at power up regulator will start up only when VCC rises over undervoltage threshold without TRD power up delay time, even if VDD_EN pin is set high.
5 VDD_LOW (option C)
filter time TFVDD VDD_LOW output voltage is set low. VDDUN is a reference voltage 300 mV (Typ) lower than VCC regulated voltage. Figure 13. VDD_LOW filter tim
6 Device options
6.1 Option A
This is the standard configuration with VDD output capable to source up to 100 mA to an external load with low dropout (400 mV max.) and double reset function provided (NMI and RESET output). Note that as we can see in absolute section VDD and TIMING pin are capable to sustain only short to VI pin. With this option input digital pins VDD_EN and WD_EN are both pulled up by 5 µA typ current source (minimum quiescent current is 110 µA typ.).
6.2 Option B
With this option VDD and TIMING pins are both capable to sustain short to 40V regardless of VI battery voltage. To provide this feature a series diode is introduced between VI pin and VDD power PMOS source. In this configuration current capability on VDD output is scaled down to 50 mA while dropout voltage increases to 1.5V (Max). All other features are un- changed and double reset capability is maintained. In option B VDD_EN and WD_EN are both pulled down with 10 µA typ internal current source so minimum quiescent current is reduced to 100 µA typ.
6.3 Option C
Using option C VDD is capable to sustain short to 40 V as in option B. VDD output current is scaled down to 50 mA and dropout increase up to 1.5 V (Max). Double reset feature is removed and RESET pin is used to monitor VDD output voltage (VDD_LOW pin). A spike dependent filter time similar to VCC main regulator is provided and same low voltage reset specifications applies to bipolar output driver (VDD_LOW driver). For this reason TIMING pin is no more used and can be left floating or shorted to ground. Note that NMI output pin behaves normally as in option A and becomes the main reset signal for VCC and watchdog monitor. As in option B VDD_EN and WD_EN are both pulled down with 10 µA typ internal current source so minimum quiescent current is reduced to 100 µA typ.
7 Electrical and thermal characteristics
VI = 5.6V to 31V, TJ = -40°C to +150°C unless otherwise specified. Table 4. Electrical and thermal characteristics
Table 4. Electrical and thermal characteristics (continued)
8 Package information
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 14. PowerSSO-12 mechanical data and package dimensions ceed 0.15mm (.006inch) in total.
9 Revision history
Table 5. Revision history 10-May-2007 1 Initial release. Changed ESD parameter values in Table 3. Modified Section 1.3: Option C features on page 6. Modified Section 6.3: Option C on page 18.