L9733XP

L9733CNTR STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 34

Technical content

Datasheet sections

• 1 Pin description
• 2 Operating conditions
• 2.1 Operating range
• 2.1.1 Functional operative range
• 2.1.2 Jump start conditions
• 2.1.3 Operation at low battery condition
• 2.1.4 Operation at load dump condition
• 2.1.5 Loss of protection against short to battery
• 2.2 Absolute maximum ratings
• 2.3 Thermal data
• 3 Electrical performance c haracteristics
• 3.1 DC characteristics
• 3.2 AC characteristics
• 3.3 SPI characteristics and timings
• 4 Functional description
• 4.1 Configurations for outputs 1-8
• 4.1.1 Low-side drivers
• 4.1.2 High-side drivers
• 4.2 Outputs 1-5
• 4.3 Outputs 6-8
• 4.4 Drn1-8 susceptibility to negative voltage transients
• 4.5 Supply pins
• 4.5.1 Main power input (Vdd)
• 4.5.2 Battery supply (Vbat)
• 4.5.3 Discrete inputs voltage supply (VDO)
• 4.6 Discrete inputs
• 4.6.1 Output 6-8 enable input (In6, ln7, ln8)
• 4.6.2 Reset input (RES)
• 5 Serial peripheral interface (SPI)

Features

■ Eight independently self configuring low/high drivers ■ Supply voltage from 4.5 V to 5.5 V ■ RON(max) = 0.7  @ Tj = 25 °C, RON(max) = 1.2  @Tj = 125 °C ■ Minimum current limit of each output 1 A ■ Output voltage clamping min. 40 V in low-side configuration ■ Output voltage clamping max. -14 V in high-side configuration ■ SPI interface for outputs control and for diagnosis data communication ■ Additional PWM inputs for 3 outputs ■ Independent thermal shutdown for all outputs open load, short to GND, short to Vb, overcurrent diagnostics in latched or unlatched mode for each channel ■ Internal charge pump without need of external capacitor ■ Controlled SR for reduced EMC

Description

The L9733 is a highly flexible monolithic, medium current, output driver that incorporates 8 outputs that can be used as either internal low or high-side drives in any combination. Outputs 1-8 are self-configuring as high or low- side drives. Self-configuration allows a user to connect a high or low-side load to any of these outputs and the L9733 will drive them correctly as well as provide proper fault mode operation with no other needed inputs. In addition, outputs 6, 7 and 8 can be PWM controlled via a external pins (IN6-8). This device is capable of switching variable load currents over the ambient range of -40 °C to +125 °C. The outputs are MOSFET drivers to minimize Vdd current requirements. For low-side configured outputs an internal zener clamp from the drain to gate with a breakdown of 50 V minimum will provide fast turn off of inductive loads. When a high-side configured output is commanded Off after having been commanded On, the source voltage will go to (VGND - 15 V). An 16 bit SPI input is used to command the 8 output drivers either "On" or "Off", reducing the I/O port requirement of the microcontroller. Multiple L9733 can be daisy-chained. In addition the SPI output indicates latched fault conditions that may have occurred. PowerSSO-28 Table 1. Device summary

1 Pin description

Figure 1. Pin connection (top view) Table 2. Pin description

1 VDD 5 Volt supply input

2 SCLK SPI serial clock input

3 CS SPI chip select (active low)

12 IN6 Discrete input used to PWM output driver #6

13 IN7 Discrete input used to PWM output driver #7

14 Vbat Battery supply voltage

15 GND Analog ground

16 IN8 Discrete input used to PWM output driver #8

17 RES Reset input (active low)

Note: The exposed slug must be soldered on the PCB and connected to GND.

26 DI SPI data in

27 DO SPI data out

28 VDO Microcontroller logic interface voltage

Table 2. Pin description (continued)

2 Operating conditions

2.1 Operating range

recover with no damage or degradation.

2.1.1 Functional operative range

Electrical performance characteristics.

2.1.2 Jump start conditions

18 V  Vbat  27 V (-40 °C  Tj  150 °C);

Operation at Jump start condition for a maximum duration of 1 minute. SPI bus and the inputs are functional during the Jump-Start condition. to stay functional for Vbat between 18 V and 27 V. Start condition is not repeated for more than five times. Table 3. Operating range

2.1.3 Operation at low battery condition

2.1.4 Operation at load dump condition

27 V  Vbat  40 V (-40 °C  Tj  150 °C)

There is not an internal circuit that switches OFF the drivers during load dump condition. to stay functional during load dump condition.

2.1.5 Loss of protection a gainst short to battery

functional, and the L9733 may fail with EOS.

2.2 Absolute maximum ratings

Table 4. Absolute maximum ratings

1. For the DRNx the MAX ASB value is the Max Clamp Voltage (see Table 6 on page 13 - DRNx Clamp
2. Device is only protected vs. GND.

2.3 Thermal data

Table 5. Thermal data

1. With 2s2p PCB thermally enhanced.

3 Electrical performance characteristics

part meet these characteristics.

3.1 DC characteristics

Table 6. DC characteristics

Table 6. DC characteristics (continued)

3.2 AC characteristics

1. R dsonDrn1-8  1.2 ; at Vbat between 3.5 V and 27 V and T between -40 °C and 150 °C
2. Design Information, not tested.

Table 7. AC characteristics

Figure 2. Output turn on/off delays and slew rates Table 7. AC characteristics (continued)

3.3 SPI characteristics and timings

Table 8. SPI characteristics and timings

Functional description L9733 18/34 Doc ID 11319 Rev 11

4 Functional description

L9733 integrates 8 self-configuring outputs (OUT1-8) which are able to drive either incandescent lamps, inductive loads (non-pwm'd, in pwm is necessary an external diode to reduce flyback power dissipation), or resistive loads biased to Vbat (low-side configuration) or to GND (high-side configuration). These outputs can be enabled and disabled via the SPI bus. Each of these outputs has a short circuit protection (with 0.8-2.4 Amps threshold) selectable via SPI bus between a filtered switching OFF overcurrent protection or a linear current limitation (default condition after power ON is switching OFF protection enabled). An over-temperature protection as described in Section 2.1 is available for each outputs. When a high-side configured output is commanded OFF after having been commanded ON, the source voltage will go to (VGND - 15 V). This is due to the design of the circuitry and the transconductance of the MOSFET. When a low-side configured output is commanded OFF after having been commanded ON, the output voltage will rise to the internal zener clamp voltage (50 VDC minimum) due to the flyback of the inductive load. Outputs 1-8 are able to drive any combination of inductive loads or lamps at one time. Inductive loads for the L9733 can range from 35mH to a maximum of 325 mH. The recommended worst-case solenoid loads (at -40 °C) are calculated using a minimum resistance of 40 for each output. The maximum single pulse inductive load energy the L9733 outputs is able to be safely handle is 20 mJ at -40 °C to 125 °C (Worst-case load of 325 mH and 40 ).

4.1 Configurations for outputs 1-8

The drain and source pins for each output must be connected in one of the two following configurations (see Figure 7).

4.1.1 Low-side drivers

When any combination of outputs 1-8 are connected in a low-side drive configuration the source of the applicable output (Src1-8) shall be connected to ground. The drain of the applicable output (Drn1-8) shall be connected to the low-side of the load.

4.1.2 High-side drivers

When any combination of outputs 1-8 are connected in a high-side drive configuration the Drain of the applicable output (Drn1-8) shall be connected to Vbat. The source of the applicable output (Src1-8) shall be connected to the high-side of the load.

4.2 Outputs 1-5

These five outputs can be used as either high or low-side drives. The room temperature Rdson of these outputs is 0.7 . A current limited (100 µA max) voltage generator is connected to Src 1-5 for open load and short to GND detection when a low-side configured output is commanded OFF . Another current limited (100 µA max if VDrn 1-5 > 60 %Vbat, 280 µA max if VDrn 1-5 < 60 % Vbat) voltage generator is connected to Drn 1-5 for open load and short to V bat detection when a high-side configured output is commanded OFF . Drain pins of outputs 1-5 (Drn1-5) are connected to the drains of the N channel MOSFET

L9733 Functional description Doc ID 11319 Rev 11 19/34 transistors. Source pins of outputs 1-5 (Src1-5) are connected to the sources of the N-channel MOSFET transistors.

4.3 Outputs 6-8

These three self-configuring outputs can be used to drive either high or low-side loads. In addition to being controlled by the SPI BUS these outputs can also be enabled and disabled via the IN6 & IN7& IN8 inputs. The IN6, IN7 and IN8 inputs are logically or'd with the SPI commands to allow either the IN6 & IN7 & IN8 inputs or the SPI commands to activate these outputs. The use of the IN6 & IN7 & IN8 pins for PWM control on these outputs should only be done with non-inductive loads if an external flyback diode is not present. The room temperature Rdson of these four outputs is 0.7 . A current limited (100µA max) voltage generator is connected to Src 6-8 for open load and short to GND detection when a low-side configured output is commanded OFF . Another current limited (100µA max if VDrn 6-8 > 60%Vbat, 280 µA max if VDrn 6-8 < 60 %Vbat) voltage generator is connected to Drn 6-8 for open load and short to Vbat detection when a high-side configured output is commanded OFF . Drain pins of Outputs 6-8 (Drn6-8) are connected to the drains of the N channel MOSFET transistors. Source pins of Outputs 6-8 (Src6-8) are connected to the sources of the N channel MOSFET transistors.

4.4 Drn1-8 susceptibility to negative voltage transients

All outputs connected in the low-side configuration must have a ceramic chip capacitor of 0.01µF to 0.1 µF connected from drain to ground. This is needed to prevent potential problems with the device operation due to the presence of fast negative transient(s) on the drain(s) of the device. Adequate de-coupling capacitors from the Drain (VBAT) to ground shall be provided for high-side configured outputs.

4.5 Supply pins

4.5.1 Main power input (Vdd)

An external +5.0 ±0.5 VDC supply provided from an external source is the primary power source to the L9733. This supply is used as the power source for all of its internal logic circuitry and other miscellaneous functions.

4.5.2 Battery supply (Vbat)

This input is the supply for the on board charge pump. This input shall be connected directly to battery. If this input is not connected to the same supply, without additional voltage drops, of the drains of any high-side connected outputs, then the Rdson of that given output will be higher than the specified maximum.

4.5.3 Discrete inputs voltage supply (VDO)

This pin is used to supply the discrete input stages of L9733 and must be connected to the same voltage used to supply the peripherals of the processor interfaced to L9733.

Functional description L9733 20/34 Doc ID 11319 Rev 11

4.6 Discrete inputs

4.6.1 Output 6-8 enable input (In6, ln7, ln8)

This input allows Output 6 (or Output 7, or Output 8) to be enabled via this external pin without the use of the SPI. The SPI command and the In6-7 input are logically or'd together. A logic "1" on this input (In6, ln7 or ln8) will enable this output no matter what the status of the SPI command register. A logic "0" on this input will disable this output if the SPI command register is not commanding this output on. This pins (In6, ln7 or ln8) can be left "open" if the internal output device is being controlled only via the SPI. This input has a nominal 100k resistor connected from this pin to ground, which will pull this pin to ground if an open circuit condition occur. This input is ideally suited for non-inductive loads that are pulse width modulated (PWM'd). This allows PWM control without the use of the SPI inputs.

4.6.2 Reset input (RES)

When this input goes low it resets all the internal registers and switches off all the output stages. This input has a nominal 100 k resistor connected from this pin to VDD, which will pull this pin to VDD if an open circuit condition occur.

L9733 Serial peripheral interface (SPI) Doc ID 11319 Rev 11 21/34

5 Serial peripheral interface (SPI)

The L9733 has a serial peripheral interface consisting of Serial Clock (SCLK), Data Out (DO), Data In (DI), and Chip Select (CS). All outputs will be controlled via the SPI. The input pins CS, SCLK, and DI, thanks to VDO pin, have level input voltages allowing proper operation from microcontrollers that are using 5.0 or 3.3 volts for their Vdd supply. The design of the L9733 allows a "daisy-chaining" of multiple L9733's to further reduce the need for controller pins.

5.1 Serial data output (DO)

This output pin is in a tri-state condition when CS is a logic '1'. When CS is a logic '0', this pin transmits 16 bits of data from the fault register to the digital controller. After the first 16 bits of DO fault data are transmitted (after a CS transition from a logic '1' to a logic '0'), then the DO output sequentially transmits the digital data that was just received (16 SCLK cycles earlier) on the DI pin. The DO output continues to transmit the 16 SCLK delayed bit data from the DI input until CS eventually transitions from a logic '0' to a logic '1'. DO data changes state 10 nsec or later, after the falling edge of SCLK. The LSB is the first bit of the byte transmitted on DO and the MSB is the last bit of the byte transmitted on DO, once CS transitions from a logic '1' to a logic '0'.

5.2 Serial data input (DI)

This input takes data from the digital controller while CS is low. The L9733 accepts an 16 bit byte to command the outputs on or off. The L9733 also serially wraps around the DI input bits to the DO output after the DO output transmits its 16 fault flag bits. The LSB is the first bit of each byte received on DI and the MSB is the last bit of each byte received on DI, once CS transitions from a logic '1' to a logic '0'. The last 4 bits (b15-b12) of the first 16 bit byte are used as key-word. The 4 bits (b11-b8) of the first 16 bits byte are used to select writing mode between OUT8-1 status and diagnosis operating mode . The DI input has a nominal 100 k resistor connected from this pin to the VDO pin, which pulls this pin to VDO if an open circuit condition occurs.

5.3 Chip select (CS)

This is the chip select input pin. On the falling edge of CS, the DO pin is released from tri- state mode. While CS is low, register data are shifted in and shifted out the DI pin and DO pin, respectively, on each subsequent SCLK. On the rising edge of CS, the DO pin is tri- stated and the fault register is "Cleared" if a valid DI byte has been received. A valid DI byte is defined as such: – a multiple of 16 bits was received. – a valid key-word was received The fault data is not cleared unless all of the 2 previous conditions have been met. The CS input has a nominal 100 k resistor connected from this pin to the VDO pin, which pulls this pin to VDO if an open circuit condition occurs.

5.4 Serial clock (SCLK)

the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK. which pulls this pin to VDO if an open circuit condition occurs.

5.5 Initial input command register and fault register SPI cycle

will be clocked out of DO (fault bits).

5.6 Input command register

transmitted byte shall be ignored (invalid). Table 9. Bit command register definition

Table 10. Command register logic definition

Other L9733 features L9733 24/34 Doc ID 11319 Rev 11

6 Other L9733 features

6.1 Charge pump usage

In order to provide low Rdson values when connected in a high-side configuration, a charge pump to drive the internal gate voltage(s) above Vbat is implemented. The charge pump used on the L9733 doesn't need external capacitor. The L9733 uses a common charge pump and oscillator for all the 8 configurable output channels. The charge pump uses the Vbat supply connected directly to the Vb pin. The normal range of the Vbat voltage is 10 to 18V18V. However, the L9733 is functional with Vbat voltages as low as 4.5V DC with eventually a degradation of Rdson. The frequency range of this charge pump is from 3.6 to 7.6 MHz. The frequency is above 1.8 MHz in order to be above the AM radio band and below 8.0 MHz so that harmonics do not get within the FM radio band.

6.2 Waveshaping

Both the turn on and the turn off slew rates on all outputs (OUT1-8) are limited to between 10 µs and 100 µs for both rise and fall times (10 to 90 %, and vice versa), to reduce conducted EMC energy in the vehicle's wiring harness. The characteristics of the turn-on and turn-off voltage is linear, with no discontinuities, during the output driver state transition.

6.3 POR register initialization

When the L9733 wakes up, the Vdd supply to the L9733 is allowed from 0 to 5 VDC in 0.3 to 3ms. The L9733 has a POR circuit, which monitors the Vdd voltage. When the Vdd voltage reaches an internal threshold, and remains above this trip level for at least 5 to 20 µs, the Command and Fault registers are "cleared". Before Vdd reaches this trip level, none of the eight outputs are allowed to momentarily glitch on.

6.4 Thermal shutdown

Each of the eight outputs has independent thermal protection circuitry that disables each output driver once the local N-Channel MOSFET's device temperature reaches between +151 and +200 °C. A filter is present to validate the thermal fault (5 µs to 20 µs). There is a 5 to 15 °C hysteresis between the enable and disable temperature levels. The faulted channel will periodically turn off and on until the fault condition is cleared, the ambient temperature is decreased sufficiently or the output is commanded off. If a thermal shutdown, of one or more output drivers, is active during the falling edge of the chip select (CS) signal all the bits of the Fault Register are "setted" to "1" (thermal shutdown is not latched and could be read only in the moment it is present). The thermal fault is cleared on the rising edge of Chip Select if a valid DI byte was received. Note: Due to the design of the L9733 each output's thermal limit "may not" be truly independent to the extent that if one output is shorted, it may impact the operation of other outputs (due to lateral heating in the die).

7 Fault operation

of chip select if a valid DI byte was received. on one of the eight independent Outputs, occurred.

7.1 Low-side configured output fault operation

protection, selectable for each channel via SPI bus, is active). register is cleared will be ignored.

7.1.1 No latch mode

This diagnostic operating mode doesn't latch open load and short to GND faults. Table 11. Fault register definition Table 12. Fault logic definition

drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. 2. Short circuit to GND The diagnostic of short circuit to GND is detected only in OFF condition sensing the Drn1-8 output voltage. This fault is detected on the falling edge of the CS input if the power drain voltage is lower than the Vth_GND threshold. 3. Overcurrent The diagnostic of overcurrent is detected only in ON condition, if the switching OFF protection of the channel is enabled (default), sensing the current level of the output power transistor. If the output current has been above the short threshold Iovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. There are three possibilities to restart one output after the fault has occurred: – Automatically after a time Tres – On the rising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic '0' and then with a logic “1” in the following SPI cycle – On the rising edge (low to high transition) at the corresponding parallel input pin (only for Outputs 6-8). – If the switching OFF protection is not active the On phase overcurrent protection is a linear current limitation and no diagnosis is available. The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad diagnostic behavior when the falling edge of CS happens a short time after the falling edge of IN6-8 during the power MOS transient. Software filtering may be needed to ignore fault signals during Drn6-8 transient after falling edge of IN6-8.

7.1.2 Latch mode

This diagnostic operating mode latches all faults when they happen. 1. Open load The diagnostic of open load is detected only in OFF condition sensing the Drn1-8 output voltage. This fault is detected if the power drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt. An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. 2. Short circuit to GND The diagnostic of short circuit to GND is detected only in OFF condition sensing the Drn1-8 output voltage. This fault is detected if the power drain voltage is lower than the Vth_GND threshold for the filtering time Tfilt. 3. Overcurrent The diagnostic of overcurrent is detected only in ON condition, if the switching OFF protection of the channel is enabled (default), sensing the current level of the output power transistor. If the output current has been above the short threshold Iovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. If the switching OFF protection is not active the On

phase overcurrent protection is a linear current limitation and no diagnosis is available. There are three possibilities to restart one output after the fault has occurred: – Automatically after a time Tres – On the rising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic '0' and then with a logic “1” in the following SPI cycle – On the rising edge (low to high transition) at the corresponding parallel input pin (only for Outputs 6-8). If the power MOS transient, after a switching-off command, is longer than Tdel filtering time, a bad diagnostic behavior happens and software filtering may be needed.

7.2 High-side configured output fault operation

The diagnostic circuitry verifies for the high-side configured output the following condition: Normal operation, open load, short circuit to Vbat and overcurrent (only if the switching OFF protection, selectable for each channel via SPI bus, is active). The diagnostic circuitry operates in two different modes, selected for each channel by SPI: no latch mode and latch mode. The fault priority is overcurrent and then open load or short circuit to Vb, this means that if an overcurrent occurs the fault register is always overwritten and following open load or short to Vbat faults that happen before that the register is cleared will be ignored.

7.2.1 No latch mode

This diagnostic operating mode doesn't latch open load and short to Vbat faults. 1. Open load The diagnostic of open load is detected only in OFF condition sensing the Src1-8 output voltage. This fault is detected on the falling edge of the CS input if the power drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and Vth_GND. An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. 2. Short Circuit to Vb The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the Src1-8 output voltage. This fault is detected on the falling edge of the CS input if the power drain voltage is higher than the Vth_Vbat threshold. 3. Overcurrent The diagnostic of overcurrent is detected only in ON condition, if the switching OFF protection of the channel is enabled (default), sensing the current level of the output power transistor. If the output current has been above the short threshold Iovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. There are three possibilities to restart one output after the fault has occurred: – Automatically after a time Tres – On the rising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic '0' and then with a logic “1” in the following SPI cycle

– On the rising edge (low to high transition) at the corresponding parallel input pin (only for Outputs 6-8). – If the switching OFF protection is not active the On phase overcurrent protection is a linear current limitation and no diagnosis is available. The use of the IN6-8 pins for PWM control on the outputs 6-8 could generates bad diagnostic behavior when the falling edge of CS happens a short time after the falling edge of IN6-8 during the power MOS transient. Software filtering may be needed to ignore fault signals during Drn6-8 transient after falling edge of IN6-8.

7.2.2 Latch mode

This diagnostic operating mode latches all faults when they happen. 1. Open load The diagnostic of open load is detected only in OFF condition sensing the Src1-8 output voltage. This fault is detected if the power drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and Vth_GND for the filtering time Tfilt. An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. 2. Short Circuit to Vb The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the Src1-8 output voltage. This fault is detected if the power drain voltage is higher than the Vth_Vbat threshold for the filtering time Tfilt. 3. Overcurrent The diagnostic of overcurrent is detected only in ON condition, if the switching OFF protection of the channel is enabled (default), sensing the current level of the output power transistor. If the output current has been above the short threshold Iovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. There are three possibilities to restart one output after the fault has occurred: – Automatically after a time Tres – On the rising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic '0' and then with a logic “1” in the following SPI cycle – On the rising edge (low to high transition) at the corresponding parallel input pin (only for Outputs 6-8). If the switching OFF protection is not active the On phase overcurrent protection is a linear current limitation and no diagnosis is available. If the power MOS transient, after a switching-off command, is longer than Tdel filtering time, a bad diagnostic behavior happens and software filtering may be needed.

Figure 7. L9733 application schematic Figure 8. L9733 HVAC applicative examples

8 HIGH/LOW SIDE DRIVER

the motor housing, only 8 wires are needed to drive this arrangement. the motor housing, only 8 wires are needed to drive this arrangement. configured to high side build a quad half bridge. configured to high side build a quad half bridge. This can drive 3 DC-motors sequantially.

Figure 9. L9733 powertrain applicative examples

8 Application circuit

Figure 10. Optimized circuit layout to achieve proper EMI/ESD capability VBAT can improve furthermore EMI performance.

9 Package information

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 11. PowerSSO28 mechanical data and package dimensions

Table 13. Document revision history 13-Apr-2005 1 Initial release. 15-Jun-2006 2 Changed only look and feel. 08-Aug-2006 3 Modified Table 9: Bit command register definition on page 22. 28-May-2007 4 Changed the min. value of the CSlead parameter on the Table 8. 17-Jul-2007 5 Updated Table 6 and Table 7. Added new Figure 4. Changed the status from Preliminary data to Datasheet. 03-Aug-2007 6 Updated in Table 4 the ESD parameter. Added order codes in Table 1: Device summary. Updated Figure 6: SPI timing diagram. Updated Table 1: Device summary on page 1. Removed all references to the SO-28 package. condition and Section 2.1.4: Operation at load dump condition. Added Section 8: Application circuit. th” parameter in Table 6: DC characteristics. Updated Table 1: Device summary on page 1. 27-Jul-2010 10 Updated Table 1: Device summary on page 1. Updated Section 7: Fault operation on page 25. 19-Sep-2013 11 Updated Disclaimer.