L9654 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 59
Technical content
Datasheet sections
- 1 Block diagram and application schematic
- 1.1 Block diagram
- 1.2 Application schematic
- 2 Pin description
- 2.1 Thermal data
- 3 Electrical specification
- 3.1 Maximum ratings
- 3.2 Absolute maximum ratings
- 3.3 Electrical characteristics
- 3.3.1 DC characteristics
- 3.3.2 AC characteristics
- 4 Functional description
- 4.1 Overview
- 4.2 Power on reset (POR)
- 4.3 RESETB
- 4.4 MSG
- 4.5 IREF
- 4.6 Loss of ground
- 4.7 Deployment and reset
- 4.8 Serial peripheral interface (SPI)
- 4.8.1 Chip select (CS_A, CS_D, CS_S)
- 4.8.2 Serial clock (SCLK, SCLK_A)
- 4.8.3 Serial data output (MISO, MISO_A)
- 4.8.4 Serial data input (MOSI, MOSI_A)
- 4.9 Deployment drivers
- 4.9.1 Arming interface
- 4.10 DEPEN
- 4.10.1 Deployment driver diagnostic
- 4.10.2 Continuity diagnostic
- 4.10.3 Short to battery
Datasheet sections
- 4.14.12 Channel configuration registers (CCR1, CCR2, CCR3, CCR4)
- 4.14.13 SPI MISO bits layout for configuration report
- 5 Package information
- 6 Revision history
Features
4 deployment drivers sized to deliver 1.2 A (min) for 2 ms (min) and 1.75 A (min) for 1ms (min). Independently controlled high-side and low- side MOS for diagnosis Analog output available for resistance Squib short to ground, short to battery and MOS diagnostic available on SPI register Capability to deploy the squib with 1.2 A (min.) or 1.75 A under 35 V load-dump condition and the low-side MOS is shorted to ground Capability to deploy the squib with 1.2 A (min.) at 6.9 V V RES and 1.75 A at 12 V VRES. Interface with 2 satellite sensors Programmable independent current trip points for each satellite channel Support Manchester protocol for satellite sensors Supports for variable bit rate detection Independent current limit and fault timer shutdown protection for each satellite output Short to ground and short to battery detection and reporting for each satellite channel 5.5 MHz SPI interface Satellite message error detection Low voltage internal reset 2 kV ESD capability on all pins Package: 48 lead LQFP Technology: ST Proprietary BCD5s (0.57 μm)
Description
L9654 is intended to deploy up to 4 squibs and to interface up to 2 satellites. Squib drivers are sized to deploy 1.2 A (min.) for 2 ms (min.) during load dump and 1.75 A (min.) for 1 ms (min.) during load dump. Diagnostic of squib driver and squib resistance measurement is controlled by micro controllers. Satellite interfaces support Manchester decoder with variable bit rates. Table 1. Device summary
1 Block diagram and application schematic
1.1 Block diagram
Figure 1. Block diagram
1.2 Application schematic
Figure 2. Application schematic
2 Pin description
Table 2. Pin function
1 MISO_A Arming SPI data out Output Hi-Z
2 NC No connect - -
3 RESETB Reset pin Input Pullup
4 GND Signal ground (analog & digital) - -
5 VDD VDD supply voltage Input -
6 NC No connect - -
7 CS_A SPI chip select for arming interface Input Pulldown
8 CS_S SPI chip select for satellite interface Input Pulldown
9 CS_D SPI Chip select for deployment driver Input Pulldown
10 DEPEN Deployment enable Input Pulldown
11 MOSI SPI data in Input Hi-Z
14 MOSI_A Arming SPI data in Input Hi-Z
15 SCLK_A Arming SPI clock Input Hi-Z
16 SCLK SPI clock Input Hi-Z
17 GND2 Power ground for loop channel 2 - -
18 SQL2 Low-side driver output for channel 2 Output Pulldown
19 SQH2 High-side driver output for channel 2 Output Hi-Z
20 VRES2 Reserve voltage for loop channel 2 Input -
21 VRES3 Reserve voltage for loop channel 3 Input -
22 SQH3 High-side driver output for channel 3 Output Hi-Z
23 SQL3 Low-side driver output for channel 3 Output Pulldown
24 GND3 Power ground for loop channel 3 - -
25 TEST Test pin Input Pulldown
26 NC No connect - -
27 V8BUCK Supply Voltage for Satellite Interface and Resistance
28 NC No connect - -
29 ICH2 Current sense output for channel 2 Output Hi-Z
30 NC No connect - -
31 ICH1 Current sense output for channel 1 Output Hi-Z
32 NC No connect - -
33 IREF External current reference resistor Output -
2.1 Thermal data
Table 3. Thermal data
34 AOUT_GND Ground reference for AOUT - -
35 AOUT Analog output for loop diagnostics Output Hi-Z
36 NC No connect - -
37 GND1 Power ground for loop channel 1 - -
38 SQL1 Low-side driver output for channel 1 Output Pulldown
39 SQH1 High-side driver output for channel 1 Output Hi-Z
40 VRES1 Reserve voltage for loop channel 1 Input -
41 VRES0 Reserve voltage for loop channel 0 Input -
42 SQH0 High-side driver output for channel 0 Output Hi-Z
43 SQL0 Low-side driver output for channel 0 Output Pulldown
44 GND0 Power ground for loop channel 0 - -
45 NC No connect - -
46 MSG Message waiting Output Pulldown
47 MISO SPI data out Output Hi-Z
48 NC No connect - -
Table 2. Pin function (continued)
3 Electrical specification
3.1 Maximum ratings
The device may not operate properly if maximum operating condition is exceeded. Table 4. Maximum operating conditions
3.2 Absolute maximum ratings
permanent damage to the integrated circuit. Table 5. Absolute maximum ratings
3.3 Electrical characteristics
3.3.1 DC characteristics
Table 6. DC specification general
- V RST shall have a POR de-glitch timer.
- V RST L shall have no timer.
Table 7. DC specification: deployment drivers
- Not applicable during a diagnostic.
- Test conditions for load resistance measurements
Table 8. Satellite interface DC specifications
3.3.2 AC characteristics
Table 9. AC specification: deployment drivers
- Application Information; Test is not performed at high voltage.
Table 10. AC specifications: satellite
Functional description L9654
4 Functional description
4.1 Overview
L9654 is an integrated circuit to be used in air bag systems. Its main functions include deployment of air bags, switched-power sources to satellite sensors, diagnostics of SDM (Sensing Deployment Module) and arming inputs. L9654 supports 4 deployment loops, 2 satellite-sensor interfaces, and SPI arming inputs.
4.2 Power on reset (POR)
L9654 has a power on reset (POR) circuit, which monitors VDD voltage. When VDD voltage falls below VRST for longer than or equal to tPOR, all outputs are disabled and all internal registers are reset to their default condition. When VDD falls below VRST_L, all outputs are disabled and all internal registers are reset to their default condition. No delay filter shall be used along with VRST_L threshold. If VDD voltage falls below VRST for less than tPOR, operation shall not be interrupted. When VDD rises above VRST, the outputs are enabled. Before VDD reaches VRST, and during tPOR, none of the outputs turn on.
4.3 RESETB
RESETB pin is active low. The effects of RESETB are similar to those of a POR event, except during a deployment. When L9654 has a deployment in-progress, it ignores the RESETB signal. However, it shall shut itself down as soon as it detects a POR condition. When the deployment is completed and the RESETB signal is asserted, the device disables its outputs and resets its internal registers to their default states. A de-glitch timer is provided to the RESETB pin. The timer protects this pin against spurious glitches. UT48 neglects the RESETB signal if it is asserted for shorter than tGLITCH. RESETB has an internal pull-up in case of open circuit. This pin has a de-glitch timer.
4.4 MSG
MSG pin is used to reflect the FIFO status. Its polarity can be configured as well as the strategy of activation. Polling mode: Message pin shall be active as soon as one of the 4 FIFO is not empty and becomes inactive when all 4 FIFO are empty. A microcontroller can periodically monitor the status of line to understand if there are data received from satellite. Interrupt mode: Message pin shall be active as soon one of the 4 FIFO is not empty and becomes inactive when an SPI communication on CS_S interface starts. At the end of the SPI communication it shall be active if one of the 4 FIFO is not empty, otherwise it shall be kept inactive. A microcontroller can wait until an edge is present on the line and manage the data available in the FIFO.
L9654 Functional description
4.5 IREF
IREF pin shall be connected to VDD supply through a resistor, RIREF. When the device detects the resistor on IREF pin is larger than RIREF_H or smaller than RIREF_L, it goes in reset condition. All outputs are disabled and all internal registers are reset to their default conditions.
4.6 Loss of ground
When GND pin is disconnected from PC-board ground, L9654 goes in reset condition. All outputs are disabled and all internal registers are reset to their default conditions. A loss of power-ground (GND0 – GND3) pin/s disables the respective channel/s. In other words, the channel that loses its power ground connection is not able to deploy. The rest of the device is not affected by a loss of power-ground condition. AOUT_GND pin is a reference for AOUT pin. When AOUT_GND loses its connection the reset loses it as well.
4.7 Deployment and reset
The following conditions reset and terminate deployments: Power On Reset (POR) IREF resistance is larger than RIREF_H or smaller than RIREF_L Loss of ground condition on GND pin The following conditions are ignored when there is a deployment in-progress: RESETB Valid soft reset sequences
4.8 Serial peripheral interface (SPI)
The device contains a serial peripheral interface consisting of Serial Clock (SCLK, SCLK_A), Serial Data Out (MISO, MISO_A), Serial Data In (MOSI, MOSI_A), and two Chip Selects (CS_A, CS_D and CS_S). This device is configured as an SPI slave. The idle state of the communication, Serial Clock (SCLK, SCLK_A) should be in low state.
Figure 9. Arming SPI transmission
4.8.1 Chip select (CS_A, CS_D, CS_S)
Chip-select inputs select L9654 for serial transfers. CS_A is independent of CS_D and CS_S. sufficient time to reload the registers, chip-select pin shall remain negated for at least tCSN. out of tri-state, but no status bits are cleared and no control bits are changed). when an open circuit condition occurs. allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply.
4.8.2 Serial clock (SCLK, SCLK_A)
when the CS_A,CS_D,CS_S are in idle state (LOW).
4.8.3 Serial data output (MISO, MISO_A)
a. Only in daisy chain, it is needed to guarantee on SCLK_A a clock skew of 3ns maximum between any devices.
4.8.4 Serial data input (MOSI, MOSI_A)
MOSI/MOSI_A input takes data from the master processor while chip select is asserted. shall be the last bit of each word/byte received. voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply.
4.9 Deployment drivers
The on-chip deployment drivers are designed to deliver 1.2 A (mi.n) at 6.9 V VRES. resistance is 1.7. At the end of a deployment, a deploy success flag is asserted via SPI. turned on. SQH and SQL drivers are also turned on momentarily during a MOS diagnostic. condition and the deploy success flag timing. Figure 10. Deployment drivers diagram
has the control of its internal logic and that prevents an inadvertent turn-on of the drivers. regulation voltage. In this condition, all drivers are inactive. deployment condition can turn on the respective SQH and SQL drivers.
4.9.1 Arming interface
Arming interface has a dedicated 8-bit SPI interface. pulse stretch timer for the respective channel/s. except during a reset event. Figure 11. Deployment sequence command is sent before the timer for the previous command expired, the timer is refreshed. Sending a deployment-disable command terminates the pulse stretch timer operation. ONLY a timer operation started by a deployment-enable command can be terminated.
command does not affect the timer operation started by a valid deployment command. Figure 12. Deployment flow chart
- MOSI Register Mode: ignored. Next MISO: SPI fault response
shall resume their operations and respond to specific SPI commands. terminate the pulse stretch timer when it receives an arming command. Table 12. SPI transmission during a deployment
- SPI MISO sent in the next SPI transmission.
4.10 DEPEN
that is already in-progress. diagnostic even without the ability to turn on the MOS. It sets the proper SPI threshold bits. the processor can diagnose SPI deploy command bits with DEPEN negated. used for the processor to diagnose the arming signal. timer being started by an arming signal or an SPI deploy command.
4.10.1 Deployment driver diagnostic
diagram of deployment driver diagnostic. SRC and IBIAS) and current sink (ISINK, IPD_SQH) is turned on or off by an SPI command. current sink pulls down SQL pin during an open circuit condition. Figure 13. Deployment driver diagnostic diagram
4.10.2 Continuity diagnostic
voltage is below SBTH threshold and SQL voltage is above SGTH threshold.
Figure 14. Continuity diagnostic flow chart
4.10.3 Short to battery
4.10.4 Short to ground and open circuit
a short to ground or an open circuit condition.
4.10.5 Resistance measurement
aout = VDD/10 + Rsquib · Isrc · 10.
internal offset compensation. Figure 15. Resistance measurement flow chart
4.10.6 MOS diagnostics
MOS is not turned on and a fail MOS diagnostic is expected.
4.10.7 Low-side MOS diagnostic
If both conditions above are satisfied, execution of low-side driver diagnostic is performed. of the above conditions, the respective SPI status bit indicates that the condition is set. of the above conditions is considered as normal in a low-side MOS diagnostic. provided to protect against short-transients on SQH and SQL pins.
Figure 16. Low-side diagnostic flow chart
Functional description L9654
4.10.8 High-side MOS diagnostic
When L9654 receives an SPI command to initiate the high-side MOS diagnostic, the following conditions are verified before turning on the high-side MOS: VSQL greater than SGTH threshold voltage VSQH less than SBTH threshold voltage If both conditions above are satisfied, the high-side MOS diagnostic is executed. Otherwise, it is ignored and both bit D13 and bit D7 in SPI diagnostic are set. Upon detection of the following conditions, the high-side driver is turned off and the diagnostic, within the specified time, t PROP_DLY, is terminated VSQH greater than SBTH threshold voltage (VSQHx – VSQLx) greater than VI_TH VSQL less than SGTH threshold voltage The state of each comparator above is reported through SPI. When L9654 detects one of the above conditions, it sets the respective SPI status bit to indicate the condition. Any of the above conditions is considered as normal in a high-side MOS diagnostic. The high-side driver is turned off when tTIMEOUT is expired. A fault detection filter, tFLT_DLY, is provided to protect against short-transients on SQH and SQL pins.
4.10.9 Loss of ground
When any of the power grounds (GND0 – 7) are lost, no deployment can occur to the respective deployment channels. A loss of ground condition on one or several channels does not affect the operation of the remaining channels. When a loss of ground condition occurs, the source of the low-side MOS is floating. In this case, no current flows through the low-side driver. This condition is detected as a fault by a low-side MOS diagnostic. Also, the resistance measurement result is on the low end of the resistance range.
Figure 17. High-side driver diagnostic flow chart
4.11 Deployment driver SPI bit definition
L9654 response to the previous command is sent in the next valid CS_D. Table 13. Deployment driver SPI response
4.11.1 Deployment driver MOSI bit definition
Table 14. MOSI bit layout MOSI mode bits are defined as shown in the below table. Table 15. MOSI mode bits definition
4.11.2 Deployment driver register mode
Register mode message are defined here below. Table 16. MOSI register mode message definition
0 Read (default)
1 Write
0 Pulse Stretch Timer Period
1 Soft Reset Sequence
0 Deployment Condition: IDEPLOY_12A and
1 Deployment Condition: IDEPLOY_175A and
Odd parity check includes all 16 bits. “Don’t care” bit is included in the parity check as well. duration of the pulse stretch timer or to address the soft reset sequence. default state of this bit shall be ‘0’.
Bit D9 and bit D8 are used to set the period of pulse stretch timer. values default to ‘00’ after a POR event. Table 17. Pulse stretch timer table the sequence is broken, the processor is required to re-transmit the sequence. This soft reset function is available only to deployment drivers. POR event, except for MISO response. During a deployment, soft reset sequence is ignored.
4.11.3 Deployment driver command mode
Command Mode message is defined as shown below. Table 18. MOSI command mode message definition
0 Channel 7 Idle (default)
1 Deploy Channel 7
0 Channel 6 Idle (default)
1 Deploy Channel 6
Odd parity check includes all 16 bits. “Don’t care” bit is included in the parity check as well. the deployment or the pulse stretch timer for the respective channels.
4.11.4 Deployment driver diagnostic mode
Diagnostic Mode message are defined as shown here below.
0 Channel 5 Idle (default)
1 Deploy Channel 5
0 Channel 4 Idle (default)
1 Deploy Channel 4
0 Channel 3 Idle (default)
1 Deploy Channel 3
0 Channel 2 Idle (default)
1 Deploy Channel 2
1 Deploy Channel 1
0 Channel 0 Idle (default)
1 Deploy Channel 0
Table 18. MOSI command mode message definition (continued) Table 19. MOSI diagnostic mode message definition
0 Read Diagnostic Mode Response (default)
1 Write Diagnostic Mode Command
0 MOS Diagnostic Disable (default)
1 MOS Diagnostic Enable
0 LS MOS Diagnostic Enable
1 HS MOS Diagnostic Enable
Odd parity check includes all 16 bits. “Don’t care” bit is included in the parity check as well. transmission regardless of bit D12. measurement current (ISRC). Diagnostic bias current is used to run continuity tests, e.g. Otherwise, ISRC and ISINK are off. When bit D11 is set to ‘1’, MOS diagnostic is enabled. ignored. Bit D2 through bit D0 selects a specific channel, which is connected. The decoding scheme of this channel selection is shown ahead. to different channels. In this configuration, a short between loop diagnostic can run. voltage across SQH and SQL pins. AOUT is connected to the differential amplifier.
0 Diagnostic Current Disable (default)
1 Diagnostic Current Enable
0 Diagnostic Bias Current, IBIAS, Enable
1 Resistance Measurement Current, ISRC, Enable
0 AOUT Disable (default)
1 AOUT Enable
0 AOUT: Resistance Measurement (default)
1 AOUT: Calibration
Table 19. MOSI diagnostic mode message definition (continued)
AOUT shall be driven to the high-impedance state. Table 20. Channel selection decoding
1 X X Don't’ Care
4.11.5 Deployment driver monitor mode
Monitor Mode message is defined as shown in the following table. Table 21. MOSI monitor mode message definition
0 Report Deploy Success Flag (default)
1 Report Deployment OR Deploy Success Flag
Odd parity check includes all 16 bits. “Don’t care” bit is included in the parity check as well. ‘0’ before the deploy success flag is cleared. the state of these flags is not affected.
0 Keep Deploy Success Flag Channel 0 (default)
1 Clear Deploy Success Flag Channel 0
0 Keep Deploy Success Flag Channel 2 (default)
1 Clear Deploy Success Flag Channel 2
0 Keep Deploy Success Flag Channel 1 (default)
1 Clear Deploy Success Flag Channel 1
Table 21. MOSI monitor mode message definition (continued)
4.11.6 Deployment driver MISO bit definition
Table 22. MISO bit layout MISO mode bits are defined as below table. Table 23. MISO mode bits definition
4.11.7 Deployment driver register mode response
transmission. Register Mode Response is defined as shown in the following table. Table 24. MISO register mode response definition
0 Pulse Stretch Timer Duration
0 Deployment Condition: IDEPLOY_12A and tDEPLOY_2ms
1 Deployment Condition: IDEPLOY_175A and tDEPLOY_1ms
Bit D12 is used to reflect the status of MOSI Read/Write bit. Bit D11 is used to reflect the MOSI bit D11 in the previous command. for deployment condition bit in MOSI register mode message. Bit D9 and bit D8 are used to report the period of the pulse stretch timer. detected, RESETB is asserted, RIREF is out-of-range, or GND connection is lost. set to '1,' after the bit has been read. A soft reset sequence does not affect this bit. containing $0001 in the next SPI transmission.
4.12 MISO register mode response summary
transmission after each event or MOSI write. Table 25. MISO register mode response summary
4.12.1 Deployment driver command mode response
Command Mode response is defined as shown here after. Table 26. MISO command mode response definition
0 DEPEN Negated
1 DEPEN Asserted
0 ARM23 Negated
1 ARM23 Asserted
0 ARM01 Negated
1 ARM01 Asserted
DEPEN status flag (bit D12) indicates the state of DEPEN pin. most recent SPI command mode message.
4.12.2 Deployment driver diagnostic mode response
Diagnostic mode response is defined as shown in table. Table 27. MISO diagnostic mode response definition
0 SQH voltage below SBTH threshold
1 SQH voltage above SBTH threshold
0 MOS Diagnostic Completed
1 MOS Diagnostic In-progress
0 LS MOS Diagnostic selected
1 HS MOS Diagnostic selected
0 Diagnostic Current OFF
1 Diagnostic Current ON
0 Diagnostic Bias Current, IBIAS selected
1 Resistance Measurement Current, ISRC selected
0 SQL voltage above SGTH threshold
1 SQL voltage below SGTH threshold
0 Squib Current below VI_TH threshold
1 Squib Current above VI_TH threshold
comparator monitors the voltage on SQH pin. DEPEN status flag (bit D12) indicates the state of DEPEN pin. This bit shall be used in conjunction with bit D11. which diagnostic current is selected. diagnostic bias current or resistance measurement current is on or off. comparator monitors the voltage on SQL pin.
by AOUT or SBTH, SGTH, VI_TH comparators. monitors the voltage across SQH and SQL pins.
4.12.3 Deployment driver status response
Status response is defined as in the following table. Table 28. MISO status response definition
0 No Deployment Event: Channel 3
1 Deploy Status: Channel 3
0 No Deployment Event: Channel 0
1 Deploy Status: Channel 0
DEPEN status flag (bit D12) indicates the state of DEPEN pin. reported in D3 through bit D0.
4.12.4 Deployment driver SPI fault response
defined as shown in the following table. Table 29. MISO SPI fault response
0 Parity error or message error during a deployment(1)
- See Table 12 for the summary of SPI transmission during a deployment.
detected, bit D12 is asserted (F000h).
1 Incorrect number of clocks/bits
1 Invalid channel address in diagnostic command
4.13 Arming SPI bit definition
4.13.1 Arming MOSI_A bit definition
Arming MOSI_A is defined as shown in the table below. Table 30. Arming MOSI_A bit definition signal for the respective loop-pair. When device is in reset, all arming signals are disabled. complement bits, it ignores the arming command.
4.13.4 Arming MISO_A bit definition
Arming MISO_A is defined in the table below. Table 31. Arming MISO_A bit definition value of 0 indicates that arming signal is disabled for the respective loop-pair. The default state of these arming signals is ‘0’ (disabled).
4.14 Satellite sensor interface
The device provides four currents limited to 60mA each through outputs ICH1 and ICH2. communicated to an external microprocessor via SPI. Figure 18. Satellite interface block diagram
4.14.1 Current sensor
current is limited to 150mA maximum and includes a fault timer. the output under an open circuit condition. In case of loss of VCC all outputs remain off.
4.14.2 Manchester decoding
reverts to the minimum bit time of the selected range, and waits for idle. Figure 19. Manchester decoding
Figure 20. Manchester decoding using satellite protocol as an example time and the correct number of bits was received, the message is considered complete. communication errors (CRC/Parity).
4.14.3 Communication protocols
order to use any of these protocols. most significant bits in the data field sent by the sensor can identify these data types. Figure 21. "A" satellite protocol case of CRC error, the device sets a fault code via SPI. Figure 22. "B" satellite protocol
- The protocol consists of a
4.14.6 FIFO buffer
when the FIFO is flushed via SPI command.
4.14.7 Satellite continuity check
condition bit is reported via SPI.
4.14.8 Message waiting
pin is TTL level and is configurable to be either active high or active low signal. if there are no messages in any of the internal 2 FIFOs the pin is forced to inactive state.
4.14.9 Satellite serial data input (MOSI)
4.14.10 Satellite MOSI bits definition
Table 32. Satellite MOSI bits layout There is a total of 5 internal registers that are used to configure all of the satellite channels.
significant word and CH2 command is the Last word. Table 33. MOSI satellite interface registers map
0 MCR Master Configuration Register (CH1 Only)
1 CCR1 Channel Configuration Register for CH1
1 CCR2 Channel Configuration Register for CH2
second SPI word communicates with channel 2.
4.14.11 Satellite module configuration register (CH1 only)
reply with SPI message $E000. Table 34. Master configuration register definition (CH1 only)
0 CH2 "A" Protocol Mode (default)
1 CH2 "B" Protocol Mode
0 CH1 "A" Protocol Mode (default)
1 CH1 "B" Protocol Mode
0 MSG Output remains active when CS_S asserted (default)
1 MSG Output inactive when CS_S asserted
0 MSG Output Active High (default)
1 MSG Output Active Low
or even parity, which is determined by the setting of bit D12. parity; the selected setting applies to all channels operating in "B" protocol node. correctly, however it can be superseded with a CCR command.
4.14.12 Channel configuration registers (CCR1, CCR2, CCR3, CCR4)
required by the application. Please refer to the below Table 35 for bits definition. Table 35. Channel configuration register definition
0 Don’t Flush FIFO (Default)
1 Flush FIFO
0 Write to bits <D9-D0>, D12 and D13 only
0 Current Trip Point Hysteresis Disabled (default)
1 Current Trip Point Hysteresis Enabled
channel. The current ranges supported are given in Table 36. Table 36. Current ranges supported are given in following table decoder. D3 enables a hysteresis around the current threshold for added noise immunity. Table 37. Satellite/decoder control through bits <11:8> in the MCR register.
Table 38. "B" protocol configuration shall initialize to the default speed as it is shown in the below table. Table 39. Bit time selection to 00 by the IC and MISO bits <12:0> shall default to the content of the MCR register. Table 40. Mode select
device reports back the content of the MCR register. MISO layout when reporting configuration report is provided in previous figure. Table 41. SPI mode selects reply for satellite channels user can modify bits <D9-D0>, D12 and D13 only, all other CCR bits keep previous setting. D13, all other CCR bits keep previous setting. locations for the specified channel, all FIFO connect is lost in this case. Table 42. Satellite MISO bits definition Table 43. SPI MISO bits layout when reporting FIFO data
4.14.13 SPI MISO bits layout for configuration report
and then removed form FIFO on rising edge of CS_S and reported through MISO. Global and channels faults are encoded in the hexadecimal range between $001 to $01F. “Global faults” cover all satellite channels. “Channel Fault” covers only a particular channel. s for bits is even and to 0 if the total number of 1’s for bits is odd. Table 44. MISO Manchester message data definition
0 No FIFO Data has been lost
1 FIFO Data has been lost
Table 45. Status bits definition Table 46. Satellites fault codes definition supporting "A" protocol
fer data lost) flag shall be set. Table 47. Satellites fault codes definition supporting "B" protocol set to 1 by the IC when receiving sensor data. it occupies bits <7:0> bits 8, 9 and 10 are set to 000. sensors "A" based or "B" based to use the same fault codes.
5 Package information
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 23. LQFP48 mechanical data and package dimensions
6 Revision history
Table 48. Document revision history 03-Dec-2009 1 Initial release. 27-Sep-2013 2 Updated disclaimer. Document status promoted from preliminary data to production data. 12-Nov-2013 3 Document reformatted no content change.