L9634 STMICROELECTRONICS | Alldatasheet
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Technical content
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change wit hout notice.
1 FEATURES
AND THE LOW SIDE MOS SHORTED TO -1V.
2 DESCRIPTION
Figure 1. Package Table 1. Order Codes
Figure 2. Block Diagram
Figure 3. Pin Connection (Top view) Table 2. Pin Function
1 SQH0 High Side Driver Output for Channel 0 Out
2 SQL0 Low Side Driver Output for Channel 0 Out
3 GND0 Power Ground 0 -
4 ARMCLK ARM Serial Mode Clock Input In
5 ARMOUT ARM Serial Mode Data Output Out
6 ARMEN ARM Serial Mode Data Enable In
7 ARMIN ARM Serial Mode Data Input In
8 TEST Test Input Pin In
9 GND7 Power Ground 7 -
10 SQL7 Low Side Driver Output for Channel 7 Out
11 SQH7 High Side Driver Output for Channel 7 Out
12 VRES7 Reserve Voltage for Loop Channel 7 In
13 VRES6 Reserve Voltage for Loop Channel 6 In
14 SQH6 High Side Driver Output for Channel 6 Out
15 SQL6 Low Side Driver Output for Channel 6 Out
16 GND6 Power Ground 6 -
17 CS SPI Chip Select In
**Table 3. Absolute Maximum Ratings *)** *) Maximum ratings are absolute values: exceeding any one of these values may cause permanent damage to the integrated circuit. Table 4. Thermal Data
18 GND5 Power Ground 5 -
19 SQL5 Low Side Driver Output for Channel 5 Out
20 SQH5 High Side Driver Output for Channel 5 Out
21 VRES5 Reserve Voltage for Loop Channel 5 In
22 VRES4 Reserve Voltage for Loop Channel 4 In
23 SQH4 High Side Driver Output for Channel 4 Out
24 SQL4 Low Side Driver Output for Channel 4 Out
25 GND4 Power Ground 4 -
26 IREF External Current Reference Resistor Out
27 VDD VDD Supply Voltage In
28 MISO SPI Data Out Out
29 MOSI SPI Data In In
30 SCLK SPI Clock In
31 GND3 Power Ground 3 -
32 SQL3 Low Side Driver Output for Channel 3 Out
33 SQH3 High Side Driver Output for Channel 3 Out
34 VRES3 Reserve Voltage for Loop Channel 3 In
35 VRES2 Reserve Voltage for Loop Channel 2 In
36 SQH2 High Side Driver Output for Channel 2 Out
37 SQL2 Low Side Driver Output for Channel 2 Out
38 GND2 Power Ground 2 -
39 VRMEAS Supply Voltage for Resistance Measurement In
40 GND1 Power Ground 1 -
41 SQL1 Low Side Driver Output for Channel 1 Out
42 SQH1 High Side Driver Output for Channel 1 Out
43 VRES1 Reserve Voltage for Loop Channel 1 In
44 VRES0 Reserve Voltage for Loop Channel 0 In
Table 2. Pin Function (continued)
3 ELECTRICAL CHARACTERISTICS
Table 5. Electrical Characteristics
Table 5. Electrical Characteristics (continued)
- Not applicable during the diagnostic.
Figure 4. MOS Settling time and turn-on time 1
Figure 5. MOS Settling time and turn-on time 2
- Application information only; not tested.
- Time from Falling edge of CS until SPI “diagnostic” flag is set.
Notes: 1. Parameters t dis and tho is measured with no additional capacitive load beyond the normal test fixture capacitance on the MISO pin. tance on MISO is the worst case for output hold time. Figure 6. SPI Timing Diagram Table 6. SPI Timing (All SPI timing is performed with a 200pF load on MISO unless otherwise noted)
Table 7. Arming Serial Mode Timing Figure 7. Arming Serial Mode Timing
4 CIRCUIT DESCRIPTION
bag and diagnostics of the SDM (Sensing Deployment Module). The OSD supports 8 de-ployment loops.
- 8 deployment drivers sized to deliver 1.2A min for 2ms min at 40V max or 1.75A min for 4ms min at 21V max (current and time are internally limited while power supply is externally lim-ited).
- 10% accuracy for deployment current.
- 5% accuracy for deployment time.
- High side and Low side current limits programmable via SPI.
- Low-voltage internal reset
- 5.5MHz SPI Interface
- SPI Message Validation
- 4 discrete logic arming inputs
- High and low-side MOS tests
- Squib resistance measurement with 5% accuracy
- Short to -1V protection on all deployment loops (high and low side).
- Capability to deploy with 1.2A min under 40V load-dump condition and the low side MOS is shorted to -1V.
- Capability to deploy with 1.75A min under 21V condition and the low side MOS is shorted to -1V
- Capability to deploy with 1.75A min, when the high side MOS is shorted to 18V-battery and -1V ground difference.
- Capability to deploy the air bag with 1.2A min @ 6.9V VRES
- Deployment loops short to ground and short to battery detection
- Short between loops detection
- -40°C to +95°C ambient temperature
- Package: 44LD TQFP
- Technology: ST's proprietary BCD4 Process
4.1 Power On Reset
abled. When OSD is in reset, none of the outputs are momentarily turned on.
4.2 Deployment Drivers
grammable via SPI. The high side driver survives deployment condition 1 and 2 as defined here below. SQLx is shorted to ground (-1V) in these two conditions. Table 8. Deployment Survivability Conditions
The Low Side driver survives deployment condition 3 as defined above. Figure 6, and Figure 7. for the valid deployment condition and the "Deploy Command Success" timing. vertent turn-on of the drivers. provided to prevent these drivers from momentarily turning-on. turns on the respective SQH and SQL drivers.
4.3 Arming Inputs
nel/loop. Either ARMx signal or SPI deployment bit starts the pulse stretcher. Figure 8. Arming Serial Mode Diagram 5 for a deployment diagram initiated by a SPI deployment command. Figure 5 for a deployment diagram initiated by an ARM discrete signal. In serial mode, OSD latch the arm state for each channel from the shift register when ARMEN is negated.
Figure 11. Serial Mode: Deployment Sequence with Pulse Stretch Timer Enabled Figure 12. Serial Mode: Deployment Sequence with Pulse Stretch Timer Disabled
4.4 ARM01 / ARMIN
the input of Arming shift register. the first bit of each word received on ARMIN. The LSB is the last bit of each word received on ARMIN. proper operation with another devices using a 3.3V to 5.0V supply. DEPEN input is assumed to be active in this sequence.
Figure 13. Arming Shift Register
4.5 ARM23 / ARMEN
ages allowing proper operation with another devices using a 3.3V to 5.0V supply. bits from the shift register, and clear the shift register contents.
4.6 ARM45 / ARMCLK
operation with another devices using a 3.3V to 5.0V supply. negated, OSD ignores ARMCLK signal. munication contains (4n - 1) ARMCLK edges. Otherwise, OSD ignores the serial arming messages.
4.7 ARM67 / ARMOUT
eration with another devices using a 3.3V to 5.0V supply. bit of the nibble shifted onto ARMOUT. The LSB is the last bit shifted onto ARMOUT.
4.8 TEST / DEPEN (Deployment Enable)
diagnostic. DEPEN does not initiate a deployment nor terminate a deployment if it is already started. To enter a test mode, this pin has to be pulled higher than VIH_TEST.
4.9 Deployment Driver Diagnostics
fault condition is detected, the state machine asserts a fault bit, which serves as a flag to the processor.
4.10 Short Between Loops Diagnostic
ported via SPI. Refer to Figure 16 for Short Between Loops diagram.
- MOSI monitor mode message with bit D12 = '1,' bit D9 = '1,' and bit D8 = '1.'
- MOSI diagnostic mode message with bit D12 = '1' and bit D9 = '1.' The test terminates when OSD receives one of the following message:
- MOSI monitor mode message with bit D12 = '1,' bit D9 = '1,' and bit D8 = '0'
- MOSI diagnostic mode message with bit D12 = '1' and bit D9 = '0.'
- MOSI command mode with bit D7 through bit D0 = '0.' If the test is in progress, OSD will continue the test when any of the following messages is received:
- MOSI monitor mode, except the one with bit D12 = '1,' bit D9 = '1,' and bit D8 = '0'
- MOSI register mode
Figure 16. Short Between Loops Diagram
4.11 Short to Battery Diagnostic
Figure 17. Short-to-Battery Diagnostic Diagram
4.12 Open Circuit and Short to Ground Diagnostic
voltage is below the open circuit threshold, OCth. Figure 18. Open Circuit and Short to Ground Diagnostic Diagram for at least tFLT_DLY before OSD sets the respective fault bit. Table 9. Open Circuit / Short to Ground Fault Condition
4.13 Resistance Measurement
resistance measurement diagram.
00 I n v a l i d S t a t e
Figure 19. Resistance Measurement Diagram due to adjacent loops short to 40V or -1V.
4.14 MOS Diagnostic
mal condition, SQHx and SQLx are equal to VBIAS. and the respective MOS fault bit is set.
4.15 Low Side MOS Diagnostic
within the specified time, tPROP_DLY.
- VSQL is less than SGth threshold voltage
- (VSQHx - VSQLx) is greater than VI_TH
- VSQH is greater than SBth threshold voltage Any of the above conditions are considered as a normal operation. Upon detection any of these conditions, OSD does not set the low side driver fault bits. On a single channel, high-side and low-side MOS diagnostics is completed within t DETECT. A low-side MOS fault bit is only set when tDETECT is expired before any of the above conditions are detected. A fault detection filter, tFLT_DLY, is provided to protect against short-transients on SQH and SQL pins. See Figure 20 for MOS test diagram.
Figure 20. MOS Diagnostic Diagram
4.16 High Side MOS Diagnostic
within the specified time, tPROP_DLY.
- VSQH is greater than SBth threshold voltage
- (VSQHx - VSQLx) is greater than VI_TH
- VSQL is less than SGth threshold voltage Any of the above conditions are considered as a normal operation. Upon detection any of these conditions, OSD does not set the high side driver fault bits. On a single channel, high-side and low-side MOS diagnostics are completed within t DETECT. A high-side MOS fault bit is only set when tDETECT is expired before any of the above conditions are detected. A fault detection filter, tFLT_DLY, is provided to protect against short-transients on SQH and SQL pins. See Figure 20 for MOS test diagram.
4.17 Loss of Ground Diagnostic
ground reference, OSD will go in reset mode.
4.18 Serial Peripheral Interface (SPI)
Serial Data In (MOSI), and Chip Select (CS). This device is configured as an SPI slave. Figure 21. SPI Block Diagram
4.19 Chip Select (CS)
current filtered status data.
4.20 Serial Clock (SCLK)
compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply. When CS is asserted, both the SPI master and this device latch input data on the rising edge of SCLK. The SPI master typically shifts data out on the falling edge of SCLK, as does this device.
4.21 Serial Data Output (MISO)
OH(min) while the MISO pin is in a logic "1" state.
4.22 Serial Data Input (MOSI)
4.23 SPI Transmission
mands summarized in the below table. OSD response to the previous command is sent in the next valid CS. Table 10. OSD SPI Response
4.24 SPI Bit Definition - MOSI Bit
Figure 22. MOSI Bit Layout Table 11. MOSI Mode Bits Definition
4.25 Register Mode
Register mode message is defined as shown in table below. Table 12. MOSI Register Mode Message Definition specific register in OSD. This address-bit is defined as shown below. in the register mode response. register is determined by the address bits sent in the previous command.
1 Write Configuration Register
Table 13. Address-bit Definition
00011 S o f t R e s e t
Table 14. STATUS.FLT Configuration Register
1 Disable Fault Report on Channel 7
1 Disable Fault Report on Channel 6
1 Disable Fault Report on Channel 5
1 Disable Fault Report on Channel 4
1 Disable Fault Report on Channel 3
1 Disable Fault Report on Channel 2
1 Disable Fault Report on Channel 1
1 Disable Fault Report on Channel 0
Table 13. Address-bit Definition (continued)
4.27 Deployment Configuration Register 1
a write request to this register is inhibited. Table 15. Deployment Configuration Register 1 channel. Either a valid ARMx or a SPI deployment command is capable to start the pulse stretch timer. These bits set the timer duration according to table. These values are default to %00 after battery connect. Table 16. Pulse Stretch Timer
1 ARM Serial Mode
1 ARM67 Pulse Stretch Enable
1 ARM45 Pulse Stretch Enable
1 ARM23 Pulse Stretch Enable
1 ARM01 Pulse Stretch Enable
4.28 Deployment Configuration Register 2
deployment current for each loop. During a deployment event, a write request to this register is inhibited. The register is defined as shown in herebelow table. Table 17. Deployment Configuration Register 2
4.29 Soft Reset
The soft reset in OSD is achieved by writing $AA and $55 within two subsequent 16-bit SPI transmissions. if the sequence is not completed within two subsequent 16-bit SPI transmissions.
4.30 Diagnostic Fault Registers
These diagnostic fault registers contain the fault status for each of the channels. Each register is cleared immediately after a SPI reading on that particular register. Table 18. Diagnostic Fault Register: Channel 0 and 1
1 Channel 6/7 4ms Deployment Period
1 Channel 4/5 4ms Deployment Period
1 Channel 2/3 4ms Deployment Period
1 Channel 0/1 4ms Deployment Period
1 Fault Exists: Channel 1
1 Fault Exists: Channel 0
Table 19. Diagnostic Fault Register: Channel 2 and 3 Table 20. Diagnostic Fault Register: Channel 4 and 5 Table 21. Diagnostic Fault Register: Channel 2 and 3 low side MOS fault. The channel number is determined by the address bit in register mode command.
1 Fault Exists: Channel 3
1 Fault Exists: Channel 2
1 Fault Exists: Channel 5
1 Fault Exists: Channel 4
1 Fault Exists: Channel 7
1 Fault Exists: Channel 6
Table 22. Diagnostic Fault-bit Definition
4.31 Resistance Measurement Registers
fined as shown in the table. Table 23. ADC Resistance Measurement Register
101 L o w S i d e M O S F a u l t
4.32 Command Mode
Command Mode message is defined as shown in next table. Table 24. MOSI Command Mode Message Definition Odd parity check includes all 16 bits. "Don't care" bit is included in the parity check as well. ated it will not be terminated. During the deployment, OSD will ignore all commands. timer that is started by a deploy command that can be terminated by sending an idle command.
1 Deploy Channel 7
1 Deploy Channel 6
1 Deploy Channel 5
1 Deploy Channel 4
1 Deploy Channel 3
1 Deploy Channel 2
1 Deploy Channel 1
1 Deploy Channel 0
4.33 Diagnostic Mode
Diagnostic Mode message is defined as shown in table. Table 25. MOSI Diagnostic Mode Message Definition Odd parity check includes all 16 bits. "Don't care" bit is included in the parity check as well. cutes these tests based on the diagnostic flow chart, shown in Figure 15.
1 Run On-chip Diagnostic
1 Short Between Loops Test Enable
1 MOS T est Enable
1 Enable Channel 7 Diagnostic
1 Enable Channel 6 Diagnostic
1 Enable Channel 5 Diagnostic
1 Enable Channel 4 Diagnostic
1 Enable Channel 3 Diagnostic
1 Enable Channel 2 Diagnostic
1 Enable Channel 1 Diagnostic
1 Enable Channel 0 Diagnostic
4.34 Monitor Mode
Table 26. MOSI Monitor Mode Message Definition Odd parity check includes all 16 bits. "Don't care" bit is included in the parity check as well. When bit D12 is set to a '0,' OSD ignores all command bits, specified in bit D9 to bit D0. is set to '0,' OSD ignores bit D9 and bit D8. is cleared. Otherwise, OSD does not affect the state of these flags.
1 Write Commands
1 Modify Short Between Loops T est
1 Enable Short Between Loops Test
1 Clear Deploy Success Flag Channel 7
1 Clear Deploy Success Flag Channel 6
1 Clear Deploy Success Flag Channel 5
1 Clear Deploy Success Flag Channel 4
1 Clear Deploy Success Flag Channel 3
1 Clear Deploy Success Flag Channel 2
1 Clear Deploy Success Flag Channel 1
1 Clear Deploy Success Flag Channel 0
4.35 MISO Bit Definition
Figure 23. MISO Bit Layout Table 27. MISO Mode Bits Definition
4.36 Register Mode Response
Register Mode Response is defined as shown in table. Table 28. MISO Register Mode Response Definition "Diagnostic Fault Register Channel 0 and 1 table" and "ADC Resistance Measurement Register table".
4.37 Command Mode Response
Command Mode Response defined as shown below. Table 29. MISO Command Mode Response Definition DEPEN status flag indicates the state of DEPEN pin. flag is de/asserted as soon as the de-glitch timer is expired. of pulse stretch timer. These bits will be overwritten by the most recent SPI command mode message. When DEPEN is negated, a valid deploy command is ignored and deploy status flag is not set.
4.38 SPI Fault Response
mine the integrity of the MOSI command transmission.This response is defined as shown in table. Table 30. MISO SPI Fault Response
1 DEPEN Asserted
4.39 Status Response
Table 31. MISO Status Response Definition fault status on channel/s enabled in the STATUS.FLT configuration register. status of "short between loops" test. flag is de/asserted as soon as the de-glitch timer is expired.
1 Diagnostic Fault Exists
1 Diagnostic Complete / Not Started
1 Deploy Command Successful: Channel 7
1 Deploy Command Successful: Channel 6
1 Deploy Command Successful: Channel 5
1 Deploy Command Successful: Channel 4
1 Deploy Command Successful: Channel 3
1 Deploy Command Successful: Channel 2
1 Deploy Command Successful: Channel 1
1 Deploy Command Successful: Channel 0
Figure 24. TQFP44 (10x10x1.4mm) Mechanical Data & Package Dimensions
Table 32. Revision History
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publicati on are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectro nics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Ital y - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America L9634 Obsolete Product(s) - Obsolete Product(s)