L9341 STMICROELECTRONICS | Alldatasheet
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PWM CONTROLLED OUTPUT CURRENT SHORT CURRENT PROTECTION AND DI- AGNOSTIC INTEGRATED FLYBACK DIODE UNDERVOLTAGE SHUTDOWN OVERVOLTAGE AND UNDERVOLTAGE DI- AGNOSTIC OVERTEMPERATURE DIAGNOSTIC
DESCRIPTION
The L9341 is a monolithic integrated circuit real- ized in Multipower BCD-II mixed technology. The driver is intended for inductive loads in synchro- nous PWM applications, especially for valve driv- ers. The output voltage and current rise and fall slopes du/dt and di/dt are controlled. This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. March 1994 UNDERVOLTAGE SHUTDOWN DIAGNOSTIC DRIVER SHORT CURRENT PROTECTION CHANNEL 1 CHANNEL 4 CHANNEL 3 CHANNEL 2 V flyth Voffth COMP1 COMP2 I OSC SDO SDI SCLK RES1 SERIAL INTERFACE PWM CONTROLL BIAS RES2 REXT CS OUT3 OUT4 GND VS Vs I Is cc IOUT1 I I OUT2 OUT3 IOUT4 OSCC I GND C BAT D BAT Vcc C O1 C O2 C C OUT2 VCC outs OUT1 di / dt & du / dt CONTROL THERMAL FLAG 220nF 10nF 10nF 10nF 10nF 10uF R ext 12.4k 10nF Ω BLOCK & APPLICATION DIAGRAM Multiwatt 15 ORDERING NUMBERS: L9341V L9341H MULTIPOWER BCD TECHNOLOGY
Symbol Parameter Value Unit VCC VCC Voltage Range -0.3 to 6 V VS VS Voltage Range -0.3 to 24 V Vspmax VS Voltage Range for t≤ 400ms -2 to 40 V Vst Schaffner Transient Pulses on VS see note 1 V Vin Input Voltage Range for SDI; SCLK;CS;RES1;RES2 -0.3to V CC +0.3 Vout Output Voltage Range for all Outputs: Negative Positive – 0.3 intern. clamped to VS V V I out Output Current for all Outputs: Negative Positive A A for Transient with t < 10ms Negative Positive A A Schaffner Transient Pulses on Output see note 2 VESD ESD Voltage Capability (MIL 883 C) 1500 V THERMAL DATA Symbol Parameter Value Unit R th j-case Thermal Resistance Junction to Case 3 °C/W R th j-amb Thermal Resistance Junction to Ambient mounted on PC Board 35 °C/W Tsdh Thermal Hysteresis 20 °C Tsd Thermal Diagnostic T j> 150 °C Notes: 1.Schaffner transient specification: DIN 40839 test waveforms of the following type: 1, 2, 3a, 3b, 5 and 6. The pulses are applied to the application circuit according to fig. 3. 2.The maximum output current results from the Schaffner pulses specified in note 1. PIN CONNECTION (Top view) L9341
ELECTRICAL CHARACTERISTICS (Unless otherwise specified: 8V≤ VS ≤ 24V; 4.7V≤ VCC ≤ 5.3V; – 40 °C ≤ Tj≤ 150°C; IO ≤ 1A (note 3); IO ≤ 1.5A; Vsp =V S for t≤ 400ms; VOUTP =V OUT for t≤ 400ms; Rext= 12.4KΩ ± 1%). Symbol Parameter Test Condition Min. Typ. Max. Unit Iccq Vcc Quiescent Current All Outputs Off 1 3 mA Isq Vs Quiescent Current All Outputs Off 14 25 mA Vccu Vcc Undervoltage Threshold See Note 4 3 4 4.7 V Vccr Vcc Range for RES1 and RES2 Operation R on On Resistance I o =1 A T j= 125°C Tj=2 5°C 750 450 m Ω m Ω Io off Off State Output Current Outputs Off 1.4V≤ Vo ≤ Vs Voutp=V sp = 40V 2.5 4 mA mA Voutf Output Voltage During Flyback Io = 1A Output Off Tj=2 5°C Tj= 125°C Vs +1.3 Vs +1.1 V V Igndf Current to GND during Flyback (see note 5) Io = 1A Output Off Vs = 24V Vsp = 40V mA mA Ioutr Reverse Leakage Current V sp -V o = 40V 500 µA VinH High Input Level of SCLK, SDI, CS, RES1, RES2 0.7*Vcc Vcc+0.3 V VinL Low Input Level of SCLK, SDI, CS, RES1, RES2 – 0.3 0.3*Vcc V VREShys Hysteresis of Reset Inputs RES1, RES2 0.3 1 V IinRESH Input Current on RES1,RES2 RES i= H; -2V≤ Vsp ≤ 8V RES i=H ;8 V≤ Vsp ≤ 40V –1 0 µA µA Iin Input Current on SCLK,SDI,CS – 2V≤ Vsp ≤ 40V – 10 10 µA VSDOH High Level SDO Output Voltage ISDO = -1mA -2V≤ Vsp ≤ 40V 0.9*V cc Vcc V VSDOL Low Level SDO Output Voltage ISDO = 1mA -2V ≤ Vsp ≤ 40V 0 0.4 V ISDOZ SDO Tristate High-Z Leakage Current 0 ≤ VSDO ≤ Vcc –2 V≤ Vsp ≤ 40V –1 0 1 0 µA PWM duty PWM Duty Cycle 1/16 15/16 Kf Frequency Accuracy Constant See Note 6 0.93*K fn Kfn 1.07*Kfn Vflyth Flyback Diagnostic Comparator Threshold 40 ≥ Vsp ≥ 8V Vs ≤ 8V Vs –1 1.5 Vs – 0.4 V V Voffth Off State Diagnostic Comparator Threshold 1.5 2 V Ioutl Output Current Limitation Threshold see Note 7 1.5 2.5 A tdpo Delay Time PWM Signal to Out. 5 15 µs Sov Output Voltage Rise and Fall Slope | du/dt | (from 10 to 90% of Vo) Fig. 2 1.0 10 V/ µs Soc Output Current Rise and Fall Slope |di/dt| 0.1≤ Io≤ 1.5A (from 10 to 90% of Io) 25 125 mA/ µs Notes: 3.The mean value is Io = 1 T ∫ Io (t) dt T 4.The outputs are switced off for Vcc≤ Vccu. The logic is not reseted. For a reset, RES1 or RES2 must be used. 5.This current is measured in the GND - terminal when one single output is in flyback and consists of the supply current added to the value of the output current source and the leakage current of the flyback diode. This leakage current is less than 1% of the nominal flyback current. 6.The PWM frequency is defined by an external capacitor. The PWM oscillator frequency is: fpwm = fosc 32 withfosc = Kf C osc ⋅1A/V and kin=1 5⋅10-6; the range is: 300Hz≤ fpwm ≤ 3000Hz. The OSC Pin can be alternatively driven by an external TTL / CMOS signal. 7. For Iout≥ Ioutlan internal comparator switches the corresponding output off for the current PWM cycle. L9341
tclcl tchcl t ch tcl tclch tchch tsu th tdtclz toh tzch 15 14 0 015 CS Figure 4:SynchronousSerial Interface Protocol. fclock Clock Frequency min. DC max. 2MHz tch Width of Clock Input High Puls min. 200ns tcl Widh of Clock Input Low Puls min. 200ns tcicl Clock Low Before CS Low min. 200ns tchcl Clock High After CS Low min. 200ns tclch Clock Low Before CS High min. 200ns tchch Clock High After CS High min. 200ns tciz SDO Low-Z CS Low min. 0ns max. 400ns tzch SDO High-Z CS High max. 400ns tsu SDI Input Setup Time min. 80ns th SDI Input Hold Time min. 80ns td SDO Output Delay Time (CL = 50pF) max. 100ns toh SDO Output Hold Time min. 0ns L9341
Bit 3 - 0 PWM1 PWM2 PWM3 PWM4 OUTPUT 0000 15/16 15/16 15/16 15/16 OFF 0001 1/16 15/16 1/16 15/16 ON 0010 2/16 14/16 2/16 14/16 ON 0011 3/16 13/16 3/16 13/16 ON 0100 4/16 12/16 4/16 12/16 ON 0101 5/16 11/16 5/16 11/16 ON 0110 6/16 10/16 6/16 10/16 ON 0111 7/16 9/16 7/16 9/16 ON 1000 8/16 8/16 8/16 8/16 ON 1001 9/16 7/16 9/16 7/16 ON 1010 10/16 6/16 10/16 6/16 ON 1011 11/16 5/16 11/16 5/16 ON 1100 12/16 4/16 12/16 4/16 ON 1101 13/16 3/16 13/16 3/16 ON 1110 14/16 2/16 14/16 2/16 ON 1111 15/16 1/16 15/16 1/16 ON Figure 5:PWM Generation Function Table. Bit. Nr. Name Contents
0 P10 PWM Duty Cycle for Channel 1 / Bit 0: LSB
1 P11 PWM Duty Cycle for Channel 1 / Bit 1
2 P12 PWM Duty Cycle for Channel 1 / Bit 2
3 P13 PWM Duty Cycle for Channel 1 / Bit 3 : MSB
4 P20 PWM Duty Cycle for Channel 2 / Bit 0 : LSB
5 P21 PWM Duty Cycle for Channel 2 / Bit 1 :
6 P22 PWM Duty Cycle for Channel 2 / Bit 2 :
7 P23 PWM Duty Cycle for Channel 2 / Bit 3 : MSB
8 P30 PWM Duty Cycle for Channel 3 / Bit 0 : LSB
9 P31 PWM Duty Cycle for Channel 3 / Bit 1 :
10 P32 PWM Duty Cycle for Channel 3 / Bit 2 :
11 P33 PWM Duty Cycle for Channel 3 / Bit 3 : MSB
12 P40 PWM Duty Cycle for Channel 4 / Bit 0 : LSB
13 P41 PWM Duty Cycle for Channel 4 / Bit 1:
14 P42 PWM Duty Cycle for Channel 4 / Bit 2 :
15 P43 PWM Duty Cycle for Channel 4 / Bit 3 : MSB
Figure 6:PWM Information From Microcontroller to QLSD. L9341
Bit Nr. Name Contents
0 F11 COMP1 State at Positive Edge of PWM1 (0: V out1 >V flyth;1 :Vout1 <V flyth)
1 F12 COMP2 State at Negative Edge of PWM1 (1: V out1>V offth;0:V out1<V ofth)
2 F21 COMP1 State at Positive Edge of PWM2 (0: V out2 >V flyth;1 :Vout2 <V flyth)
3 F22 COMP2 State at Negative Edge of PWM2 (1: V out2>V ofth;0:V out2<V ofth)
4 F31 COMP1 State at Positive Edge of PWM3 (0: V out3 >V flyth;1 :Vout3 <V flyth)
5 F32 COMP2 State at Negative Edge of PWM3 (1: V out3>V offth;0:V out3<V ofth)
6 F41 COMP1 State at Positive Edge of PWM4 (0: V out4 >V flyth;1 :Vout4 <V flyth)
7 F42 COMP2 State at Negative Edge of PWM4 (1: V out4 > Voffth;0:V out4<V ofth)
8 RES1 Logic State of RES1 Input (0: RES1 = L ; 1: RES1 = H)
9 RES2 Logic State of RES2 Input (0: RES2 = L ; 1: RES2 = H)
10 TSDF Thermal Diagnostic Flag ( 0: Overtemperature ; 1:Normal )
11 C1 Current at Negative Edge of PWM1 ( 0: I out >Ioutl;1 :Iout<Ioutl)
12 C2 Current at Negative Edge of PWM2 ( 0: I out >Ioutl;1 :Iout<Ioutl)
13 C3 Current at Negative Edge of PWM3 ( 0: I out >Ioutl;1 :Iout<Ioutl)
14 C4 Current at Negative Edge of PWM4 ( 0: I out >Ioutl;1 :Iout<Ioutl)
15 1 Framing Information (always 1) Figure 7:Diagnostic Information from QLSD to Microcontroller. PWM V OUT PWM V OUT ID tC tV dPO PWMON t t min Sample point COMP2 Sample point COMP1 dPOt tV PWMOFFt min Sample point COMP2 Sample point COMP1 Fig.1 Fig.2 Figure 8. Fig. A Fig. B Note: For safty diagnostic take notice of the following conditions: tPWMON ≥ tdPOMAX +tC +tV (see Fig. A) t C = ID SOCMIN tV = Voutfmax SOVMIN tPWMOF F ≥ tdPOMAX +tV (see Fig. B) L9341
The U511 is a PWM quad low side driver for in- ductive loads. The duty cycle of the internal gen- erated PWM signal is set by a microcontroller via a serial interface for each output. An output slope limitation for both dv/dt and di /dt is implemented to reduce RFI. The PWM generation is realized avoiding a simultaneous output switching. As a result, di/dt becomes smaller. Integrated flyback diodes clamp the output voltage during the fly- back phase of the low side switches. The driver is protected against short circuit. An undervoltageshutdown circuit switches off all out- puts if V cc is less then Vccu. Below the shutdown voltage all outputs remain in off state regardless of the input state. After each malfunction which resets the driver, only the serial link interface can reactivate the normal function. In case of overcur- rent (I out =Iout1), an internal comparator switches the output off. The overcurrent information can be read via the serial link for each driver separately at the negative edge of the corresponding PWM signal. The interface to the microcontroller is realized with a 16 bit synchronous serial peripheral inter- face (SPI). If CS is switched low, the serial link becomes active and SDO goes to low impedance. At the rising edge of the SCLK signal, one of the 16 bit of data stored in a shift register appear se- quencely at SDO. These data contain the 8 error flags, the status of thermal diagnostic flag and the external reset sources RES1, RES2 and the over- current flgs c1...c4. The last bit is framing infor- mation (see fig. 7). At each falling edge of SCLK, one of the 16 bits of data sent by the microcon- troller is transferred via the SDI input to the driver. These data contain the duty-cycle information for the internal PWM generation (4 times 4 bit). On the rising edge of CS the previously stored in- formation is transferred to the circuits. SDO be- come now high impedance and SDI is inactive. The serial interface of the QLSD is cascadable with the serial link interface of another QLSD, thus obtaining a 32 bit serial link information wich can control eight inductive loads. For a safety data transfer the takeover of data bits is only real- ized when the number of SCLK - clocks is n x 16 (n≥ 1). The PWM duty cycle is set by 4 bit for each out- put independently via the serial link. If all four bits for an output are zero, the output is turned off, but the error diagnosis will work correctly (see fig. 5 and 6). The PWM frequency is defined by an ex- ternal capacitor on the OSC pin. Rext defines through the reference current the output current slope, the diagnostic current sink and the internal oscillator frequency (together with C osc). For error diagnosis the voltage on the output is measured during the on and off state of the par- ticular output driver. Upon the rising edge of the PWM signal (at this moment the power output is off and will be switched on) the status of COMP1 is stored into an internal latch. On the falling edge of the PWM signal ( the power output is on and will be switched off) the status of COMP2 is stored into another internal latch. This information can be read via the serial link for each output driver separately (see fig. 7). The thermal diagnostic switch the thermal flag to 0 in case of overtemperature T≥ T sd.I tw i l lb e switched to 1 with the hysteresis Tsdth in case of T<T sd -Tsdh. To avoid male functions due to extensive noise or spikes at the supply pins VCC ,V S and Rext must be blocked externally via capacitors. L9341
MULTIWATT15 PACKAGE MECHANICAL DATA DIM. mm inch A 5 0.197 B 2.65 0.104 C 1.6 0.063 D 1 0.039 E 0.49 0.55 0.019 0.022 F 0.66 0.75 0.026 0.030 H1 19.6 0.772 H2 20.2 0.795 L2 17.65 18.1 0.695 0.713 L7 2.65 2.9 0.104 0.114 S 1.9 2.6 0.075 0.102 S1 1.9 2.6 0.075 0.102 Dia1 3.65 3.85 0.144 0.152 L9341
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men- tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. L9341