L9305_V01 STM | Alldatasheet
Document overview
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- PDF pages: 107
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pins description
- 3 Product Characteristics
- 3.1 Absolute maximum ratings
- 3.2 Latchup trials
- 3.3 ESD performance
- 3.4 Temperature range
- 4 Input / Output
- 4.1 Reset (RESn)
- 4.2 Enable (EN_DR)
- 4.3 Channel inputs (INx/NDISx)
- 4.4 Fault (FAULTn)
- 4.5 SPI communications (CS, SCLK, MOSI & MISO)
- 4.6 Input / output electrical specifications
- 5 Power supply
- 5.1 Overview
- 5.2 Battery supply (VBATP)
- 5.3 Load supplies (VSOL1, VSOL2, VSOL3 & VSOL4)
- 5.4 Analog and digital supply (VDD)
- 5.5 I/O supply (VDDIO)
- 5.6 Power-On reset
- 5.7 GND (GNDD, GNDA, GND_SOLx)
- 5.8 Charge pump
- 5.9 Startup & power down sequence
- 5.10 Power supply electrical specifications
- 6 Current control drivers
- 6.1 Hardware current control
- 6.1.1 Current set point programming
- 6.1.2 PWM switching period programming
- 6.1.3 Current control loop configuration
- 6.1.4 Fixed frequency control
- 6.1.5 Variable frequency control
- 6.1.6 Chopper offset compensation of current sense amplifier
- 6.1.7 Staggered channel activation
Features
- AEC-Q100 qualified
- 4-channel independent LSD/HSD current controlled drivers – Integrated current sense path – Current accuracy (in normal range) ◦ ± 5 mA in 0 to 0.5 A range ◦ ± 1% in 0.5 A to 1.5 A range – Current accuracy (in extended range) ◦ ± 15 mA in 0 to 0.3 A range ◦ ± 5% in 0.3 A to 0.5 A range ◦ ± 4% in 0.5 A to 2 A range – Max driver RDSON 375 mΩ @ 175 °C – 13-bit current set-point resolution – Variable and fixed frequency current control – Programmable dither function – Selectable driver slew rate control
- Safety features – High side fail safe ENABLE switch pre-driver with VDS monitoring – Redundant safe enable path – Advanced diagnosis and monitoring using BIST – Temperature sensor and monitoring – Redundant current sensing for all channels – Calibration & configuration memory including CRC – Secure serial communications using address feedback, 5-bit CRC, frame counter & long/short frame detection – Register verification
- 32-bit SPI communications with 5-bit CRC message verification
- Package options: PWSSO36, TQFP48
- Full ISO26262 compliant, ASIL-D systems ready
Description
The L9305 is a configurable, monolithic solenoid driver IC designed for the control of linear solenoids for automatic transmission, electronic stability control, and active suspension applications. The four channels can be configured as either low side or high side drivers in any combination. The device includes the power transistor, recirculation transistor and current sensing for both the power and recirculation transistor. This architecture guarantees redundancy of the current measurement for each channel. The regulated current is programmable in the range of 0-1.5 A (normal range), with a resolution of 0.25 mA, or 0-2 A (extended range), with a resolution of 0.33 mA. The user can superimpose configurable dither modulation over the set point current. GADG0203181458PS TQFP48 exposed pad down (7x7x1 mm) GAPGPS00337 PowerSSO36 exposed pad down Product status link L9305 Product summary Order code L9305EP Package PowerSSO36 Packing Tube Order code L9305EP-TR Package PowerSSO36 Packing Tape and reel Order code L9305QFP Packing Tray Order code L9305QFP-TR Packing Tape and reel Automotive 4-channel valve driver L9305 Datasheet DS12774 - Rev 10 - June 2024 For further information contact your local STMicroelectronics sales office.
A 32-bit CRC protected SPI interface is used for configuration and control of all channels and provides status feedback of all diagnostic functions. An active low reset input, RESN, is used to disable all channels and resets internal registers to their default values. A safe enable path is provided through the EN_DR pin and the integrated Fail Safe Pre-driver. An isolated redundant safety switch-off path ensures that critical internal faults disable the fail safe pre-driver. An active high enable pin, EN_DR, is used to enable or disable the operation of all channels. When the EN_DR pin is low, all channels are disabled. A fault output pin is provided and can be used to generate an external interrupt to the microcontroller whenever a fault is detected. The user can map specific faults to the FAULTn pin based on their specific system requirements. L9305 DS12774 - Rev 10 page 2/107
1 Block diagram
Figure 1. Block diagram
Figure 2. PWSSO36 application schematic
Figure 3. TQFP48 application schematic
2 Pins description
Figure 4. PowerSSO-36 pinout diagram Figure 5. TQFP48 pinout diagram
Table 1. PowerSSO-36 and TQFP48 pins list 1 10 GND_SOL1 Channel 1 Ground: Ground connection for channel 1 power stage. 18 27 GND_SOL2 Channel 2 Ground: Ground connection for channel 2 power stage. 19 34 GND_SOL3 Channel 3 Ground: Ground connection for channel 3 power stage. 26 41 FS_S0 Fail Safe Source: to be connected to external FET Source used as FS.
32 47 VC1 Charge Pump: External Capacitor connection 33 48 VBATP Supply Voltage: Connected to Protected Battery Voltage (reverse protection diode and filter against EMC) 34 1 VS_SOL0 Channel 0 Supply Voltage: Connect to Switched Battery Voltage with reverse protection diode 35 2 LOAD_SOL0 Channel 0 Output 36 3 GND_SOL0 Channel 0 Ground: Ground connection for channel 0 power stage. – – – Available on TQFP-48 version only – 9 FS_G_1 Fail Safe Gate: Gate command for external FET Drain used as FS – 8 FS_S_1 Fail Safe Source: to be connected to external FET Source used as FS. VDS monitor – 7 FS_D_1 Fail Safe Drain: to be connected to external FET Drain used as FS. VDS monitor – 6 NC Not Used: To be connected to GND. – 5 NC Not Used: To be connected to GND. – 4 NC Not Used: To be connected to GND. – 28 FS_G2 Fail Safe Gate: Gate command for external FET Drain used as FS – 29 FS_S2 Fail Safe Source: to be connected to external FET Source used as FS. VDS monitor – 30 FS_D2 Fail Safe Drain: to be connected to external FET Drain used as FS. VDS monitor – 31 FS_D3 Fail Safe Drain: to be connected to external FET Drain used as FS. VDS monitor – 32 FS_S3 Fail Safe Source: to be connected to external FET Source used as FS. VDS monitor – 33 FS_G_3 Fail Safe Gate: Gate command for external FET Drain used as FS L9305 Pins description DS12774 - Rev 10 page 8/107
3 Product Characteristics
3.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
- 35V AMR over life-time, 40V for ISO-pulse transients (as defined in ISO7637-2 standard).
- biased condition, -0.3V for unbiased conditions/sleep mode.
3.2 Latchup trials
3.3 ESD performance
Table 3. ESD Performance
3.4 Temperature range
Table 4. Device operating temperature
- 175°C are allowed for limited time. Eventual Mission profiles with passive lifetime temperature >150°C have to be evaluated
by ST to confirm that product qualification is able to cover the required conditions. correlation with ATE tests at reduced temperature and adjusted limits (if needed).
4 Input / Output
4.1 Reset (RESn)
the pin is open. RESn pin status is echoed in each SPI frame.
4.2 Enable (EN_DR)
can be connected to a general purpose output pin of the microcontroller or to an alternative safety circuit. drivers can be controlled through the Fail Safe Configuration Register.
4.3 Channel inputs (INx/NDISx)
when low output control is enabled. low side configurations are explained in Section 6: Current control drivers.
4.4 Fault (FAULTn)
The device sets the FAULTn pin low upon detecting internal and external faults and while the device is in reset. Table 5. Global and external supply fault pin error masking
Table 6. Solenoid channel and fail safe fault pin error masking
4.5 SPI communications (CS, SCLK, MOSI & MISO)
The CS, SCLK, MOSI & MISO pins provide serial communications between the device and the microcontroller. Please see Section 9: SPI for details on SPI features, device register functions and electrical characteristics.
4.6 Input / output electrical specifications
Table 7. Digital input/output electrical performance
5 Power supply
5.1 Overview
voltage source for the high side integrated valve drivers and fail safe pre-drivers.
5.2 Battery supply (VBATP)
summarizes the functional ranges dependent on battery supply voltage. Table 8. VBATP electrical performance
- Device is capable of full functional operation; VBATP must be reversed battery protected
- Device is capable of full functional operation at Ta ≤ 50 °C with possible degradation of electrical parameters linked to
operation and input pins will withstand voltage and current defined in Absolute ratings regardless of battery voltage range.
- Ta ≤ 50 °C, duration less than 500 ms. There will be no damage to the device, Solenoid channels and Fail Safe switch will
voltage returns to normal operating voltage range.
- Device is capable of full functional operation until charge pump is out of under voltage condition with possible degradation of
operation will resume without operator intervention when battery voltage returns to normal operating voltage range.
5.3 Load supplies (VSOL1, VSOL2, VSOL3 & VSOL4)
5.4 Analog and digital supply (VDD)
The VDD pin provides the source voltage for all internal analog (V3V3A) and digital (V3V3D) circuits. An internal start-up circuit connected to VDD initializes the internal regulators (V3V3A & V3V3D) once VDD reaches VDD_UV threshold. V3V3A & V3V3D regulators are monitored for internal power on reset control (POR). VDD input voltage is diagnosed for over and under voltage conditions. The status of this diagnostic is readable by SPI. Please see Section 8.1.1: VDD over and under voltage diagnostics.
5.5 I/O supply (VDDIO)
VDDIO is the supply for all pins that interface with the external microcontroller. This pin must be connected to a supply with the same voltage used by the microcontroller I/O, 3.3 V or 5.0 V. There is no monitoring function associated with VDDIO.
5.6 Power-On reset
An internal power on reset circuit holds the device in a reset state if VDD goes below the under voltage threshold. The power on reset is released once VDD is within normal operating range for the specified reset filter time TPOR. The SPI interface can be accessed after the power on reset time. The fault bit “POR_flag” in the SERVFLT1 register is set, when the device exits the reset state. This bit is cleared automatically, whenever the SERVFLT1 register is accessed. Also RES_echo in PINSTATUS register is set, when the device exits the reset state in case of Power-On reset event, despite the state of RESn pin. The microcontroller can use these bits to determine if an internal or external reset has occurred. A power on reset (POR) can also occur if any of the internal bandgap regulators or internal analog & digital regulators are diagnosed as over or under voltage. Additional details on these and VDD monitoring can be found
5.7 GND (GNDD, GNDA, GND_SOLx)
The L9305 has two low power ground connections, GNDD and GNDA. These connections are for internal analog and digital control circuits. Exposed pad is connected to substrate and to GNDA. GNDD and GNDA are connected through a pair of anti-parallel ESD diodes. The device has 4 power ground connections, GND_SOL0, GND_SOL1, GND_SOL2 and GND_SOL3. All ground pins have open circuit detection. Additional details on ground loss detection are shown in Section 8.1.5: GND loss detection .
5.8 Charge pump
To effectively bias the high side solenoid drivers and fail safe switch, a charge pump is used to drive the gate voltage above VBATP. The device uses a common charge pump for all channels and is referred to the battery voltage supply connected to the VBATP pin. The charge pump output voltage is present at the VCP pin. The charge pump switching frequency is nominally 470 kHz and its internal control loop reduces emissions by pulse skipping once the targeted operating voltage is reached. The charge pump circuit requires three external capacitors. A “Tank” capacitor with a recommended value of 220 nF must be connected between the VCP pin and the VBATP pin. Two pump capacitors with recommended values of 68 nF must be connected between the VCP1 and VCP2 pins and also between the VCP3 and VCP4 pins. A built-in monitoring circuit checks if the charge pump output voltage is sufficient to control the high side valve driver. Additional details for charge pump voltage monitoring are shown in Section 8.1.3: VCP supply under voltage. The charge pump voltage is also used as parallel supply to the VDD supply for internal references to avoid ASIC reset at low VDD input. L9305 Power supply DS12774 - Rev 10 page 15/107
Figure 6. Charge pump mechanization
5.9 Startup & power down sequence
VDD_UV threshold. A detailed list of these monitoring functions is summarized in Section 8: Safety features . registers maintain RESET default states until both POR is set high and RESn is set by the user. Figure 7. Startup procedure example VBATP voltage levels to perform the power down sequence.
5.10 Power supply electrical specifications
Table 9. Power supply electrical performance
6 Current control drivers
recirculates load current. Configuration examples are shown in Figure 8 and Section 6: Current control drivers. device defaults to low side configuration. Figure 8. HS driver (left) and LS driver (right) configuration Section 8.4.4 for more details.
- Hardware current control – Current Set Point and Switching frequency are programmed through SPI registers – Device automatically adjusts the PWM Duty cycle to maintain the programmed load current
- Software current control – Current Set Point and Switching frequency are managed directly by the microcontroller – L9305 provides average current feedback through SPI and acts only as load driver Current control configuration and setup are programmed through the SPI interface. Configuration registers (Channel_x. CONFIGURATION 1 and Channel_x.CONFIGURATION2) can only be modified when the channel is not enabled (SOLENDR).
6.1 Hardware current control
select driver operating state, therefore the table below shows only two bits.
Table 10. Solenoid driver status in hardware mode PWM Mode: Output drivers are actively regulating load current as programmed, off state diagnostics are disabled. Figure 9. Hardware control configuration The device can synchronize channel actuation by enabling all channels with a single SPI write operation. Stagger Enable D[0] bit in SERVENA register.
6.1.1 Current set point programming
regulated current. Below is a brief summary for using HILOAD to select current range and resolution.
- HILOAD = 0 → Normal current mode - Single bit resolution = 0.25 [mA] - Max Avg. Current 1.5 [A]. Tar g et Av er ag eCu r ren t = S etp o in t 12 : 0 * 0.25 m A
- HILOAD = 1 → High current mode - Single bit resolution = 0.33 [mA] - Max Avg. Current 2.0 [A]. Tar g et Av er ag eCu r ren t = S etp o in t 12 : 0 * 0.33 m A The maximum guaranteed ripple current for the device’s specified accuracy is 0.5 [A] peak to peak for HILOAD=0 and 0.66 [A] peak to peak for HILOAD=1, so that the max load current for correct current control is
- 1500 mA + 250 mA = 1750 mA for HILOAD = 0
- 2000 mA + 330 mA = 2330 mA for HILOAD = 1 If the channel is enabled and programmed with 0x0000h current set point, the power output is forced with duty cycle 0 (recirculation path fully on) and the current measurement is disabled; set point codes higher than 0x1770h are reserved for calibration and offset compensation purposes: in case such codes are selected, the accuracy is not guaranteed. When CHx.SETPOINT=0000 and channel x is controlled Hardware mode (CONFIGURATION1.D[2]=0), then current measurement is disabled and AVGCUR always returns all ‘0’, even if channel x is driven full-on.
6.1.2 PWM switching period programming
Table 11. PWM period and Frequency Programming Normal Period/Frequency range.
6.1.3 Current control loop configuration
operation through register Channelx_CTRLCFG, bit D[11]. control algorithm and a Proportional-Integral (PI) processing circuit with ramp-compare control the duty cycle. duty cycle. The actual PWM period may differ from the target PWM period, especially during transients.
6.1.4 Fixed frequency control
PROPORTIONAL and INTEGRAL signals and compares the result with ramp generator. Figure 10. Fixed frequency algorithm exceeds the max. and min. levels of the RAMP signal. This allows fastest loop transient response.
Figure 11. Fixed frequency signals
- Switch OFF point (1): the PI signal crosses the RAMP signal from high to low, the output driver is switched off and the load CURRENT reaches its maximum peak value.
- Switch ON point (2): every clock based TPWM periods, the RAMP signal resets and the output driver is switched on and the load current reaches its minimum peak value. To optimize current control capability, the user must properly select KP and KI amplitude settings (Channel_x.KGAINS) for each application.
- KP: parameter controls the amplitude of the Proportional signal and is calculated as: KP = 2 KP _ s el
- KI: parameter controls the amplitude of the Integral signal and is calculated as: KI = 2 K I s el
6.1.5 Variable frequency control
frequency integral (F_I) output signal.
- Switch OFF point: the INTEGRAL signal crosses the F_I signal from high to low, the output driver is switched off and the load CURRENT reaches its maximum peak value.
- Switch ON point: the INTEGRAL signal crosses the zero level signal from low to high, the output driver is switched ON, and the load CURRENT reaches its minimum peak value. The variable frequency control provides a transient mode for optimization of the transient condition behavior. It eliminates in this way current over/undershoot and allows the fastest reaching of the final frequency. The transient mode is entered in case of a change of current set point (Set Point Change) while the Auto Limit control bit is set. The transient mode is also entered in case the PWM period is longer than a threshold (Long Period Detection). The 2-bit control input Transition Time (D[15:14] in CTRLCFG register) selects the Long Period Detection threshold. L9305 Current control drivers DS12774 - Rev 10 page 22/107
Figure 12. Variable frequency algorithm NEGINTLIM are available for optimized positive and negative integrator limits. to its final value when exiting from transient mode.
- KI (Channel_x.KGAINS)
- KFI (Channel_x.KFREQCTRL)
- POSINTLIM & NEGINTLIM (Channel_x.INTGLIM)
- Auto Limit (Channel_x.SETPOINT)
- Transition Time (Channel_x.CTRLCFG)
- Fint_Start (Channel_x.KFREQCTRL) Programming values can be selected considering the following:
- KI: Integral portion of the loop gain. It can be calculated as KI = 2 K I s el
- KFI: Integral portion of the frequency control loop gain. It can be calculated as KF I = 2 KF I s el
- POSINTLIM: Positive Integrator Saturation Limit. It can be calculated as POS I NTL I M = 2 PO SI NTL I M s el − 1
- NEGINTLIM: Negative Integrator Saturation Limit. It can be calculated as NE G I NTL I M = − 2 N EG I NTL I M s el − 1
- AUTO_LIMIT: – If AUTOL_LIMIT_SEL = 0 → Transient mode is insensitive to changes of Current Set Point – If AUTOL_LIMIT_SEL = 1 → Any change in the current set point activates the transient mode
- FINIT_START: – If FINIT_START_SEL = 0 → F I NI T ST ART = 0 – If FINIT_START_SEL >0 → F I NI T ST ART = NE G I NTL I M *2 F I NI TS T A RT s el − 7 L9305 Current control drivers DS12774 - Rev 10 page 23/107
- TRANSITION TIME: Too long PWM period detection: if the current PWM time exceeds this threshold, the controller enters the transient state. It can be programmed as follows: – If TRANSITION TIME = 0 → TR ANS TI ME = 2,5* T PWM – If TRANSITION TIME = 1 → TR ANS TI ME = 4,5* T PWM – If TRANSITION TIME = 2 → TR ANS TI ME = 8,5* T PWM – If TRANSITION TIME = 3 → TR ANS TI ME = 16,5 * T PW M
6.1.6 Chopper offset compensation of current sense amplifier
This function cancels the input offset of the current sense amplifier by converting the DC input offset voltage to an AC noise at the chopper frequency. Function is normally enabled and can be disabled by the user via SPI register (OFS_CMP_DIS D[14] in Channel_x.CONFIGURATION1 register).
6.1.7 Staggered channel activation
Staggered channel operation is enabled by the user through the SPI Service Enable register, SERVENA (Stagger Enable bit D[0]). When staggered operation is enabled and the targeted regulated current is achieved, the PWM switch-on points is staggered per the following sequence:
- Channel 0 → 0° phase advance; reference channel
- Channel 1 → 90° phase advance
- Channel 2 → 180° phase advance
- Channel 3 → 270° phase advance This function is specific to fixed frequency current control and is disabled in variable frequency mode.
6.1.8 Parallel mode
The 4 channels can be configured to work in parallel mode to allow regulation of higher current set-points: this option is suitable for example in applications where setting HILOAD = 1 is not enough to match targets. Channel parallelization can be enabled only for fixed channel pairs:
- ch0 can be put in parallel with ch1 only
- ch2 can be put in parallel with ch3 only In parallel mode one channel acts as a master (ch0, ch2) and the other as a slave (ch1, ch3): both channel current sense measurements are kept active to measure load current split between channel pair: the two measurements are combined and used to close control loop on master logic only. Configuration of parallel mode is done through master channel registers and in detail the following master parameters are valid for both channels, overwriting slave channel configuration (if any):
- Current set-point,
- Dither parameters,
- Control loop parameters (Ki, Kp, fix/var frequency mode selector, Kfi, etc…) As a consequence of the described implementation, the resulting resolution of the current and dither set-point registers is doubled since target value is applied on both channels in parallel: it means that in parallel mode 1 LSB = 0.5 mA instead of default 0.25 mA. Feedback of measured average current is kept distinguished like in normal operation and available for each channel on its own register with nominal LSB of 0.25 mA. The same applies for HS-LS compare check and applied offset compensation. The following parameters are kept independent between master and slave channels and particular attention must be paid for proper configuration settings:
- HW/SW mode selection
- HS/LS configuration
- INx/NDISx functionality
- diagnostic
- calibration data
- offset compensation L9305 Current control drivers DS12774 - Rev 10 page 24/107
- Bit 14 and/or Bit15 in SERVENA register must be set to 1 (Bit14 enables parallel mode for ch0-ch1 pair, Bit15 for ch2-ch3 pair)
- SOLENDRV configuration must be equal for selected parallel channel pair Even if diagnostic is kept independent, faults causing tri-state condition will affect both channels in parallel mode. Parallel mode is mandatory to use only with maximum slew rate setting and in configuration HILOAD=0. Besides, driver active time (T_ON) must be higher than a minimum value, which directly depends on load current, battery voltage applied to the solenoid and load parameters. Further guidelines on the usage of this feature are provided in a specific dedicated Application Note.
6.1.9 Dither programming
modulation on the current set point as shown in the Figure 13. Figure 13. Dither waveforms definitions
- Tstep: Dither step time duration is programmable as an integer number of PWM periods as defined by the formula Di t ℎ e rSt ep Du ra ti o n = Ts t ep + 1 * Tp w m where: – Tstep is programmable in Channel_x.DITHPGM2, D[5:0]. – TPWM is the PWM period programmable in Channel_x.CTRLCFG register, D[10]
- Nstep: number of steps in a quarter of a dither period, where: – Nstep is the value programmed in Channel_DITHPGM2 register, D[12:8] – If Nstep = 0, a square wave dither of 2 steps peak to peak will be generated
- Istep: Current step amplitude is programmable in Channel_xDITHPGM1 register, D[7:0] with the same current resolution as the current set point. – HILOAD = 0 → Normal current mode - Single bit resolution = 0.25 [mA] - Max Step Current 63.75[mA]; Di t ℎ e rSt ep Cu r ren t = I s t ep 7 : 0 * 0.25 m A – HILOAD = 1 → High current mode - Single bit resolution = 0.33 [mA] - Max Step Current 84.15[mA]. Di t ℎ e rSt ep Cu r ren t = I s t ep 7 : 0 * 0.33 m A
- Tdither: Dither period calculated as: Td i t ℎ er = 4* N s tep * Ts t ep
- Idither: Peak-to-peak current modulation amplitude calculated as: I di t ℎ er = 2* Ns t ep * I s tep Dither can be enabled/disabled via SPI in register Channel_x.DITHPGM1, D[15]. Dither waveform maximum amplitude is limited by the selected current resolution configuration (HILOAD, register CONFIGURATION1, D[15]) as shown below: HILOAD = 0 → Normal current mode - Max Dither Current Amplitude = ± 250 [mA]; HILOAD = 1 → High current mode - Max Dither Current Amplitude = ± 330 [mA]; L9305 Current control drivers DS12774 - Rev 10 page 25/107
6.1.10 Dither synchronization
synchronous with the PWM control frequency.
- Dither SYNC Enable - register Channelx_DTHPGM1, bit D[14] – 0 → Dither synch for variable frequency is disabled – 1 → Dither synch for variable frequency is enabled
- SYNC TYPE – register ChannelxDTHPGM1, bit D[13] – 0 → All Dither Steps are synchronous with the PWM Period. In this case the time base for Dither Step duration is the actual PWM period rather than the exact target set point PWM period – 1 → The Dither Period starts synchronous with the actual PWM Period. Only for the initial step in the dither period, the Tstep is delayed to the next switch on transition of the PWM period. The time of such initial step may be longer than the programmed period.
6.2 Software current control
feedback, the MCU can close the current control loop. Figure 14. Software control configuration and LOADx_toff_res (where “x” is related to selected channel), has been added to these pins. the minimum period or maximum frequency of the signal delivered to the LOADx pin. (Global.Solenoid Drivers Enable) as shown below. Table 12. Solenoid driver channel status in software mode
(Channel_x.Configuration) can be enabled. Table 13. INx polarity until the FULL_ON mode is removed or a fault occurs.
6.3 Solenoid current control feedback
6.3.1 Average current
output register through the dedicated 14-bit field in SPI register Channel_x.AVGCUR.
- HILOAD = 0 → Normal current mode - Single bit resolution = 0.25 [mA] A v erag eC u rr en t = 2 Co mp l emet A v gC u r 13 : 0 *0.25 m A
- HILOAD = 1 → High current mode - Single bit resolution = 0.33 [mA] A v erag eC u rr en t = 2 Co mp l emet A v gC u r 13 : 0 *0.33 m A In case the Driver input signal is stuck high or low for a time period longer than Tpwm_max, the TMOUT warning flag is set in Channel_x.PWMSENSE register and the average current is evaluated only for Tpwm_max. After timeout, the average current and PWM code calculations restart automatically. When CHx.SETPOINT=0000 and channel x is controlled Hardware mode (CONFIGURATION1.D[2]=0), then the current measurement is disabled and AVGCUR always returns all ‘0’, even if channel x is driven full-on.
6.3.2 Integrator feedback
Integrator low threshold: The integrator such a threshold corresponds to the integrator value at which the PWM toggles from high to low and the output driver switches off. At this point, the load current reaches its max peak level. In variable frequency this level also corresponds to the “F_INTEGRAL” signal at the frequency integrator output. Use this integrator reading to correctly set the “Fint_Start” parameter. Integrator high threshold: The integrator such a threshold corresponds to the integrator value at which the PWM toggles from low to high and the output driver switches on. At this point, the load current reaches its min peak level. In variable frequency this level is zero. Use this integrator reading to verify the correct functionality of the variable frequency algorithm. Integrator minimum level: The minimum current integrator level. Use this integrator reading to correctly set the “NEGINTLIM” parameter. Integrator maximum level: The maximum current integrator level. Use this integrator reading to correctly set the “POSINTLIM” parameter.
6.3.3 Solenoid PWM period feedback
The actual PWM time period, whether it is generated by the internal logic in hardware mode or by the INx pins in software mode, is internally measured at each PWM rising edge and provided to the MCU for comparison with the programmed value in register Channel_x.PWMSENSE. It is also checked against the minimum period reference (Tpwm_min) and maximum period reference (Tpwm_max) values. Should the PWM period fall outside these limits, the TMOUT flag is set in SPI register Channel_x.PWMSENSE indicating the control loop is working at an unusual value. If no PWM signal is generated after the maximum reference period (Tpwm_max), the average current is calculated over Tpwm_max period of time. The PWM period is provided using 15 bits with 1µs resolution, providing feedback for periods exceeding Tpwm_max values. The PWM period feedback value is obtained by the formula: PW MPer i od = C ℎ an ne l _ x . PW MSE NSE . PW MC od e μ s (1)
- Tpwm_min = 40 µs → fpwm_max = 25 kHz
- Tpwm_max = 16.667 ms → fpwm_min = 60 Hz
6.3.4 Out of regulation flag
An out of regulation flag is set when the current controller average error is not zero for a time longer than 8 PWM periods, where the PWM period is the programmed PWM period in SPI register Channel_x.CTRLCFG. The flag is independent for each channel and is only available in Hardware Current Control mode. L9305 Current control drivers DS12774 - Rev 10 page 28/107
6.4 Solenoid driver and load diagnostic
6.4.1 Thermal protection
Each solenoid channel has a dedicated temperature sensor that continuously monitors the temperature of the Low Side and of the High Side power transistor. Temperature information is available in the dedicated SPI register Channel_x.TEMPMON. Register data can be decoded from the SPI frame using the following formula: T J = 1.353 * Temp er atu r eMon i t or − 74 C o (2) Should channel temperature reach the thermal warning threshold T_WARN, the thermal warning flag is set in the EXCEPTIONS1 register bit D[15]. The warning flag is latched and is cleared upon SPI read if the thermal warning condition is no longer present. Should channel temperature continue to rise up to the thermal shutdown threshold T_SD, the related channel is placed in tristate mode (setting the Solenoid Driver Status bits to 01, but keeping the programmed current set- point). This event has a dedicated fault flag in the EXCEPTIONS1 register, bit D[0]. Channel activation is prevented if thermal shut down condition is still present on SPI read. This fault is latched and is cleared upon SPI read if the fault is no longer present. Channel thermal shutdown temperature has no hysteresis, but user can decide which temperature is low enough to re-enable the channel. In fact, by monitoring Channelx.TEMPMON register, user can re-enable the channel when TEMPMON reading is below the temperature desired value: thus a further degree of flexibility is provided.
6.4.2 Overcurrent protection
Overcurrent protection is present for each HS and LS solenoid driver. The overcurrent threshold is selectable through SPI register Channel_x.CONFIGURATION1 bit D[6]. Should an overcurrent fault be detected (on HS or on LS), the related channel is put in tri-state (setting the Solenoid Driver Status bits to 01, but keeping programmed current set-point) and a dedicated diagnostic bit is set in register Channel_x.EXCEPTION1, bits D[2] for HS and D[1] for LS. To restart the channel, the MCU must clear the fault bit by reading the fault register and re-enable the channel.
6.4.3 Supply disconnection
When a solenoid channel is configured for low side operation, current recirculation occurs through the internal high side transistor. If the supply Vs_solX of the high side driver is lost, the voltage at LOAD_SOLx pin can become unpredictable and possibly exceed the absolute rating of the device. To prevent this condition from damaging the device, the low side driver has an integrated clamping circuit to limit the peak voltage. Should the low side clamping structure be activated during normal operation (i.e. solenoid supply line within normal operating range), the channel is put in tri-state (setting the Solenoid Driver Status bits to 01) and the Low Side Clamp Active fault flag D[3] is set in the EXCEPTIONS1 register. To restart the channel, the MCU must clear the fault by reading the EXCEPTIONS1 register and re-enable the channel. Activation of LS clamp during a load dump event could damage the device due to the high energy of load dump event. To avoid this condition, the LS clamp circuitry is automatically disabled when VBATP pin exceeds deep over-voltage threshold, as defined in Section 8.1.6.
6.4.4 Off state solenoid diagnostics
The device provides independent off-state diagnostics for each channel. Simplified diagrams are shown in Figure 15 and Figure 16 below, depending on the chosen configuration. L9305 Current control drivers DS12774 - Rev 10 page 29/107
Table 14. LS diagnostic truth table Table 15. HS diagnostic truth table
6.5 Valve driver electrical specifications
Tj ≤ 175 °C unless otherwise noted. All voltages refer to GNDA pin. Table 16. Valve driver power stage electrical parameters
Table 17. Current control electrical parameters
- provided configuration parameters and current control settings are able to allow proper regulation.
Table 18. Valve driver on state diagnostics parameters
Table 19. Valve driver LS off state diagnostics parameters Table 20. Valve Driver HS Off State Diagnostic Parameters
7 High side fail safe pre-driver
VDS comparator, to detect overcurrent/short conditions and prevent FET from overheating. the output driver, fault monitoring is masked for a period of T_FS_VDS_blank and filtered for T_FS_VDS_flt. again through the SPI (FSCONF register). status reading the PINSTATUS register, bit D[0]. Figure 17. Fail safe concept
- FS OFF: Device in Idle State. Fail Safe related registers at their default state. Internal reset state
- FS IDLE: Fail safe disabled. Fail safe related registers preserved but Enable Low. Two cases: – EN_DR low. Echo on SPI – Error on FS present. Error on SPI and on FAULT pin, if not masked.
- RUNNING: Fail Safe enabled and running with gate status depending on SPI command register value L9305 High side fail safe pre-driver DS12774 - Rev 10 page 35/107
allow for multiple fail safe pre-drivers the unused drivers will be kept disabled.
7.1 Fail safe predriver diagnostic
ground. Through SPI registers four different VDS thresholds are programmable (FSCONF register, bits D[1:0]). the Fail Safe pre-driver and sets the VDS fault flag in the SERVFLT1 register, bit D[10].
7.2 Fail safe predriver electrical characteristics
otherwise noticed. All voltages refer to AGND pin. Table 21. Fail safe predriver electrical parameters
Symbol Parameter Test condition Min Typ Max Unit Pin T_FS_VDS_blank VDS blank time Guaranteed by scan 90 110 120 µs FS_Dx, FS_Sx T_FS_VDS_flt VDS filter time EMI filter, guaranteed by design 100 600 1000 ns FS_Dx, FS_Sx L9305 High side fail safe pre-driver DS12774 - Rev 10 page 37/107
8 Safety features
Table 22. Safety monitors and self test summary
8.1 Power supply monitoring and diagnostics
8.1.1 VDD over and under voltage diagnostics
a fault, the corresponding fault bits are set as summarized below. Table 23. VDD Fault Summary read but solenoid and fail safe operation must be re-enabled through the SPI. drivers and the fail-safe pre-driver. The fault is clear on SPI read.
8.1.2 VBATP supply over voltage
fault, the corresponding fault bits are set as summarized below. Table 24. VBATP Fault Summary read but solenoid and fail safe operation must be re-enabled through the SPI.
8.1.3 VCP supply under voltage
Table 25. Charge pump fault summary read but solenoid and fail safe operation must be re-enabled through the SPI.
8.1.4 Bandgap regulators, internal analog and digital supply monitoring
POR flag is available as shown below. Table 26. POR fault summary
- In ODTEST register set bit D[0] = 1
- Monitor ODTEST register bit D[0] for test status, 1 = test in process, 0 = test complete.
- If ODTEST register bit D[0] = 1 the test has succeeded; if the test fails device executes a POR and the related bit will be set on SPI register.
8.1.5 GND loss detection
Table 27. GNDA and GNDD fault summary SPI read but solenoid and fail-safe operation must be re-enabled through the SPI. Table 28. Solenoid GND fault summary
- For the desired channel, in CONFIGURATION2 register set bit D[0] = 1
- Monitor EXCEPTIONS2 register, bit D[5] for test status, 1 = test in process, 0 = test complete.
- Read EXCEPTIONS2 register, bit D[3]; 0 = no fault; 1 = fault L9305 Safety features DS12774 - Rev 10 page 40/107
ground loss faults do not disable fail safe and are cleared on SPI read.
8.1.6 Power supply monitoring and diagnostics electrical characteristics
Table 29. Power supply monitoring electrical performance
- LS clamp circuitry automatically disabled, see Section 6.4.3
8.2 Main & reference oscillators
safe pre-driver: this disable condition will last until fault is recovered. through SPI Service Fault 2 register. Basic implementation of clock monitor is shown in the next figure. Figure 18. Oscillator monitor
8.2.1 Main and reference oscillators electrical characteristics
Table 30. Main and reference oscillator safety parameters
8.3 Safety switch-off path
overvoltage detection, i.e. the faults that cannot be directly managed by the digital core. power up it is always possible to test the safety off path functionality through EN_DR pin actuation.
8.3.1 Safety switch-off path electrical characteristics
Table 31. Oscillator safety switch-off path parameter
8.4 Valve drivers
explained in the following sections.
8.4.1 High side – low side current sense compare
independent. The current sense output is multiplexed into an analog to digital converter to close the control loop. reading the Measured H/L Delta Current value on a continuous basis and check for deviations. Figure 19. HS/LS current compare example
8.4.2 Solenoid current control ADC check
is cleared upon reading. A simplified block diagram is shown in the figure below. Figure 20. ADC check block diagram
8.4.3 Digital control loop logic BIST
- In CONFIGURATION1 register, set Solenoid Logic Bist, bit D[10] =1
- Test status and results are available in the EXCEPTIONS1 register, bits D[8:7] Test results are cleared on register read. If test is running and channel is activated, result is unpredictable since CONFIGURATION1 register becomes write protected and test cannot be put back in IDLE. In this case it is better to de-activate the test before activating the channel.
8.4.4 Calibration data check
Calibration and trimming data are used to compensate solenoid current control and internal reference circuitry. Table 32. NVM memory map CRC fault will operate uncalibrated thus having reduced performance.
8.4.5 Diagnostic comparators
(LV and OV) fails and actuation will be permitted.
- Disable off-state diagnostics, set CONFIGURATION1 register, D[5] = 0
- Enable diagnostics self-test, CONFIGURATION2 register, D[1] = 1
- Read results in EXCEPTIONS1 register, D[8:7]
8.4.6 PWM check
Check Fault, D[12] is set in the EXCEPTIONS1 register.
8.4.7 Valve driver safety electrical characteristics
Table 33. Valve driver safety parameters
0.8 A -15 – 15 % LOAD_SOLx
8.5 Core over temperature
around over temperature threshold.
8.5.1 Core over temperature electrical characteristics
Table 34. Core thermal monitoring electrical performance
8.6 IC data verification
- A global register mismatch flag (SERVFLT1, D[2]) is associated to the global registers – SERVENA – SOLENDR – TIMEOUTSPICFG – FSCONF – SERVFLTMSK1 – SERVFLTMSK2
- A channel register mismatch flag (EXCEPTIONS2, D[0]) is dedicated to each channel register bank – CONFIGURATION1 – CONFIGURATION2 – DITHPGM1 – DITHPGM2 – SETPOINT – CTRLCFG – KFREQCTRL – KGAINS – INTGLIM – DRVFLTMASK1 – DRVFLTMASK2 – BASEHLDELTACURR All the flags are cleared-on-read and refer to the entire register bank. No action is taken when a mismatch arises. Data mismatch flags can also be mapped to FAULTn pin using SERVFLTMSK1, D[2] for global register and DRVFLTMSK2, D[0] for channel registers. These flags are masked by default and must be enabled by the users as per their system needs. L9305 Safety features DS12774 - Rev 10 page 46/107
9 SPI
The SPI interface is used to configure the device, control the outputs and read diagnostic and status registers.
9.1 SPI protocol
- 5-bit CRC check (Hamming distance of 3 over 26 bits data)
- Frame Counter and Address Feedback
- Timeout Monitoring
- Short and Long Frame Length All R/W registers are mirrored (i.e., simultaneously written with the same value) and the content of each main register is verified with its related mirror register. Should a mismatch be detected, a fault flag is set. Details of this safety feature are summarized in Section 8.6. The SPI frame format is shown in Figure 21.
Figure 21. SPI Frame Format response consisting in the device ID. Figure 22. Out of frame response contain the device ID as shown in Figure 23.
- Input pins: – CS: Chip Select Active Low – SCLK: SPI Clock – MOSI: Master Output Slave Input. Communication path from MCU to the device
- Output pins: – MISO: Master Input Slave Output. Communication path from the device to the MCU
9.2 CRC
If a CRC error is detected, the received frame is ignored and the fault is indicated in the next SPI frame. account when executing hand calculations for CRC check. addition, as already stated, Bit 21 must be removed and Bit 4 to Bit 0 must be removed for CRC calculation. which should be divided by 100101, then “01010” should result as a CRC. and divide by 100101, then ‘0’ will be obtained as a remainder.
9.3 SPI errors management
Figure 26. SPI frame with error on previous SPI frame
9.4 SPI timeout monitoring function
monitoring function detects loss of the communications between the microcontroller and the device. (SERVFLT1 register, D[6]) and the FAULTn pin is set low if the corresponding fault mask bit is not set. with a default value of 2 ms. The timer is cleared when a valid SPI frame is received.
Table 35. SPI time out values D[6:5]) is programmed through SPI. Table 36. Reset latch enable state Table 37. Time out reset latch counter values
9.5 SPI channel exception field
9.6 SPI electrical specification
Table 38. SPI electrical parameters
- SPI max frequency may be less depending on the total capacitive load and MCU timing requirements
Figure 27. SPI timings, thresholds 20% to 80% and viceversa
9.7 SPI registers map table
monitored by SPI interface, the address space has been divided in pages of 32 addresses each. The table below shows the SPI page vs. macro function distribution. Table 39. SPI page address mapping
000 Solenoid Channel 0 Channel_0_BaseAddress 0x00 0000 0000
001 Solenoid Channel 1 Channel_1_BaseAddress 0x20 0010 0000
010 Solenoid Channel 2 Channel_2_BaseAddress 0x40 0100 0000
011 Solenoid Channel 3 Channel_3_BaseAddress 0x60 0110 0000
110 Global Global_BaseAddress 0xC0 1100 0000
111 Fault and Test Fault_Test_BaseAddress 0xE0 1110 0000
9.8 Global page
Global page contains general control/monitor registers. Table 40. SPI global page register address mapping
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Parallel mode selection for ch2-ch3 Parallel mode selection for ch0-ch1 Unused RAM retrigger Spread Spectrum Disable Unused Stagger Enable RW RW R RW RW R RW Address: Global Base Address + 0x00 Type: RW Reset: 0x0000 Description: General SERVICE Enable bits [15] Parallel mode selection for ch2-ch3 [14] Parallel mode selection for ch0-ch1 [13:10] Unused [9] RAM retrigger 1: Download calibration data from EEPROM. 0: Download complete or inactive [8] Spread Spectrum Disable: 0: Main Clock Spread Spectrum Enabled 1: Main Clock Spread Spectrum Disabled [7:1] Unused [0] Stagger Enable: 1: Stagger Enabled. 0: Stagger Disabled. Valid only when channel is in Fixed Frequency mode L9305 SPI DS12774 - Rev 10 page 53/107
SOLENDR Solenoid drivers enable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Solenoid Driver State_3 Solenoid Driver State_2 Solenoid Driver State_1 Solenoid Driver State_0 R RW RW RW RW Address: Global Base Address + 0x01 Type: RW Reset: 0x0055 Description: Solenoid Driver Configuration [15:8] Unused [7:6] Solenoid Driver State, Channel 3 00: Driver Off, OFF State Diagnostics disabled and masked 01 : Driver tristate. OFF DIAG depending on bit on config reg 10: Drives on in PWM. OFF DIAG off and masked 11: Drives on in full-on. OFF DIAG off and masked [5:4] Solenoid Driver State, Channel 2 00: Driver Off, OFF State Diagnostics disabled and masked 01 : Drives tristate. OFF DIAG depending on bit on config reg 10: Drives on in PWM. OFF DIAG off and masked 11: Drives on in full-on. OFF DIAG off and masked [3:2] Solenoid Driver State, Channel 1 00: Driver Off, OFF State Diagnostics disabled and masked 01 : Drives tristate. OFF DIAG depending on bit on config reg 10: Drives on in PWM. OFF DIAG off and masked 11: Drives on in full-on. OFF DIAG off and masked [1:0] Solenoid Driver State, Channel 0 00: Driver Off, OFF State Diagnostics disabled and masked 01: Drives tristate. OFF DIAG depending on bit on config reg 10: Drives on in PWM. OFF DIAG off and masked 11: Drives on in full-on. OFF DIAG off and masked L9305 SPI DS12774 - Rev 10 page 54/107
TIMEOUTSPICFG Timeout SPI configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 unused Timeout NR Reset Timeout Configuration Enable Reset Latch Disable Reset Latch R RW RW RW RW Address: Global Base Address + 0x02 Type: RW Reset: 0x0028 Description: SPI TIMEOUT Configuration Register [15:7] Unused [6:5] Number of SPI timeout events to force an internal reset Timeout NR Reset [1:0]; Calculated as 2^(N+1) (e.g., default N= "01", Timeout Events = 4) [4:2] Maximum time between valid SPI frames before SPI time-out fault flag is set.Timeout Configuration [2:0]: Calculated as follows: 504 x 2N [µs] (e.g., default N=B“010” means 2016 [µs]) [1] Enable Reset Latch - En_Res_Latch[1]: 0: Reset Latch Disabled 1: Reset Latch Enabled [0] Disable Reset Latch - Dis_Res_Latch[0] 0: Reset Latch Enabled 1: Reset Latch Disabled L9305 SPI DS12774 - Rev 10 page 55/107
FSCONF Fail safe pre-driver configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused FS_3_EN (only TQFP48) FS3 Predriver Fault Threshold (only TQFP48) FS_2_EN (only TQFP48) FS2 Predriver Fault Threshold (only TQFP48) FS_1_EN (only TQFP48) FS1 Predriver Fault Threshold (only TQFP48) FS_EN/ FS_0_EN FS/FS0 Predriver Fault Threshold R RW RW RW RW RW RW RW RW Address: Global Base Address + 0x03 Type: RW Reset: 0x0000 Description: Fail Safe Configuration and Enable [15:12] Unused [11] FS3 Predriver Enable – FS_3_EN (only TQFP48) 0: Fail Safe Predriver Disabled 1: Fail Safe Predriver Enabled [10:9] FS3 Predriver Fault Threshold (only TQFP48) 00: 0.25V VDS Threshold 01: 0.5V VDS Threshold 10: 0.75V VDS Threshold 11: 1.0V VDS Threshold [8] FS2 Predriver Enable – FS_2_EN (only TQFP48) 0: Fail Safe Predriver Disabled 1: Fail Safe Predriver Enabled [7:6] FS2 Predriver Fault Threshold (only TQFP48) 00: 0.25V VDS Threshold 01: 0.5V VDS Threshold 10: 0.75V VDS Threshold 11: 1.0V VDS Threshold L9305 SPI DS12774 - Rev 10 page 56/107
[5] FS1 Predriver Enable – FS_1_EN (only TQFP48) 0: Fail Safe Predriver Disabled 1: Fail Safe Predriver Enabled [4:3] FS1 Predriver Fault Threshold (only TQFP48) 00: 0.25V VDS Threshold 01: 0.5V VDS Threshold 10: 0.75V VDS Threshold 11: 1.0V VDS Threshold [2] FS/FS0 Predriver Enable – FS_EN/FS_0_EN 0: Fail Safe Predriver Disabled 1: Fail Safe Predriver Enabled [1:0] FS/FS0 Predriver Fault Threshold 00: 0.25V VDS Threshold 01: 0.5V VDS Threshold 10: 0.75V VDS Threshold 11: 1.0V VDS Threshold L9305 SPI DS12774 - Rev 10 page 57/107
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Reserved CHIP ID Version CHIP ID SubVersion Address: Global Base Address + 0x1F Type: Read Only Description: Chip Identification Information Register Bit Field name/description Default values Type [15:7] Unused All "0" Read [6] Reserved 0 Read [5:3] CHIP ID Version 001 Read [2:0] CHIP ID SubVersion 011 Read Note: Reserved bit [6] should not be used by customer. L9305 SPI DS12774 - Rev 10 page 58/107
9.9 Fault and test page summary
Table 41. SPI fault and test page register address mapping
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused BUSY echo SAFETYn echo FAULTn echo RES echo IN 3 echo IN 2 echo IN 1 echo IN 0 echo EN_DR echo Address: Fault Test Base Address + 0x00 Type: R Reset: 0b0000000X1XXXXXXX Description: Echo Input Status & Internal Settings [15:9] Unused [8] Busy Echo - Internal signal set high when device is downloading data from EEPROM to various system control registers [7] SAFETY echo - internal signal set low when the device has disabled the failsafe pre-driver using the parallel shutdown path [6] FAULTn Pin echo - FAULTn pin status feedback [5] RES Echo 1: RESn pin is Low 0: RESn pin is high [4] IN 3 echo: IN3 Pin Status when in HW mode 0: Solenoid Channel 3 Enabled 1: Solenoid Channel 3 Disabled or SW mode selected [3] IN 2 echo: IN2 Pin Status when in HW mode 0: Solenoid Channel 2 Enabled 1: Solenoid Channel 2 Disabled or SW mode selected [2] IN 1 echo: IN1 Pin Status when in HW mode 0: Solenoid Channel 1 Enabled 1: Solenoid Channel 1 Disabled or SW mode selected [1] IN 0 echo: IN0 Pin Status when in HW mode 0: Solenoid Channel 0 Enabled 1: Solenoid Channel 0 Disabled or SW mode selected [0] EN_DR echo: EN_DR pin status 0: Driver Disabled 1: Driver Enabled L9305 SPI DS12774 - Rev 10 page 60/107
ODTESTS On demand self tests 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused V3V3 Self Tests R RW Address: Fault Test Base Address + 0x01 Type: RW Reset: 0x0000 Description: Global On Demand Self Tests [15:1] Unused [0] V3V3 Self Tests: 1: Start test 0: Test completeShould test fail, POR fault will be latched (SERVFLT1 register). L9305 SPI DS12774 - Rev 10 page 61/107
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Digital Ground Loss Analog Ground Loss Fail safe pre-driver CH3 VDS fault (valid only for TQFP48 package) Fail safe pre-driver CH2 VDS fault (valid only for TQFP48 package) Fail safe pre-driver CH1 VDS fault (valid only for TQFP48 package) Fail safe VDS Fault POR flag EEPROM Trimming Data CRC error SPI Timeout Latch SPI Timeout VDD Over Voltage VDD Under Voltage CP Under Voltage Configuration Register Monitor VBATP Over Voltage Core Over temperature RH RH R R R RH RH R RH RH RH RH RH RH RH RH Address: Fault Test Base Address + 0x03 Type: R Type: 0x200 Description: Service Fault register stores Diagnostic flags of enabled services (i.e., Monitors) [15] Digital Ground Loss (GNDD Loss) 0: No Fault 1: GND_D Loss Clear on Read [14] Analog Ground Loss (GNDA Loss) 0: No Fault 1: GND_A Loss Clear on Read [13] Fail safe pre-driver VDS fault CH3: 0: No Fault. 1: VDS fault detected L9305 SPI DS12774 - Rev 10 page 62/107
[12] Fail safe pre-driver VDS faul CH2: 0: No Fault. 1: VDS fault detected [11] Fail safe pre-driver VDS fault CH1: 0: No Fault. 1: VDS fault detected [10] Fail safe pre-driver VDS fault CH0: 0: No Fault 1: VDS fault detected Clear on Read [9] Power On Reset (POR) flag: 0: POR released and flag read 1: POR detected Clear on Read [8] EEPROM Trimming data CRC error: 0: No CRC error 1: CRC error [7] SPI Timeout Latch: 0: No Fault 1: SPI Communication Timeout Latch Set Clear on Read [6] SPI Timeout: 0: No Fault 1: SPI Communication Timeout Clear on Read [5] VDD Over Voltage: 0: No Fault 1: Over Voltage Fault Clear on Read [4] VDD Under Voltage: 0: No Fault 1: Under Voltage Fault Clear on Read [3] Charge Pump Under Voltage: 0: No Fault 1: Under Voltage Fault Clear on Read [2] Configuration Register Monitor Solenoid Drivers Enable, Timeout SPI Config, FS Predriver Config 0: No Fault 1: Register Fault Clear on Read [1] VBATP Over Voltage: 0: No Fault 1: Over Voltage Fault Clear on Read L9305 SPI DS12774 - Rev 10 page 63/107
[0] Core Over Temperature: 0: No Fault 1: Thermal Shutdown Clear on Read L9305 SPI DS12774 - Rev 10 page 64/107
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Clamp inhibit self-test Clamp inhibit monitor Unused VDD OV Self-test VDD UV Self-test Unused VBAT OV Self-test GNDLOSS D Self-test GNDLOSS A Self-test Diag Oscillator Stuck-at Monitor Main Oscillator Monitor RH R R RH RH R RH RH RH RH RH Address: Fault_Test_BaseAddress + 0x04 Type: R Reset: 0x0000 Description: Service Fault register stores Diagnostic flags of enabled services (i.e., Monitors & Self Tests) [15] Clamp Diode Inhibit Selftest Clear on Read [14] Clamp Diode Inhibit Monitor [13:8] Unused [7] VDD OV Selftest 0: No Fault 1: Fault Detected Clear on Read [6] VDD UV Selftest 0: No Fault 1: Fault Detected Clear on Read [5] Unused [4] VBAT OV Selftest 0: No Fault 1: Fault Detected Clear on Read [3] GNDLOSS D Selftest: 0: No Fault 1: Fault Detected Clear on Read L9305 SPI DS12774 - Rev 10 page 65/107
[2] GNDLOSS A Selftest: 0: No Fault 1: Fault Detected Clear on Read [1] Diag Oscillator Stuck-at Monitor: 0: No Fault 1: Fault Detected Clear on Read [0] Main Oscillator Monitor: 0: No Fault 1: Fault Detected Clear on Read L9305 SPI DS12774 - Rev 10 page 66/107
SERVFLTMSK1 Service Fault Mask 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Digital Ground Loss Analog Ground Loss Fail Safe VDS Fault CH3 (valid only for TQFP48 package) Fail Safe VDS Fault CH2 (valid only for TQFP48 package) Fail Safe VDS Fault CH1 (valid only for TQFP48 package) Fail Safe VDS Fault CH 0 Unused EEPROM Trimming data CRC error SPI Timeout Latch SPI Timeout Unused VDD Under Voltage CP Under Voltage Configuration Register VBATP Over Voltage Core Over Temperature RW RW R RW R RW RW RW R RW RW RW RW RW Address: Fault_Test_BaseAddress + 0x05 Type: RW Reset: 0xFFFF Description: Service Fault Mask register allows the user to map specific fault flags to the FAULTn pin. Setting mask bit high disables (masks) fault from setting FAULTn pin. [15] Digital Ground Loss: 0: Mask Disabled 1: Mask Enabled [14] Analog Ground Loss: 0: Mask Disabled 1: Mask Enabled [13] Fail Safe VDS Fault CH3: 0: Mask Disabled 1: Mask Enabled [12] Fail Safe VDS Fault CH2: 0: Mask Disabled 1: Mask Enabled [11] Fail Safe VDS Fault CH1: 0: Mask Disabled 1: Mask Enabled [10] Fail Safe VDS Fault CH0: 0: Mask Disabled 1: Mask Enabled [9] Unused [8] EEPROM Trimming data CRC error: L9305 SPI DS12774 - Rev 10 page 67/107
0: Mask Disabled 1: Mask Enabled [7] SPI Timeout Latch: 0: Mask Disabled 1: Mask Enabled [6] SPI Timeout: 0: Mask Disabled 1: Mask Enabled [5] Unused [4] VDD Under Voltage: 0: Mask Disabled 1: Mask Enabled [3] CP Under Voltage: 0: Mask Disabled 1: Mask Enabled [2] Configuration Register 0: Mask Disabled 1: Mask Enabled [1] VBATP Over Voltage: 0: Mask Disabled 1: Mask Enabled [0] Core Over Temperature: 0: Mask Disabled 1: Mask Enabled L9305 SPI DS12774 - Rev 10 page 68/107
SERVFLTMSK2 Service fault mask 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Clamp Inhibit Monitor Unused SPI Protocol Error Unused IN 3 echo IN 2 echo IN 1 echo IN 0 echo EN_DR echo R RW R RW R RW RW RW RW RW Address: Fault Test Base Address + 0x06 Type: RW Reset: 0xFFFF Description: Service Fault Mask register allows the user to map specific fault flags to the FAULTn pin. Setting mask bit high disables (masks) fault from setting FAULTn pin. [15] Unused [14] Clamp Inhibit Monitor 0: Mask Disabled 1: Mask Enabled [13:8] Unused [7] SPI Protocol Error 0: Mask Disabled 1: Mask Enabled [6:5] Unused [4] IN3 0: Mask Disabled 1: Mask Enabled [3] IN2 0: Mask Disabled 1: Mask Enabled [2] IN1 0: Mask Disabled 1: Mask Enabled [1] IN0 0: Mask Disabled 1: Mask Enabled [0] EN_DR 0: Mask Disabled 1: Mask Enabled L9305 SPI DS12774 - Rev 10 page 69/107
COMMUNICATIONFLTS SPI communications faults 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Frame Counter Error Flag CRC Error Flag Short Frame Flag Loong Frame Flag Unused Address: Fault_Test_BaseAddress + 0x1D Type: R Reset: 0x0000 Description: SPI communication faults monitors [15:13] Unused [12] Frame Counter Error Flag 0: No Fault 1: Wrong Counter Value [11] CRC Error Flag 0: No Fault 1: CRC Check Fault [10] Short Frame Flag 0: No Fault 1: Frame bits received < 16 [9] Long Frame Flag 0: No Fault 1: Frame bits received > 16 [8:0] Unused L9305 SPI DS12774 - Rev 10 page 70/107
9.10 Channel page registers
Table 42. SPI channel page register address mapping
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T_WARN EEPROM CRC error on CSA Calibration data EEPROM CRC error on A2D trimming bits PWM check fault PWM check comp mismatch Solenoid Logic BIST Status Solenoid Diag Self Test Open Load Short Detection Solenoid ADC mismatch Monitor LS clamp active HS over current LS over current T_SD RH R R RH RH R RH RH RH RH RH RH RH RH Address: Channel_X_BaseAddress + 0x00 Reset 0x0000 Description: Solenoid Driver Fault Status [15] Thermal Warning (T_WARN): 0: No Fault 1: Thermal Warning Present Clear on Read [14] EEPROM CRC Error on CSA Calibration Data: 0: No Fault 1: CRC Error Read [13] EEPROM CRC error on A2D trimming bits: 0: No Fault 1: CRC Error Read [12] PWM Check Fault (ON State): 0: No Fault 1: Fault Clear on Read [11] PWM Check Comp Mismatch (ON State): 0: No Fault 1: Fault Clear on Read [10:9] Solenoid Logic BIST Status: (ADC mismatch, out of regulation, Solenoid driver control loop) L9305 SPI DS12774 - Rev 10 page 72/107
00: Idle 01: BIST running 10: BIST passed 11: BIST failed Read [8:7] Solenoid Diag Self Test (OFF State): 00: Self Test pass 01: DIAG_LV comparator fail 10: DIAG OL comparator fail 11: Self Test fail Clear on Read [6] Open Load (OFF State): 0: No Fault 1: Open load Clear on Read [5] Short Detection (OFF State): 0: No Fault 1: Short Detected Clear on Read [4] Solenoid ADC Mismatch monitor: 0: No Fault 1: Mismatch Fault Detected Clear on Read [3] LS Clamp Active (ON state): 0: No Fault 1: LS Clamp Activated Clear on Read [2] HS Over Current (ON State) 0: No Fault 1: HS Over Current Clear on Read [1] LS Over Current (ON State) 0: No Fault 1: LS Over Current Clear on Read [0] T_SD: (Thermal Shutdown) 0: No Fault 1: Thermal Shutdown Fault Clear on Read L9305 SPI DS12774 - Rev 10 page 73/107
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 unused GND_SOL loss self test Out of regulation GND_SOL loss fault RAM CRC error HS/LS compare Fault Configuration Register Monitor R RH RH RH RH RH RH Address: Channel_X_BaseAddress + 0x01 Type: RH Reset: 0x0000 Description: Solenoid Driver Fault Status [15:6] Unused [5] GND_SOL Loss Self Test Status 0: Test Complete 1: Test Running Clear on Read [4] Out of regulation 0: No Fault 1: Out of Regulation After 8 PWM Cycles Clear on Read [3] GND_SOL loss fault 0: No Fault 1: Solenoid Ground Loss Detected Clear on Read [2] RAM CRC error 0: No Fault 1: CRC Fault Detected on RAM Read Clear on Read [1] HS/LS compare Fault: 0: No Fault 1: Fault Detected Clear on Read [0] Configuration Register Monitor: L9305 SPI DS12774 - Rev 10 page 74/107
0: No Fault 1: Fault Detected Clear on Read L9305 SPI DS12774 - Rev 10 page 75/107
CONFIGURATION1 Configuration 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 unused OFS_CMP_DIS CALIBRATION_DIS unused Solenoid Logic BIST Td_Blank HILOAD unused Overcurrent threshold selection Enable OFF Diagnosis unused Solenoid Load Configuration Current Feedback Control Mode Output Slew Rate R RW RW R RW RW RW RW RW RW R RW RW RW Address: Channel_X_BaseAddress + 0x02 Type: RW Reset: 0x0000 Description: Configuration Register provides information related to channel configuration [15] Unused [14] OFS_CMP_DIS: 0: Current Sense Offset Compensation Active 1: Current Sense Offset Compensation disabled [13] CALIBRATION_DIS: 0: Digital Current Sense Calibration Active 1: Digital Current Sense Calibration Disabled [12:11] Unused [10] Solenoid Logic BIST: 0: Logic BIST Reset 1: Logic BIST Enabled [9] Td_Blank: 0: Long Blanking Time 1: Short Blanking Time [8] HILOAD: Current Sense Scale 0: 1.5A Max Current Range 1: 2.0A Max Current Range [7] Unused [6] Overcurrent threshold selection: 0: 4A Theshold 1: 5A Threshold [5] Enable OFF Diagnosis: L9305 SPI DS12774 - Rev 10 page 76/107
0: Disabled (OFF) 1: Enabled [4] Unused [3] Solenoid Load Configuration: 0: Low Side 1: High Side [2] Current Feedback Control Mode: 0: HW Feedback 1: SW Feedback [1:0] Output Slew Rate: 00: 0.4V/µs 01: 1.0V/µs 10: 4.0V/µs 11: 8.0V/µs L9305 SPI DS12774 - Rev 10 page 77/107
CONFIGURATION2 Configuration 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Solenoid Diag Self Test GND_SOL loss self test R RW RW Address: Channel_X_BaseAddress + 0x03 Type: RW Reset: 0x0000 Description: Configuration Register for channel configuration self-tests. Before restarting any tests, wait for the register to return to "0" [15:2] Unused [1] Solenoid Diag Self Test: Short, Open Load and PWM Check 0: Self Test Disabled 1: Self Test Enabled [0] GND_SOL loss self test 0: Self TestDisabled 1: Self Test Enabled L9305 SPI DS12774 - Rev 10 page 78/107
DITHPGM1 Dither programming 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dither Enable DITHER_SYNC_EN SYNC TYPE Unused Istep RW RW RW R RW Address: Channel_X_BaseAddress + 0x04 Type: RW Reset: 0x0050 Description: Dither Generator Configuration [15] Dither Enable: 0: Disabled 1: Enabled [14] DITHER_SYNC_EN: 0: Disabled 1: Enabled [13] SYNC TYPE: 0: Dither Synchronization at each Dither Step 1: Dither Synchronization at each dither Period [12:8] Unused [7:0] Istep: Current step Value L9305 SPI DS12774 - Rev 10 page 79/107
DITHPGM2 Dither programming 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Nstep Unused Tstep R RW R RW Address: Channel_X_BaseAddress + 0x05 Type: RW Reset: 0x028A Description: Dither Generator Configuration [15:13] Unused [12:8] Nstep: Number of steps in a quarter of dither period [7:6] Unused [5:0] Tstep: Number of PWM cycles for each dither step SETPOINT Current set point 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Auto Limit unused Current Set Point code RW R RW Address: Channel_X_BaseAddress + 0x06 Type: RW Reset: 0x0000 Description: Register stores current setpoint code (HW mode current control). Current Control SETPOINT is coded into 13 bits. Current value depends on HILOAD bit. [15] Auto Limit: Activates the transient mode on set point change 0: Inactive 1: Active [14:13] Unused [12:0] Current Set Point Code L9305 SPI DS12774 - Rev 10 page 80/107
CTRLCFG Control configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Transition Time Unused HW Feedback Frequency Mode Target PWM Period Code RW R RW RW Address: Channel_X_BaseAddress + 0x07 Type: RW Reset: 0x0000 Description: [15:14] Transition Time: Too long period detection (if the current PWM time exceeds this threshold, the controller enters the transient state): 00: 2.5 * Tpwm 01 : 4.5 * Tpwm 10: 8.5 * Tpwm 11 : 16.5 * Tpwm [13:12] Unused [11] HW feedback Frequency Mode: 0: Fixed Frequency 1: Variable Frequency [10:0] Target PWM Period Code L9305 SPI DS12774 - Rev 10 page 81/107
KFREQCTRL Frequency control 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused KFI FINT_START R RW RW Address: Channel_X_BaseAddress + 0x08 Type: RW Reset: 0x002F Description: Register stores KF, FCIL (Variable frequency forward gain: HW mode current control) [15:6] unused [5:3] KFI: Integral Gain of Frequency Control Loop [2:0] FINT_START: Start value for frequency integrator upon exiting transient mode KGAINS Gains configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused KI KP R RW RW Address: Channel_X_BaseAddress + 0x09 Type: RW Reset: 0x0024 Description: Register stores KI (Integral error gain: HW mode current control) and KP (Proportional error gain: HW mode current control). [15:6] unused [5:3] KI: Integral Gain of HW current control loop (fixed & variable freq.) [2:0] KP: Proportional Gain of HW current control loop (fixed freq. only) L9305 SPI DS12774 - Rev 10 page 82/107
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT_OUT_SEL unused NEGINTLIM POSINTLIM RW R RW RW Address: Channel_X_BaseAddress + 0x0A Type: RW Reset: 0x0000 Description: -- [15:14] INT_OUT_SEL: 00: Integrator Low Threshold 01: Integrator High Threshold 10: Integrator Min Level 11: Integrator Max Level [13:8] Unused [7:4] NEGINTLIM [3:0] POSINTLIM AVGCUR Average current 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused AVGCUR Address: Channel_X_BaseAddress + 0x0B Type: R Reset: 0x0000 Description: Stores Average Current Code in 1 PWM period [15:14] Unused [13:0] AVGCUR: Average current code (signed) in 1 PWM period L9305 SPI DS12774 - Rev 10 page 83/107
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMOUT PWM Code RH R Address: Channel_X_BaseAddress + 0x0C Type: RH Reset: 0x0000 Description: PWM period out of range flag (TMOUT). PWM code: measured effective PWM period [15] TMOUT 0: No Fault 1: Fault Detected Clear on Read [14:0] PWM Code L9305 SPI DS12774 - Rev 10 page 84/107
DRVFLTMASK1 Driver fault mask 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E_SOL_TW EEPROM CRC Error on CSA Calibration Data Mask EEPROM CRC Error on A2D Trimming Bits Mask PWM check fault PWM Check Comp Mismatch Unused E_SOL_OL E_SOL_SHORT E_SOL_A2D E_LSCLAMP E_SOL_HSOVC E_SOL_LSOVC E_SOL_OT RW RW RW RW RW R RW RW RW RW RW RW RW Address: Channel_X_BaseAddress + 0x0D Type: RW Reset: 0xFFFF Description: Driver Fault Mask register is an active High Mask register for Driver Faults. Setting mask bit disables corresponding fault from generating interrupt on FAULT pin. [15] E_SOL_TW: Solenoid Driver Thermal Warning 0: NOT Masked 1: MASKED [14] EEPROM CRC error on CSA Calibration data Mask: 0: NOT Masked 1: MASKED [13] EEPROM CRC error on A2D trimming bits Mask: 0: NOT Masked 1: MASKED [12] PWM Check Fault: 0: NOT Masked 1: MASKED [11] PWM Check Comp Mismatch: 0: NOT Masked 1: MASKED L9305 SPI DS12774 - Rev 10 page 85/107
[10:7] Unused [6] E_SOL_OL: Open Load Fault Mask 0: NOT Masked 1: MASKED [5] E_SOL_SHORT: Solenoid Short Fault Mask 0: NOT Masked 1: MASKED [4] E_SOL_A2D: Solenoid ADC Mismatch Fault Mask 0: NOT Masked 1: MASKED [3] E_LSCLAMP: Low Side Clamp Active Fault Mask 0: NOT Masked 1: MASKED [2] E_SOL_HSOVC: High Side Over Current Fault Mask 0: NOT Masked 1: MASKED [1] E_SOL_LSOVC: Low Side Over Current Fault Mask 0: NOT Masked 1: MASKED [0] E_SOL_OT: Solenoid Driver Over Temperature Fault Mask 0: NOT Masked 1: MASKED L9305 SPI DS12774 - Rev 10 page 86/107
DRVFLTMASK2 Driver fault mask 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Out of regulation GND_SOL loss fault E_RAM_CRC_ERR E_SOL_HS/LS E_CFG_REG_FAIL R RW RW RW RW RW Address: Channel_X_BaseAddress + 0x0E Type: RW Reset: 0xFFFF Description: Driver Fault Mask register is an active Hi Mask register for Driver Faults. Setting mask bit disables corresponding fault from generating interrupt on FAULT pin [15:5] unused [4] Out of regulation 0: NOT Masked 1: MASKED [3] GND_SOL loss fault 0: NOT Masked 1: MASKED [2] RAM CRC error 0: NOT Masked 1: MASKED [1] E_SOL_HS/LS: 0: NOT Masked 1: MASKED [0] E_CFG_REG_FAIL: 0: NOT Masked 1: MASKED L9305 SPI DS12774 - Rev 10 page 87/107
BSHLDELTACURR Base H/L delta current 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Base Delta Current R RW Address: Channel_X_BaseAddress + 0x0F Type: RW Reset: 0x0000 Description: Base High Side/Low Side Delta Current [15:8] Unused [7:0] Base Delta Current: Base High Side/Low Side Delta Current L9305 SPI DS12774 - Rev 10 page 88/107
MEASHLDELTACURR Measure H/L delta current 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 unused Meas Delta Current R RW Address: Channel_X_BaseAddress + 0x10 Type: R Reset: 0x0000 Description: Measured H/L Delta current [15:8] Unused [7:0] Measured Base Delta Current Between High & Low Side L9305 SPI DS12774 - Rev 10 page 89/107
TEMPMON Temperature monitor 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Temperature Monitor Address: Channel_X_BaseAddress + 0x11 Type: R Reset: 0x0000 Description: Temperature Monitor [15:8] Unused [7:0] Temperature Monitor: Unsigned L9305 SPI DS12774 - Rev 10 page 90/107
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTOUT Address: Channel_X_BaseAddress + 0x14 Type: R Reset: 0x0000 Description: Integrator Output Monitor [15:0] Integrator Output Monitor: Unsigned L9305 SPI DS12774 - Rev 10 page 91/107
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10.1 TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package information Figure 28. TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package outline
Package information
DS12774 - Rev 10 page 92/107
Table 43. TQFP48 (7x7x1 mm exp. pad down 5.0x5.0) package mechanical data
- Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
- The top package body size may be smaller than the bottom package size up to 0.15 mm.
- Datum A-B and D to be determined at datum plane H.
- To be determined at seating datum plane C.
- Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25
mm” per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
- Details of pin 1 identifier are optional but must be located within the zone indicated.
- All dimensions are in millimeters.
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- No intrusion allowed inwards the leads. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 10. Exact shape of each corner is optional. 11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. A1 is defined as the distance from the seating plane to the lowest point on the package body. 13. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from exposed pad itself. 14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove. 15. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface. 16. “N” is the number of terminal positions for the specified body size. L9305
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10.2 TQFP48 (7x7x1.0 exposed pad down) footprint Figure 29. TQFP48 (7x7x1.0 exposed pad down) footprint DS12774 - Rev 10 page 95/107
10.3 TQFP48 marking information
Figure 30. TQFP48 marking information engineering samples to run a qualification activity. DS12774 - Rev 10 page 96/107
10.4 PowerSSO-36 (7.2x4.75 mm option C exposed pad down) package information Figure 31. PowerSSO-36 (7.2x4.75 mm option C exposed pad down) package outline Table 44. PowerSSO-36 (exposed pad down) package mechanical data DS12774 - Rev 10 page 97/107
Min. Typ. Max. A2 2.15 - 2.35 b 0.18 - 0.32 7, 8 b1 0.13 0.2 0.30 7, 8 c 0.23 - 0.32 7 c1 0.20 0.20 0.30 7 D 10.30 BSC 3, 4 D1 VARIATION 11 D2 - 3.65 - D3 - 4.30 - e 0.50 BSC E 10.30 BSC E1 7.50 BSC 3, 4 E2 VARIATION 11 E3 - 2.30 - E4 - 2.90 - G1 - 1.20 - G2 - 1.00 - G3 - 0.80 - h 0.30 - 0.40 9 L 0.55 0.70 0.85 L1 1.40 REF L2 0.20 BSC N 36 6 R1 0.30 - - R2 0.20 - - S 0.25 - - Tolerance of form and position aaa 0.20 1, 2 bbb 0.20 ccc 0.08 ddd 0.08 eee 0.10 fff 0.20 ggg 0.15 VARIATIONS D1 6.50 - 7.10 A E2 4.10 - 4.70 D1 4.90 - 5.50 B E2 4.10 - 4.70 D1 6.90 - 7.50 C L9305 DS12774 - Rev 10 page 98/107
Min. Typ. Max. E2 C4.30 - 5.20 Notes: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. 3. Dimensions D and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side D and “0.15 mm” per side E1. D and E1 are Maximum plastic body size dimensions including mold mismatch. 4. The top package body size may be smaller than the bottom package size. 5. Datum A-B and D to be determined at datum plane H. 6. “N” is the max number of terminal positions for the specified body size. 7. The dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in exceed of the “b” dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. 9. This Chamfer feature is optional. If it is not present, then a PIN 1 identifier must be located within the index area indicated. 10. A1 is defined as the vertical distance from the seating plane to the lowest point on the package body. 11. Dimension D1 and E2 show the minimum allowed for the optional exposed pad. The size of exposed pad is variable depending of leadframe design pad size. End user should verify “D1” and “E2” dimensions for each device application.
10.5 PowerSSO-36 marking information
Figure 32. PowerSSO-36 marking information engineering samples to run a qualification activity. DS12774 - Rev 10 page 99/107
Revision history
Table 45. Document revision history 12-Dec-2018 1 Initial release. 17-Jul-2019 3 The confidentiality level is changed from "Restricted" to "Public". Table 4. Device operating temperature; Table 33. Valve driver safety parameters. Minor text changes in Features. Section 9.10.3 CONFIGURATION1. 11-May-2021 7 Minor text changes in Section 6.1.8 Parallel mode. 25-Nov-2021 8 Typo corrections. 27-Feb-2024 9 Updated Table 33. Valve driver safety parameters.
Contents
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