L9026-B03N-TR

L9026 STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 60

Technical content

Datasheet sections

• 1 Block diagram
• 2 Application circuit
• 3 Pins description
• 4 Product characteristics
• 4.1 Absolute maximum ratings
• 4.2 Latchup trials
• 4.3 Temperature range
• 5 Input / Output
• 5.1 Parallel inputs (IN0, IN1)
• 5.2 Idle pin (IDLE)
• 5.3 Reset pin (NRES, only in VFQFPN32 package option)
• 5.4 Enable (DIS, only in VFQFPN32 package option)
• 5.5 SPI communications (NCS, CLK, SI & SO)
• 5.6 Input / output electrical specifications
• 6 Power supply
• 6.1 Overview
• 6.2 Battery supply (VBATT)
• 6.3 Operating modes
• 6.4 Analog & Digital supply (VBATT)
• 6.5 I/O Supply (VDDIO)
• 6.6 Power up
• 6.7 Sleep mode
• 6.8 Idle mode
• 6.9 Active mode
• 6.10 Limp Home mode
• 6.11 Power supply transition
• 6.12 Reset
• 6.13 Power supply electrical specifications
• 7 Power stages

Features

• AEC-Q100 qualified
• Six Configurable LS/HS drivers
• Two High Side drivers
• 2 parallel input pins with Input Mapping functionality
• Cranking capability down to VBATT = 3 V
• Digital supply voltage compatible with 3.3 V and 5 V microcontroller
• Reverse battery protection on VBATT and on drain pins without external components
• LED mode
• Bulb Inrush Mode (BIM) to drive lamps and electronic loads
• 2 Internal PWM Generator for microcontroller offload
• Very low quiescent current (with usage of IDLE pin)
• Limp Home mode (with usage of IDLE and IN pins)
• Green Product (RoHS compliant)
• Safety features – Temperature Sensor and Monitoring – Serial communications using address feedback, 1 parity bit, frame counter & short frame detection
• 16-bit serial peripheral interface for control and diagnosis
• Daisy Chain capability SPI, also compatible with 8-bit SPI devices
• Package options: HTSSOP24, VFQFPN32
• Full ISO26262 compliant, ASIL-B systems ready

Description

The L9026 is an eight-channel IC, with 2 fixed HS drivers and 6 configurable HS/LS drivers designed for Automotive applications (LEDs and Relays) and compatible with resistive, inductive and capacitive loads. The device offers advanced diagnostic and protection functionalities such as: short to GND, open load, overcurrent, over- temperature detections. The 8 output channels can be either driven by SPI or by 2 dedicated parallel inputs. Limp home functionality is also featured, which allows using 2 selected drivers in particularly faulty conditions, such as SPI fault, micro fault or supply UV. Daisy chain compatible even with 8bit SPI is available. The device is able to guarantee operations under cranking scenario down to VBATT = 3 V and guarantees very low quiescent current under RESET condition. A serial peripheral interface (SPI) is used for control and configuration of the loads as well as of the device; besides, status feedback of all diagnostic functions is provided. For direct control and PWM there are two input pins available: these are connected to two defined outputs by default, but additional or different output mapping can be controlled by SPI. As reported above, the device is available in two package versions: HTSSOP24 and VFQFPN32. Only for the QFN package 2 additional pins are available for safety reasons. In details, the NRES pin is used to reset internal registers to their default values and the DIS pin is used to disable all channels. Product status link L9026 Product summary Order code L9026-B03N-TR Packing Tape & Reel Order code L9026-YO-TR Packing Tape & Reel Automotive configurable multi-channel relay driver 2HS + 6HS/LS L9026 Datasheet DS13397 - Rev 5 - March 2021 For further information contact your local STMicroelectronics sales office.

1 Block diagram

Figure 1. Block diagram

2 Application circuit

• Figure 2 reports L9026 with the HTSSOP24 version package
• Figure 3 shows the application of L9026 with the VFQFPN32 version package In the list of external components, the different parts are marked following the items reported below: 1. mandatory components for L9026 functionality 2. recommended components for EMC robustness 3. recommended components for ESD trials 4. recommended System component Note: recommended components may depend on the requirements at system levels and shall be confirmed by specific tests on the final application.

Figure 2. HTSSOP24 Application schematic

Figure 3. VFQFPN32 Application schematic Table 1. External components list for L9026 application circuit

50 V, Transient and load dump protection

3 Pins description

Figure 4. HTSSOP-24 pinout diagram

Figure 5. VFQFPN32 pinout diagram

Table 2. HTSSOP-24 pins list

1 VBATT Battery voltage

2 SOURCE0 HS Source 0

3 DRAIN7 LS/HS Drain 7

4 SOURCE7 LS/HS Source 7

5 DRAIN6 LS/HS Drain 6

6 SOURCE6 LS/HS Source 6

7 DRAIN5 LS/HS Drain 5

8 SOURCE5 LS/HS Source 5

9 IN1 Parallel command input 1

10 IN0 Parallel command input 0

11 GND Ground pin

12 IDLE Idle function

13 VDDIO IO supply

14 SO SPI output stream

15 CLK SPI clock

16 NCS SPI Chip Select

17 SI SPI input stream

18 DRAIN4 LS/HS Drain 4

19 SOURCE4 LS/HS Source 4

20 DRAIN3 LS/HS Drain 3

21 SOURCE3 LS/HS Source 3

22 DRAIN2 LS/HS Drain 2

23 SOURCE2 LS/HS Source 2

24 SOURCE1 HS Source 1

Table 3. VFQFPN32 pins list

1 DRAIN7 LS/HS Drain 7

2 SOURCE7 LS/HS Source 7

3 DRAIN6 LS/HS Drain 6

4 SOURCE6 LS/HS Source 6

5 DRAIN5 LS/HS Drain 5

6 SOURCE5 LS/HS Source 5

7 NRES NRES function – available only in VFQFPN32 package

8 DIS Channel disable – available only in VFQFPN32 package

12 GND Ground pin

13 IDLE Idle function

14 VDDIO IO supply

15 SO SPI output stream

16 CLK SPI clock

17 NCS SPI Chip Select

18 SI SPI input stream

19 DRAIN4 LS/HS Drain 4

20 SOURCE4 LS/HS Source 4

21 DRAIN3 LS/HS Drain 3

22 SOURCE3 LS/HS Source 3

23 DRAIN2 LS/HS Drain 2

24 SOURCE2 LS/HS Source 2

27 SOURCE1 HS Source 1

28 DRAIN1 HS Drain 1

29 VBATT Battery voltage

30 DRAIN0 HS Drain 0

31 SOURCE0 HS Source 0

Note: • In case of VFQFPN32 package, CFG_0.DIS_EN and bit CFG_0.NRES_N needs to be set through SPI.

• In case of HTSSOP24 package, NRES and DIS pins are not available; CFG_0.DIS_EN and bit CFG_0.NRES_N must be considered as reserved, kept at ‘0’.
• For both package options the exposed pad must be left floating to guarantee the reverse battery protection feature. L9026 Pins description DS13397 - Rev 5 page 8/60

4 Product characteristics

4.1 Absolute maximum ratings

the Absolute Maximum Ratings may also cause a decrease in reliability. exceeded. All voltages are referred to analog ground pin GND. Table 4. Absolute maximum rating capability

4.2 Latchup trials

4.3 Temperature range

Table 5. Temperature range All parameters are guaranteed, and tested, in the temperature range Tj -40 ÷ 150 °C (unless otherwise specified).

5 Input / Output

5.1 Parallel inputs (IN0, IN1)

Device has two input pins available. Each input pin is connected by default to one channel (IN0 to channel 2, IN1 to channel 3). Input Mapping Registers MAP_IN0 and MAP_IN1 can be programmed to connect different channels to each input pin. The signals driving the channels are an OR combination between PWM_SPI register status, PWM Generators (according to PWM Generator Output Mapping status), IN0 and IN1 (according to Input Mapping registers status). See Section 11 SPI for further details. The logic level of the input pins can be monitored via the status register STA_0. The Input Status Monitor is operative also when device is in Limp Home mode. If one of the Input pins is set to “high” and the IDLE pin is set to “low”, the device switches into Limp Home mode and activates the channel mapped by default to the input pins.

5.2 Idle pin (IDLE)

The IDLE pin is used to bring the device into Sleep mode operation when is set to “low” together with IN0, IN1 input pins being at “low” state. When IDLE pin is set to “low” while one of the input pins is set to “high” the device enters Limp Home mode. To ensure a proper mode transition, IDLE pin must be set for at least tIDLEFLT_max (transition from “high” to “low” or from “low” to “high”). Setting the IDLE pin to “low”, with both IN0 and IN1 also at “low” value, has the following consequences:

• Device goes in SLEEP MODE
• All registers in the SPI are reset to default values
• VDDIO and VBATT Under voltage detection circuits are disabled to decrease current consumption
• No SPI communication is allowed: SO pin remains in high impedance state also when NCS pin is active.

5.3 Reset pin (NRES, only in VFQFPN32 package option)

The NRES pin, available only for VFQFPN32 version, is the reset input for the device. The function uses the inverse logic, if the NRES pin is low, the device is held in an internal reset state, all outputs channels are disabled, and all registers are reset to their default values. An internal pull down will hold the NRES pin asserted in case of pin open. As default, the state of NRES pin is masked by the logic. The user must send a specific SPI frame to force the logic to take into account the state of NRES pin.

5.4 Enable (DIS, only in VFQFPN32 package option)

The DIS pin, available only for VFQFPN32 version, is used to enable / disable the output stages. When DIS pin is high, all channels are disabled if the pin is not masked. An internal pull up will hold the DIS pin asserted in case of pin open. When DIS pin is set low, all channels are enabled based on their configuration settings. As default, the DIS pin is masked by the logic. The user needs to send a specific SPI frame to force the logic to take into account the state of DIS pin. The status of DIS pin can be monitored reading the STA_0 register. The DIS pin can be connected to a general purpose output pin of the microcontroller or to an alternative safety circuit.

5.5 SPI communications (NCS, CLK, SI & SO)

The NCS, CLK, SI & SO pins provide serial communications between the device and the microcontroller. See Section 11 SPI for details on SPI features, device register functions and electrical characteristics. L9026 Input / Output DS13397 - Rev 5 page 11/60

5.6 Input / output electrical specifications

Table 6. Digital input/output electrical performance

6 Power supply

6.1 Overview

• VBATT (general supply for analog and digital part)
• VDDIO (supply for digital and output buffers) The supply lines are monitored against under voltage: in case under voltage condition is detected the IC reacts as per the following:
• An under voltage on VBATT supply voltage prevents the activation of the power stages.
• An under voltage on VDDIO supply prevents any SPI communication and SPI read/write registers are reset to default values. The combination of the different under voltage conditions are reported in Table 7.

Table 7. Supply ranges

6.2 Battery supply (VBATT)

This pin is the general supply for analog and digital part unless an undervoltage condition is detected on VBATT. the functional ranges dependent on battery supply voltage. Table 8. VBATT electrical performance

1. Possible degradation of electrical parameters linked to battery line. Full functional operation will resume without operator

intervention when battery voltage returns to Normal Operating Voltage Range. care has to be taken in PCB manufacturing to keep thermal dissipation to a reasonable level.

• For VBATT < VBATT (UV) the device is in a safety state (internal circuitries are on but all the outputs are off).
• For VBATT up to 40 V all the functions are granted with increased power dissipation and no reset is asserted during transient. L9026 Power supply DS13397 - Rev 5 page 13/60

6.3 Operating modes

• Sleep mode
• Idle mode
• Active mode
• Limp Home mode The transition between operation modes is determined according to the following levels and states:
• logic level at IDLE pin
• logic level at INn pins
• PWM_SPI.OUTn bits state
• CFG_1.ACT bit state
• MAP_PWM.OUTn and PWM_SEL.OUTn bits state The Figure 6 represents the possible transitions in the state diagram. The description is valid if the digital POR signal is de-asserted (indicated as POR_N in the register map). In case of POR = 0 transitions from Active to idle and from Limp Home to Sleep do not guarantee switch off behavior with functional timings. A POR condition is traced in a clear on read register in the STA_1.POR bit. The behavior of the device as well as some parameters may change depending on the operating mode of the device. Furthermore, due to the under voltage detection circuitry which monitors VBATT and VDDIO supply voltages, some changes within the same operation mode can be seen accordingly. In case of VBATT < VBATT(UV_L) and IDLE = IN0 = IN1 = high device doesn't go from IDLE state to ACTIVE state. Starting from Active state in the condition IDLE = ’0’ and INn = ’0’ (that corresponds to the transition Active to Sleep) to guarantee drivers turn OFF it is necessary also a SW reset. There are different options to observe the operation mode of the device:
• status of output channels
• status of SPI registers
• current consumption at VBATT pin (IVBATT)

Figure 6. State ddiagram

will be extended due to the mode transition latency. device functions (channels operability, SPI communication and SPI registers). Table 9. Functions availability in different supply conditions

6.4 Analog & Digital supply (VBATT)

VBATT) and the output loads. latched until its status is acknowledged by the microcontroller via SPI. Under voltage condition on VBATT influences the status of the channels as described in Table 7.

6.5 I/O Supply (VDDIO)

internal logic if VBATT is in under voltage condition. In case the voltage drops below VDDIO(UV) the under voltage mechanism is triggered and the bit STA_1. until its status is acknowledged by the microcontroller via SPI.

6.6 Power up

and the INn or IDLE pins are set to “high”.

6.7 Sleep mode

voltages. The current consumption is reduced to the IVDDIO(SLEEP) and IVBATT(SLEEP).

6.8 Idle mode

In Idle mode, the current consumption of the device reaches the parameters IVDDIO(IDLE) and IVBATT(IDLE). The internal voltage regulator is still working. ON diagnosis functions are not available. The output channels are switched OFF, independently of the supply voltages. When VDDIO is available, the SPI registers are working and SPI communication is possible. In Idle mode the DIAG_OVC_OVT bits are not cleared.

6.9 Active mode

Active mode is the normal operation mode when no Limp Home condition is set and it is necessary to drive some or all loads. Voltage levels of VDDIO and VBATT influence the behavior as described in detail in Section 6.1 Overview. Device current consumption is specified with IVDDIO(ACTIVE) and IVBATT(ACTIVE). In case CFG_1.ACT is set to “1”, the device enters in Active mode and remains in this state independently on the status of input pins, of internal PWM generators and PWM_SPI.OUTn bits. Otherwise, in case the bit CFG_1.ACT is not set, in order to move the device in Active mode all conditions below are needed:

• the IDLE pin set to “high”
• the outputs configured as driven either by external pins (through MAPIN0, MAPIN1 registers) or by SPI (at least one PWM_SPI.OUTn bit is set to “1”) or by the internal PWM generators (through MAP_PWM)
• at least one channel enabled In this scenario, the device returns to Idle mode as soon as IDLE pin set to “low”, all inputs pins are set to “low”, all PWM_SPI.OUTn bits are set to “0” and all the internal pwm generators are OFF. Being the IDLE pin asserted high, an under voltage condition on VDDIO supply brings the device into Idle mode once all INn input pins are set to “low”, on top of the setting of the bit CFG_1.ACT. L9026 Idle mode DS13397 - Rev 5 page 16/60

6.10 Limp Home mode

• IN0 is mapped as channel 2 input command, IN1is mapped as channel 3 input command
• MODE bits are set to “01B” (Limp Home mode)
• Overload and Over temperature diagnostics on channel 2 and 3 are available and the related DIAG_OVC_OVT bits can be read. Entering Limp Home mode from sleep means that all other registers are set to their default value and cannot be programmed as long as the device is in Limp Home mode (SPI in in read only mode) so far a special feature for Channel 2 and 3 is implemented and channels are able of auto-configuring as LS or HS depending on the configuration of the external load. Open in ON diagnosis is not performed in Limp Home mode. This is true also if Limp Home mode has been entered from Active mode and DIAG_OPL_ON_EN.OUTn bits are set to '1'. In this case, the diagnostic cycles will be performed only when back in ACTIVE mode. See Table 9 for a detailed overview of supply voltage conditions required to switch ON channels 2 and 3 during Limp Home. All other channels are kept OFF.

6.11 Power supply transition

Supply modes, as reported in Figure 7. Figure 7. Transition times block diagram

6.12 Reset

• VDDIO not present or below the undervoltage threshold VDDIO(UV)
• IDLE pin is set to “low” with both INn “low"
• A software reset (CFG_1.RST set to “1”) is commanded
• NRES pin is asserted (only available in VFQFPN32 package option and configured to sense the pin status) When the SPI registers are reset, all channels (except 2,3) are switched OFF and the Input Mapping configuration is also reset. This means channels 2, 3 are still commanded by IN0, IN1 respectively. For functional safety register DIAG_OVC_OVT and STA_1. VDDIO_UV, STA_1.VBATT_UV bits are not cleared by a reset command. One of the following conditions resets the whole internal logic;
• General internal supply failure (internal supply 3.3 V in UV or bandgap reference not correct)
• VDDIO < VDDIO(UV) and IN1 = 0 and IN0 = 0

6.13 Power supply electrical specifications

Table 10. Power supply electrical parameters

Parameter Description Test condition Min Typ Max Unit VDDIO pin VDDIO(OP) Logic Supply Operating range voltage fCLK = 8 MHz 3 - 5.5 V VDDIO(UV_RECOVERY) Analog supply threshold for recovery after battery undervoltage MISO from “low” to high impedance 2.7 2.85 3 V VDDIO(UV) Undervoltage shutdown MISO from “low” to high impedance 2.65 2.8 2.95 V IVDDIO(SLEEP) Logic supply current in Sleepmode VIDLE = 0; VINn = 0; VDDIO = 5 VTJ ≤ 85 °C - - 1 µA IVDDIO(SLEEP) Logic supply current in Sleep mode VIDLE = 0V; VINn = 0 V; VDDIO = 5 VTJ ≤ 150 °C - - 2 µA IVDDIO(IDLE) Logic supply current in Idle Mode VIDLE = 5 V; VINn = 0 V; VDDIO = 5 V; fCLK = 0 MHz; CFG_1.ACT = 0B; PWM_SPI.OUTn = 0B; DIAG_OFF_EN.OUTn = 0B - - 1.2 mA IVDDIO(IDLE) Logic supply current in Idle mode (COR) VIDLE = 5 V; VINn = 0 V; VDDIO = 5 V; fCLK = 0 MHz; CFG_1.ACT = 0B; PWM_SPI.OUTn = 0B; DIAG_OFF_EN.OUTn = 0B; VBATT = VDDIO - 1 V 2 - 16 mA IVDDIO(ACTIVE) Logic supply current in Active mode – channels OFF VIDLE = 5 V; VINn = 0 V; VDDIO = 5 V; fCLK = 0 MHz; CFG_1.ACT = 1B; PWM_SPI.OUTn = 0B; DIAG_OFF_EN.OUTn = 0B - 0.95 1.5 mA IVDDIO(ACTIVE_COR) Logic supply current in Active mode – channels OFF (COR) VIDLE = 5 V; VINn = 0 V; VDDIO = 5 V; fCLK = 0 MHz; CFG_1.ACT = 1B; PWM_SPI.OUTn = 0B; DIAG_OFF_EN.OUTn = 0B; VBATT = VDDIO - 1 V 12 - 20 mA tVDDIOUVFLT VDDIO undervoltage filter Covered bySCAN 9 14 19 µs Timings tIDLEFLT Idle filter time - 5 7 10 µs tSLEEP2IDLE Sleep to Idle delay - - - 10 µs tIDLE2SLEEP Idle to Sleep delay from IDLE pin to sleep External pull-down MISO to GND required - - 10 µs tIDLE2ACTIVE Idle to Active delay from INn or NCS pins to MODE = 11B - - 1 µs tACTIVE2IDLE Active to Idle delay from INn or NCS pins to MODE = 10B - - 150 µs tSLEEP2LH Sleep to Limp Home delay from INn pins to VDS = 10 % VBATT - - 10+tON µs tLH2SLEEP Limp Home to Sleep delay from INn pins to MODE = 00B External pull-down MISO to GND required. - - 150 µs tLH2ACTIVE Limp Home to Active delay from IDLE pin to MODE = 11B - - 10 µs tACTIVE2LH Active to Limp Home delay from IDLE pin to MODE = 01B - - 10 µs tACTIVE2SLEEP Active to Sleep delay from IDLE pin to MODE = 00B External pull-down MISO to GND required. - - 150 µs L9026 Power supply electrical specifications DS13397 - Rev 5 page 19/60

7 Power stages

activation) are determined according to the SPI settings of CFG_0 register. any potential between ground and VBATT. directly or through a reverse current blocking diode). The configuration can be chosen for each of these configurable channels individually via SPI. Figure 8. HS driver (left) and LS driver (right) configuration

7.1 Operating modes

The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature TJ.

7.1.1 Switching resistive modes

When switching resistive loads, the following switching times and slew rates can be considered.

Figure 9. Switching resistive loads

7.1.2 Inductive output clamp

allowed to go below VOUT_S(CL). The voltage clamping is necessary to prevent device destruction. To clarify this idea Figure 10 shows a concept drawing of the implementation. protects the device in all operative modes (Sleep, Idle, Active, Limp Home). Figure 10. Output clamp concept

7.1.3 Maximum load inductance

connected to the outputs are demagnetized at the same time.

7.2 Inverse current behavior

Inverse current (VOUTn_S > VOUTn_D) in high-side configuration may occur with channels in ON or in OFF state. protection, diagnostic) of unaffected channels.

7.3 Bulb inrush mode

current mat startup may trigger the overload diagnostic, switching the channel OFF. re-engagement procedure takes too long to transfer enough energy to activate the load. The IC provides means to overcome this issue by setting BIM.OUTn bit to “1”. once the tBIM is expired, unless a reset condition occurs (VDDIO_uv, hardware or software reset). Figure 11. Bulb inrush mode

7.4 PWM generators

Device has two independent PWM generators, which are defined as “PWM GEN” and “PWM LED” here below.

7.4.1 PWM GEN

setting is reported in Table 12. Table 11. Adjustment coefficients

• duty cycle (bits PWM_GEN_DC.DUTY_CYCLE) – 8 configuration bits are available, with 100/255 duty cycle resolution for each LSB – The maximum duty cycle achievable is 100% (PWM_GEN_DC.DUTY_CYCLE set to “11111111B”) – In case the duty cycle is changed, the next target is applied once the previous PWM period is over and the new one is started. Once a new target is programmed, the behavior above is valid also if the current duty is 100% while when the current duty is 0% the new target value is applied immediately.
• frequency (bits CFG_1.PWM_DIV_GEN) – 2 configuration bits are available to select the frequency among 4 target values

Table 12. PWM GEN generator available frequencies

• Channels driven by PWM GEN (PWM_SEL and PWM_MAP registers) The correct sequence to use the PWM generator is:
• define the frequency divider through CFG_1.PWM_DIV_GEN bit.
• define duty cycle control register through PWM_GEN_DC register.
• set up channel output control through PWM_SEL register (PWM GEN corresponds to 0)
• define channels driven by PWM selected in PWM_SEL through mapping register PWM_MAP In order to clarify how to select the source that can drive the channels command, the driving tree with all possible sources (ie PWM generators, SPI and parallel inputs) is reported in Figure 12. L9026 PWM generators DS13397 - Rev 5 page 23/60

Figure 12. Driving tree

7.4.2 PWM LED

with PWM GEN, using CFG_2.FR_ADJ bits described in Table 11.

• duty cycle (bits PWM_LED_DC.DUTY_CYCLE) – 8 configuration bits are available, with 100/255 duty cycle resolution for each LSB – The maximum duty cycle achievable is 100% (PWM_LED_DC.DUTY_CYCLE set to “11111111B”) – In case the duty cycle is changed, the next target is applied once the previous PWM period is over and the new one is started. Once a new target is programmed, the behavior above is valid also if the current duty is 100% while when the current duty is 0% the new target value is applied immediately.
• frequency (bits CFG_1.PWM_DIV_LED) – 2 configuration bits are available to select the frequency among 4 target values

Table 13. PWM LED generator available frequencies

• Channels driven by PWM LED (PWM_SEL and PWM_MAP registers) The correct sequence to use the PWM LED generator is:
• define the frequency divider through CFG_1.PWM_LED_GEN bit.
• define duty cycle control register through PWM_LED_DC register.
• set up channel output control through PWM_SEL register (PWM LED corresponds to 0)
• define channels driven by PWM selected in PWM_SEL through mapping register PWM_MAP

7.5 Power stages electrical specifications

Table 14. Power stages electrical parameters

Parameter Description Test condition Min Typ Max Unit VS(CL) Source to GND Output clamping voltage HS IL = 10 mA; VBATT = VOUT_Dn = 7 V; High- Side Configuration -18 -17 -16 V IL(OFF) Output leakage current (each channel) TJ = 150 °C VBATT = 0 V; VDDIO = 0 V; VSOURCE = 0 V; VDS = 28 V; TJ up to 150 °C -3 0 3 µA IL(OFF)_HS Output leakage current (each channel) TJ = 150 °C VBATT = 28 V; VDDIO = 0 V; VSOURCE = 0 V; VDS = 28 V; TJ up to 150°C – High side case -3 - 3 µA I(OFF)_HS Output current (each channel) in High side case High side configuration, Power OFF, VSOURCE = 0 V -70 - -30 µA I(OFF)_HS Output current (each channel) in High side case High side configuration, Power OFF, VSOURCE = 2.5V -10 - 10 µA Timing tDELAY(ON) Turn-ON delay (from INn pin or bit to VOUT = 90% VBATT) (Channels used as Low-Side) RL = 50 Ω VBATT= 14 V Active or Limp Home mode 3 5 7 µs tDELAY(OFF) Turn-OFF delay (from INn pin or bit to VOUT = 10% VBATT) (Channels used as Low-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 2.5 10 21 µs tON Turn-ON time (from INn pin or bit to VOUT = 10% VBATT) (Channels used as Low-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 7 15 35 µs tOFF Turn-OFF time (from INn pin or bit to VOUT = 90% VBATT) (Channels used as Low-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 4 - 40 µs dV/dtON Turn-ON slew rate VDS = 70% to 30% VBATT (Channels used as Low-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 0.35 1 2.2 V/µs -dV/dtOFF Turn-OFF slew rate VDS = 30% to 70% VBATT (Channels used as Low-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 0.15 1.3 3.4 V/µs -dV/dtOFF Turn-OFF slew rate VDS = 30% to 70% VBATT Gate kill condition RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 12 - 35 V/µs (Channels used as Low-Side) tDELAY(ON) Turn-ON delay (from INn pin or bit to VOUT = 10% VBATT) (Channels used as High-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 1.2 3.5 7.5 µs tDELAY(OFF) Turn-OFF delay (from INn pin or bit to VOUT = 90% VBATT) (Channels used as High-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 2 10 21 µs tON Turn-ON time (from INn pin or bit to VOUT = 90% VBATT) (Channels used as High-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 7 16 25 µs tOFF Turn-OFF time (from INn pin or bit to VOUT = 10% VBATT) (Channels used as High-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 5 19 35 µs dV/dtON Turn-ON slew rate VDS = 30% to 70% VBATT (Channels used as High-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 0.25 1 1.9 V/µs -dV/dtOFF Turn-OFF slew rate VDS = 70% to 30% VBATT (Channels used as High-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 0.25 - 2.5 V/µs -dV/dtOFF Turn-OFF slew rate VDS = 70% to 30% VBATT Gate kill condition (Channels used as High-Side) RL = 50 Ω; VBATT= 14 V; Active or Limp Home mode 6 - 30 V/µs tINRUSH Bulb Inrush Mode restart time Active mode; Covered by SCAN 29 40 51 µs L9026 Power stages electrical specifications DS13397 - Rev 5 page 26/60

Table 15. PWM electrical parameters

8 Protection functions

8.1 Overload protection

• I L(OVL0) between channel switch ON and tOVLINDS1
• I L(OVL1) after tOVLIN

Figure 13. Overload thresholds Every time the channel is switched OFF the over load current threshold is set back to IL(OVL0). set back to “0” internally after de-latching the channel. Please refer to Figure 14 for details. Figure 14. Latch off in overload condition

8.2 Over temperature protection

OFF the channel in over temperature in order to prevent destruction.

8.3 Over temperature and over load in Limp Home mode

channel is still required to be on, in case of Over Load the channels restart at every tRETRY.

8.4 Reverse polarity protection

diode of each DMOS. The reverse current through the channels has to be limited by the connected loads. In order to sustain the Reverse polarity condition the exposed pad of device must be left electrically floating.

8.5 Electrical characteristics

Table 16. Over temperature and over load electrical parameters

Symbol Description Test condition Min Typ Max Unit (Channels used as High-Side) IL(OVL1_HS) Over Load detection current (Channels used as High-Side) TJ = 150 °C 0.7 - 1.2 A tOVLIN Over Load threshold switch delay time Covered by SCAN 110 170 260 µs tOFF(OVL) Over Load shut-down delay time BIM.OUTn = 0B 4 7 11 µs TJ(SC) Thermal shut-down temperature - 182 192 202 °C tRETRY Restart time in Limp Home mode Covered by SCAN 29 41 52 ms tOVC Restart time in Limp Home mode Covered by SCAN - - 50 µs L9026

Electrical characteristics

DS13397 - Rev 5 page 30/60

9 Diagnosis

The SPI interface provides diagnosis information about the device and the load status. Each channel diagnosis information is independent of other channels. A faulty condition on one channel has no influence on the diagnostic of other channels in the device.

9.1 Over load and Over temperature

When either an Over Load or an Over Temperature occurs on one channel, the diagnosis bit DIAG_OVC_OVT is set accordingly. The channel latches OFF and must be reactivated setting corresponding DIAG_OVC_OVT_RLWn bit to “1”. The writing operation is necessary to remove the fault as a consequence of the fact that DIAG_OVC_OVT register is clear on write.

9.2 OFF diagnosis

This diagnosis is available only in Active mode. The device is able to detect two kind of faults in OFF, open load and short (to battery in HS configuration or to ground in LS configuration). This diagnosis is available upon SPI request; Once the diagnosis has been started on one or more channels, a new eventual diagnosis request is ignored until the ongoing cycle is finished. The diagnosis strategy is implemented over two different phases:

• First the IC distinguishes between faulty and no faulty condition.
• In case of trouble found in the previous step, a specific procedure is put in place to detect the nature of the fault. The diagnosis is slightly different depending on a LS or HS configured output. The strategy in LS configuration is reported below and referred to Figure 15; the HS case is quite similar, except for the order in which pull-up and pull-down current generators are activated and for the pin involved (SOURCEn for a HS configured channel, DRAINn for a LS).
• This first phase lasts for t OFF1LS. The current generator marked with ‘pldw’ (driven by dw_on) is active while the current generator marked as ‘plup’ is off.. In this condition, if the drain voltage remains above the threshold VDS(OL), the comparator output is low which means that a load is present. If the drain voltage decreases below the threshold, instead, the comparator flags the presence of a fault.
• This second phase lasts for t OFF2LS. After the first diagnosis step the output of the comparator is set to ‘1’ if a faulty condition has been found. The current generator marked with ‘plup’ (driven by the signal up_on) is activated while ‘pldw’ is off. In case, after the pull-up activation, the drain voltage rises and overcomes the comparator threshold again, an Open Load fault is reported. If the voltage remains constant and equal to zero for the whole diagnosis time, instead, a Short to ground fault is recognized. L9026 Diagnosis DS13397 - Rev 5 page 31/60

Figure 15. OFF diagnosis circuit

9.3 Open load at ON

On each channel it is possible to request the open load at on diagnosis. This diagnosis is designed having in mind a specific case of high side channels driving LEDs kept fully ON. on a low side configured channel. the PWM driving signal) and inductive loads (to avoid unwanted power dissipations during switch OFF transients).

9.3.1 Open load at ON (diagnosis mechanism)

The diagnosis cannot be run on more channels simultaneously, but it can work only on one channel at a time. This can be activated by setting the bit corresponding to the desired channel in the DIAG_OPL_ON_EN register. During the diagnostic loop the channel is switched off every tOPLCYC for a maximum time of tOPLEN. the source of the channel, as can be seen from Figure 16. battery and the Vds value remains stable for the whole diagnosis time interval. channel is anyway restarted. The OPL ON diagnosis lasts just a tOPLEN time in the worst case scenario, i.e. when the open load is detected. corresponding request has been accepted. the corresponding bit DIAG_OPL_ONn is set.

channels will not be executed and SPI command will have no effect. Figure 16. Open load at ON circuit

9.3.2 Open load at ON bit

• “0” = no Open Load at ON state detected, or the channel is OFF when the diagnosis is performed
• “1” = Open Load at ON state detected This register is clear on read. An SPI read is necessary to clear the faulty information. Once the DIAG_OPL_ON flag is set, it remains asserted until a new diagnostic cycle is completed when the fault is no longer present, and the diagnostic register is read through SPI. L9026 Open load at ON DS13397 - Rev 5 page 33/60

9.4 Electrical parameters

Table 17. Output status and open load ON electrical parameters

10 Limp Home mode

The Limp is intended to handle limited functionality of the device in critical faulty situations. IN0, IN1 is over, being the IDLE pin still de-asserted, the device will reach Sleep mode. Figure 17. Possible system configuration during normal operating conditions lines mark the signals path.

Figure 18. Possible system configuration during Limp mode

11 SPI

The SPI interface is used to configure the device, control the outputs and read diagnostic and status registers.

11.1 SPI protocol

lines: SO, SI, CLK and NCS. Data is transferred by the lines MOSI and MISO at the rate given by CLK. communication because is meaningless. of CLK while the output data is shifted out on line MISO (SO) at the falling edge of CLK. (CPOL=’0’, CPHA = ‘0’). End of SPI access is defined by a rising edge of NCS. structure of MOSI and MISO frames is shown in Section 11.5 SPI frame structure. implements an out-of-frames strategy. Figure 19. SPI out-of-frame protocol eventual frames are ignored and MISO pin remains in high impedance.

11.2 Daisy chain capability

single NCS and MOSI lines, getting back data from a single MISO line as reported in the Figure 20. Figure 20. SPI Daisy chain configuration consistent and error free once the MNCS is de-asserted. Figure 21. SPI message in daisy chain configuration

11.3 SPI electrical specifications

Table 18. SPI electrical parameters

Parameter Description Test condition Min Typ Max Unit Input pull up resistor at NCS pin RNCS L-input pull-up resistor at NCS pin VNCS = 0.8 V 40 58 95 KΩ Input pull down resistor at pin RCLK Input pull-down resistor on CLK VCLK = 2 V 50 - 140 KΩ RSI Input pull-down resistor on SI VSI = 2 V 50 - 140 KΩ Output characteristics VSO(L) L level output voltage ISO = -1.5 mA 0 - 0.4 V VSO(H) H level output voltage ISO = 1.5 mA VDDIO -0.4 - VDDIO V ISO(OFF) Output tristate leakage current VNCS = VDDIO VBATT = 0 V -1 - 1 μA ISO(OFF) Output tristate leakage current VNCS =VDDIO VBATT = VDDIO -1 - 1 μA Timings tCSN(lead) Enable lead time (falling NCS to rising CLK) VDDIO = 4.5 V or VBATT > 7 V 200 - - ns tCSN(lag) Enable lag time (falling CLK to rising NCS) VDDIO = 4.5 V or VBATT > 7 V 200 - - ns tCSN(td) Transfer delay time (rising NCS to falling NCS) VDDIO = 4.5 V or VBATT > 7 V 650 - - ns tSO(en) Output enable time (falling NCS to SO valid) VDDIO = 4.5 V or VBATT > 7 V; CL = 20 pF at MISO pin - - 200 ns tSO(dis) Output disable time (rising NCS to SO tristate) VDDIO = 4.5 V or VBATT > 7 V; CL = 20 pF at MISO pin - - 200 ns fCLK Serial clock frequency VDDIO = 4.5 V or VBATT > 7 V - - 8 MHz tCLK(H) Serial clock “high” time VDDIO = 4.5 V or VBATT > 7 V 45 - - ns tCLK(L) Serial clock “low” time VDDIO = 4.5 V or VBATT > 7 V 45 - - ns tSI(su) Data setup time (required time MOSI to falling CLK) VDDIO = 4.5 V or VBATT > 7 V 30 - - ns tSI(h) Data hold time (falling CLK to SI) VDDIO = 4.5 V or VBATT > 7 V 30 - - ns L9026 SPI electrical specifications DS13397 - Rev 5 page 39/60

11.4 SPI timing diagram

Figure 22. SPI timing diagrams

11.5 SPI frame structure

11.5.1 MOSI frame structure

• 1 command bit R/W, ‘1’ for write, ‘0’ for read
• 5 ADDRESS bits
• 8 DATA bits
• 1 PARITY bit, odd parity, calculated on bit [2:15]
• 1 FR_CNT frame counter bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W ADDRESS DATA PAR FR_CNT

11.5.2 MISO frame structure

• 1 ERR error bit, ‘1’ if an error happened in the previous transmission, ‘0’ otherwise
• 5 ADDRESS bits
• 8 DATA bits
• 1 PARITY bit, odd parity, calculated on bit [2:15]
• 1 FR_CNT frame counter bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERR ADDRESS DATA PAR FR_CNT L9026 SPI timing diagram DS13397 - Rev 5 page 40/60

11.6 SPI register

11.6.1 Register structure

CHIP_ID Register name: CHIP_ID Address: Global Base Address + 0x00 Description: Chip ID register Field name Type Bit Offset Bit Width Reset Value Reset Sources Description CHIP_ID RO 0 8 AA Bit 0->7 00100010 BA Bit 0->7 00101010 BB Bit 0->7 01010101 X 8 bit chip identifier CFG_0 Register name: CFG_0 Address: Global Base Address + 0x01 Description: Configuration 0 Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RW 2 6 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:2], MSB refers to channel 7 0: (default) OUTn low side 1: OUTn high side DIS_EN RW 1 1 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV 0: (default) DIS pin masked 1: DIS pin not masked NRES_EN RW 0 1 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV 0: (default) NRES pin masked 1: NRES pin not masked CFG_1 Register name: CFG_1 Address: Global Base Address + 0x02 Description: Configuration 1 Field name Type Bit Offset Bit Width Reset Value Reset Sources Description RST WO 7 1 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Reset 0: (default) Normal operation 1: Execute Reset command (self clearing) ACT RW 6 1 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV active mode 0: (default) Normal operation or device leaves Active Mode 1: device enters and hold in Active Mode NU RO 2 4 0x00 X - L9026 SPI register DS13397 - Rev 5 page 41/60

PWM_DIV_LED RW 0 2 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV 00: (default) PWM_FRQ=122.5Hz 01: PWM_FRQ=245.1Hz 10: PWM_FRQ=490.2Hz 11: PWM_FRQ=980.4Hz CFG_2 Register name: CFG_2 Address: Global Base Address + 0x03 Description: Configuration 2 Field name Type Bit Offset Bit Width Reset Value Reset Sources Description NU RO 4 4 0x00 X - FR_ADJ RW 2 2 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV 00: NO FREQ ADJUSTMENT 01: -15% ON SELECTED FREQUENCY 10: +15% ON SELECTED FREQUENCY 11: NO FREQ ADJUSTMENT PWM_DIV_GEN RW 0 2 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV 00: (default) PWM_FRQ=122.5Hz 01: PWM_FRQ=245.1Hz 10: PWM_FRQ=490.2Hz 11: PWM_FRQ=980.4Hz BIM Register name: BIM Address: Global Base Address + 0x04 Description: Bulb Inrush Mode register configuration Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RW 0 8 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:0], MSB refers to channel 7 0: (default) no BIM active 1: BIM active RESERVED_1 Register name: RESERVED_1 Address: Global Base Address + 0x05 Description: Reserved Field name Type Bit Offset Bit Width Reset Value Reset Sources Description UNUSED RO 0 8 0x00 X - PWM_SPI Register name: PWM_SPI Address: Global Base Address + 0x06 Description: Power output control register L9026 SPI register DS13397 - Rev 5 page 42/60

Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RW 0 8 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:0], MSB refers to channel 7 0: (default) Output OFF 1: Output ON MAP_IN0 Register name: MAP_IN0 Address: Global Base Address + 0x07 Description: IN0 input mapping register Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RW 0 8 0x04 OUT2 mapped on IN0 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:0], MSB refers to channel 7 0: OUTn not driven by IN0 1: OUTn driven by IN0 MAP_IN1 Register name: MAP_IN1 Address: Global Base Address + 0x08 Description: IN1 input mapping register Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RW 0 8 0x08 OUT3 mapped on IN1 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:0], MSB refers to channel 7 0: OUTn not driven by IN1 1: OUTn driven by IN1 MAP_PWM Register name: MAP_PWM Address: Global Base Address + 0x09 Description: Internal PWM generator mapping register Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RW 0 8 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:0], MSB refers to channel 7 0: OUTn not driven by internal PWM generator 1: OUTn driven by internal PWM generator PWM_SEL Register name: PWM_SEL Address: Global Base Address + 0x0A Description: Internal PWM generator selection register L9026 SPI register DS13397 - Rev 5 page 43/60

Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RW 0 8 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:0], MSB refers to channel 7 0: (default) PWM_GEN selected for OUTn 1: PWM_LED selected for OUTn PWM_GEN_DC Register name: PWM_GEN_DC Address: Global Base Address + 0x0B Description: PWM GEN duty cicle setting Field name Type Bit Offset Bit Width Reset Value Reset Sources Description DUTY_CYCLE RW 0 8 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV b00000000, PWM GEN OFF b11111111, PWM GEN fully ON duty = 100/255*LSB PWM_LED_DC Register name: PWM_LED_DC Address: Global Base Address + 0x0C Description: PWM LED duty cicle setting Field name Type Bit Offset Bit Width Reset Value Reset Sources Description DUTY_CYCLE RW 0 8 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV b00000000, PWM GEN OFF b11111111, PWM GEN fully ON duty = 100/255*LSB DIAG_OFF_EN Register name: DIAG_OFF_EN Address: Global Base Address + 0x0D Description: OFF Diagnostic enable register Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RW 0 8 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:0], MSB refers to channel 7 0: (default) OFF diagnosis not active 1: OFF diagnosis active DIAG_OPL_ON_EN Register name: DIAG_OPL_ON_EN Address: Global Base Address + 0x0E Description: Open Load in ON Diagnostic enable register L9026 SPI register DS13397 - Rev 5 page 44/60

Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RW 0 8 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:0], MSB refers to channel 7 0: (default) OL diagnosis not active 1: OL diagnosis active DIAG_OVC_OVT_RLW Register name: DIAG_OVC_OVT_RLW Address: Global Base Address + 0x0F Description: Overcurrent/overtemperature error Clear on write Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn WO 0 8 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:0], MSB refers to channel 7 0: (default) clear on write not active 1: clear on write active STA_0 Register name: STA_0 Address: Global Base Address + 0x10 Description: Status Register 0 Field name Type Bit Offset Bit Width Reset Value Reset Sources Description NU RO 7 1 0x00 X - DIS RO 6 1 0x00 POR_N Echo status of DIS input (if properly configured) X - 5 1 X X - IDLE RO 4 1 0x00 POR_N Echo status of IDLE input IN1 RO 3 1 0x00 POR_N Echo status of IN1 input IN0 RO 2 1 0x00 POR_N Echo status of IN0 input OUT_ON_ERR RLR 1 1 0x00 POR_N 0: normal 1: overcurr/overtemp detected on a whatever channel OUT_OFF_ERR RLR 0 1 0x00 POR_N 0: normal 1: OFF state diag fail on whatever channel STA_1 Register name: STA_1 Address: Global Base Address + 0x11 Description: Status Register 1 L9026 SPI register DS13397 - Rev 5 page 45/60

Field name Type Bit Offset Bit Width Reset Value Reset Sources Description NU RO 5 3 0x00 X - POR RLR 4 1 0x00 POR_N 0: POR condition not detected 1: POR condition detected VDDIO_UV RLR 3 1 0x00 POR_N 0: no VDDIO undervoltage 1: VDDIO undevoltage detected VBATT_UV RLR 2 1 0x00 POR_N 0: no VBATT undervoltage 1: VBATT undevoltage detected MODE RO 0 2 0x00 POR_N IC operating mode 00: Sleep Mode 01: Limp Home Mode 10: Idle Mode 11: Active Mode DIAG_OVC_OVT Register name: DIAG_OVC_OVT Address: Global Base Address + 0x12 Description: Overcurrent/overtemperature detection Register Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RLW 0 8 0x00 POR_N Channel [7:0], MSB refers to channel 7 0: (default) no fail 1: overcurr/overtemp detected DIAG_OPL_OFF Register name: DIAG_OPL_OFF Address: Global Base Address + 0x13 Description: Driver Open load detection in off state Register Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RLR 0 8 0x00 POR_N Channel [7:0], MSB refers to channel 7 0: (default) no fail 1: open load detected DIAG_OPL_ON Register name: DIAG_OPL_ON Address: Global Base Address + 0x14 Description: Driver Open load detection in on state Register L9026 SPI register DS13397 - Rev 5 page 46/60

Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RLR 0 8 0x00 POR_N Channel [7:0], MSB refers to channel 7 0: (default) no fail 1: open load detected DIAG_SHG Register name: DIAG_SHG Address: Global Base Address + 0x15 Description: Driver shorted load detection in OFF state Register Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RLR 0 8 0x00 POR_N Channel [7:0], MSB refers to channel 7 0: (default) no fail 1: STG/STB detected Note: Global Base Address to be considered as 0x00 L9026 SPI register DS13397 - Rev 5 page 47/60

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 12.1 VFQFPN32 (5x5x1 mm exp. pad down 3.5x3.5) package information Figure 23. VFQFPN32 (5x5x1 mm exp. pad down 3.5x3.5) package outline

Package information

DS13397 - Rev 5 page 48/60

Table 19. VFQFPN32 (5x5x1 mm exp. pad down 3.5x3.5) mechanical data

Notes: 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. All Dimensions are in millimeters. 3. Terminal A1 identifier and terminal numbering convention shall conform to JEP95 SPP-002. Terminal A1 identifier must be located within the zone indicated on the outline drawing. Topside terminal A1 indicator may be a molded, or metalized feature. Optional indicator on bottom surface may be a molded, marked or metallized feature. 4. Outlines with “D” and “E” increments less than 0.5 mm should be registered as “stand alone” outlines. These outlines should use as many of the algorithms and dimensions states in the design standard as possible to insure predictability in manufacturing. 5. Inner edge of corner terminals may be chamfered or rounded in order to achieve minimum gap “k”. This feature should not affect the terminal width “b”, which is measured L/2 from the edge of the package body. 6. “N” is the maximum number of terminal positions for the specified body size. Depopulation is allowed, but only under the following conditions. – Depopulation scheme must be consistent in each quadrant of the package. – Non-symmetric variations should be broken out as separate mechanical outline variations, including depopulation graphics. 7. A1 is defined as the distance from the seating plane to the lowest point on the package body (standoff). 8. Dimension D2 and E2 refer to exposed pad. 9. For Tolerance of Form and Position see Table 19. 10. Critical dimensions: 10.1 L1 11. Dimensions “b” and “L” are measured at terminal plating surface. 12. For Symbols, Recommended Values and Tolerances see Table below: (ACCORDING TO PACKAGE OR JEDEC SPEC IF REGISTERED) L9026 VFQFPN32 (5x5x1 mm exp. pad down 3.5x3.5) package information DS13397 - Rev 5 page 50/60

1. The pin #1 identifier must be present on the top surface of the package by using indentation mark or other

feature of package body. Exact shape and size of this feature are optional.

Revision history

Table 21. Document revision history 06-Aug-2020 1 Initial release.

• Order Code in Product summary;
• Table 4. Absolute maximum rating capability;
• Table 5. Temperature range;
• Table 8. VBATT electrical performance;
• Table 9. Functions availability in different supply conditions;
• Table 16. Over temperature and over load electrical parameters;
• Table 17. Output status and open load ON electrical parameters;
• Table 18. SPI electrical parameters. Minor text changes. 09-Oct-2020 3 Added Errata. 10-Nov-2020 4 Removed watermark "Restricted". 23-Mar-2021 5 Updated:
• Figure 2. HTSSOP24 Application schematic;
• Figure 3. VFQFPN32 Application schematic;
• Table 10. Power supply electrical parameters. Minor text changes in:
• Table 6. Digital input/output electrical performance;
• Table 18. SPI electrical parameters. L9026 DS13397 - Rev 5 page 54/60

Contents

DS13397 - Rev 5 page 56/60

DS13397 - Rev 5 page 57/60