L8602

L8602 UTC | Alldatasheet

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UNISONIC TECHNOLOGIES CO., LTD L8602 Preliminary LINEAR INTEGRATED CIRCUIT www.unisonic.com.tw 1 of 8 Copyright © 2018 Unisonic Technologies Co., Ltd QW-R123-023.a LOW POWER 6 STAGE FET LNA AND MIXER BIAS CONTROLLER  DESCRIPTION The UTC L8602 is a programmable low power depletion mode FET bias and mixer controller intended primarily for satellite Low Noise Blocks (LNBs). Designed to provide system flexibility the UTC L8602 can be programmed to bias six low noise amplifier (LNA) stages or four LNA and two active mixer stages, allowing the UTC L8602 to be used in several system designs. Combining an advanced IC process and packaging techniques, the UTC L8602 helps minimize power consumption, component cost and PCB area whilst enhancing overall reliability.  FEATURES * Low quiescent supply current, 1.6mA typical * Six stage FET bias controller, two configurable as mixer stages * Operating range of 3.0V to 8.0V * Amplifier FET drain voltages set at 2.0V, mixer drain voltage set at 0.25V * Amplifier FET drain current selectable from 0 to 15mA, mixer current from 0 to 7.5mA * Switchable FET’s for power management * FET drain voltages and currents held stable over temperature and VCC variations * FETs protected against overstress during power-up and power-down. * Internal negative supply generator allowing single supply operation (available for external use) * Low external component count  ORDERING INFORMATION Ordering Number Lead Free Halogen Free Package Packing L8602G-Q20-4040-R L8602G -Q20-4040-R QFN-20(4×4) Tape Reel L8602G-Q20-4040-R L8602G -Q20-4040-R QFN-20(4×4) Tape Reel (1) R: Tape Reel (3) G: Halogen Free and Lead Free, L: Lead Free L8602G-Q20-4040-R (1)Packing Type (2)Package Type (3)Green Package

L8602 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 2 of 8 www.unisonic.com.tw Q W - R 1 2 3 - 0 2 3 . a  MARKING  PIN CONFIGURATION VCC RCAL1RCALM 16181920 6 7 8 10 CSUB Top View RCAL2 Cnb2 Cnb1 GND CSUB 2 14G2 G5  PIN DESCRIPTION PIN NO. PIN NAME DESCRIPTION

1 D2 To D of fet 2

2 G2 To G of fet 2

3 D3 To D of fet 3

4 G3 To G of fet 3

5 R CALM Connect 68kohm to set Id3/6 to 5mA

6 GND Ground

7 Cnb1 connect an external cap to cnb2

8 Cnb2 connect an external cap to cnb1

9 CSUB connect an external cap to produce -2.5V

10 R CAL2 Connect 36kohm to set Id2/5 to 10mA

11 R CAL1 Connect 36kohm to set Id1/4 to 10mA

12 G6 To G of fet 6

13 D6 To D of fet 6

14 G5 To G of fet 5

15 D5 To D of fet 5

16 G4 To G of fet 4

17 D4 To D of fet 4

18 V CC Power supply

19 D1 To D of fet 1

20 G1 To G of fet 1

L8602 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 3 of 8 www.unisonic.com.tw Q W - R 1 2 3 - 0 2 3 . a  BLOCK DIAGRAM

L8602 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 4 of 8 www.unisonic.com.tw Q W - R 1 2 3 - 0 2 3 . a  ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL RATINGS UNIT Supply Voltage VCC -0.6 ~ +10 V Supply Current ICC 100 mA Power Dissipation P D 600 mW Operating Temperature Range T OPR -40 ~ +85 °C Storage Temperature Range T STG -40 ~ +150 °C Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.  ELECTRICAL CHARACTERISTICS (Measured at TA=25°C, VCC=3.3V(Note 1), RCAL1=RCAL2=36KΩ (setting ID1/2/4/5 to 10mA), RCALM=68KΩ (setting ID3/6 to 5mA) unless otherwise stated) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Operating Voltage Range V CC 3.0 8.0 V ICC I D1-6=0 1.6 4.0 mA Supply Current ICC(L) I D1-6=10mA, no RCALM 62 64 mA Oscillator Frequency F OSC 100 260 600 kHz Gate Characteristics Gate (G1 to G6, resistor RCALM ot present) Current Range I G -100 +500 uA Voltage Low V G(L) I D=12mA, IG=-10uA -3.0 -2.5 -2.0 V Voltage High V G(H) I D=8mA, IG= 0 0 0.7 1.0 V Voltage Disabled (Note 1) V G(DIS) I D=0, IG=-10uA, VRCAL1-2=3.0V -3.0 -2.5 -2.0 V Gate (G3 and G6, resistor RCALM present) Current Range I G -100 +500 uA Voltage Low V G(L) I D=6mA, IG=-10uA -3.0 -2.5 -2.0 V Voltage High V G(H) I D=4mA, IG=0 0 0.7 1.0 V Voltage Disabled (Note 1) V G(DIS) I D=0, IG=-10uA, VRCAL2=V 3.0V -3.0 -2.5 -2.0 V Drain Characteristics Drain (D1 to D6, resistor RCALM not present) Current Range I D 0 15 mA Current Operating I D(OP) Standard Application Circuit 8 10 12 mA Current Disabled (Note 1) I D(DIS) V D=0, VRCAL=3.0V 10 uA Voltage Operating V D(OP) I D=10mA 1.8 2.0 2.2 V Drain Characteristics Drain (D3 and D6, resistor RCALM present) Current Range I DM 0.5 7.5 mA Current Operating I DM(OP) Standard Application Circuit 4 5 6 mA Current Disabled (Note 1) I DM(DIS) VD=0, VRCAL=3.0V, RCALM not present 10 uA Voltage Operating V DM(OP) I D=5mA 0.15 0.3 0.45 V

L8602 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 5 of 8 www.unisonic.com.tw Q W - R 1 2 3 - 0 2 3 . a  ELECTRICAL CHARACTERISTICS (Cont.) (Measured at TA=25°C, VCC=3.3V(Note 1), R CAL1=RCAL2=36KΩ (setting ID1/2/4/5 to 10mA), RCALM=68KΩ (setting ID3/6 to 5mA) unless otherwise stated) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT R CAL (1 and 2) Disable Threshold (Note 1) V RCAL(DIS) 1.8 2.7 3.0 V Input Current I RCAL(DIS) V RCAL=3.0V 1.7 10 uA R CALM Disable Threshold (Note 1) R CALM(DIS) 1.5M 3.3M 5.0M Ω RCALM Range R CALM 39k 390k Ω Voltage and Temperature dependence (RCALM not present) delta ID vs. VCC dI D/dVCC V CC=3.3 to 8.0V 1.2 %/V delta ID vs. TOP dI D/dTOP T OP=-40°C to +85°C 0.05 %/°C delta VD vs. VCC dV D/dVCC VCC=3.3 to 8.0V 0.05 %/V delta VD vs. TOP dV D/dTOP TOP=-40°C to +85°C 50 ppm/° C Output Noise Drain Voltage V D(NOISE) CGATE-GND=10nF, CDRAIN-GND=10nF 0.02 Vpk-pk Gate Voltage V G(NOISE) CGATE-GND=10nF, CDRAIN-GND=10nF 0.005 Vpk-pk Notes: 1. To disable FET stages 3 and 6, pin RCAL2 must be set to 3V or above and pin RCALM should be open circuit. 2. The characteristics are measured using up to three external reference resistors, R CAL1, RCAL2 and R CALM, wired from pins R CAL1/2/M to ground. Resistor R CAL1 sets the drain current of FETs 1 and 4. If R CALM is not present, resistor RCAL2 sets the drain currents of FETs 2, 3, 5 and 6. If R CALM is present, resistor RCAL2 sets the drain currents of FETs 2 and 5 and RCALM sets the drain currents of FETs 3 and 6. 3. The negative bias voltages are gener ated on-chip using an internal oscillator. Two external capacitors, CNB and CSUB of value 47nF are required for this purpose. 4. The QFN-20(4×4) package exposed pad must either be connected to Csub or left open circuit. 5. Noise voltage measurements are made with FETs and gate and drain capacitors of value 10nF in place. Noise voltages are not measured in production. 6. ESD sensitive, handling precautions are recommended.

L8602 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 6 of 8 www.unisonic.com.tw Q W - R 1 2 3 - 0 2 3 . a  LNB SYSTEM DIAGRAM LeftRight 2*2 mux VerticalHorizontal  TYPICAL APPLICATION CIRCUIT The UTC L8602 series of devices are designed to meet the bias requirements of GaAs and HEMT FETs commonly used in satellite receiver LNBs with a minimu m of external components whilst operating from a minimal voltage supply and using minimal current. The truth table below shows the function of UTC L8602’s features. L8602 truth table RCAL Pin Resistor Termination 1st LNA Stages FET Stage 2nd LNA Stages 3rd LNA/ Mixer Stages FEATURE RCAL1 R CAL2 RCALM Bias 1 Bias 4 Bias 2 Bias 5 Bias 3 Bias 6 GND GND OPEN on on on on on on 3V GND OPEN off off on on on on

6 LNA stages to provide

standard bias to the GaAs or HEMT FET’s GND 3V OPEN on on off off off off Power down FET groups for LNA switching or power saving. 3V 3V OPEN off o ff off off off off GND GND GND on on on on mixer mixer GND 3V GND on on off off mixer mixer 3V GND GND off off on on mixer mixer

4 LNA stages to provide

standard bias to the GaAs or HEMT FET’s plus 2 active mixer stages 3V 3V GND off off off off mixer mixer

L8602 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 7 of 8 www.unisonic.com.tw Q W - R 1 2 3 - 0 2 3 . a  TYPICAL APPLICATION CIRCUIT (Cont.) UTC L8602 Vcc RcalM RCAL1 CNB1 CNB2 CSUB RCAL2 C* C1 10nF C* C2 10nF JF2 VCC RCAL1 RCAL2 36k 36kCNB 47nF CSUB 47nF* Stripline Elements Gnd UTC L8602 in 6 LNA mode The bias stages are split up into two groups, with the drain current of each group set by an external R CAL resistor. RCAL1 sets the drain currents of stages 1 and 4, whilst RCAL2 sets the drain currents of stages 2, 3, 5 and 6. To ensure that the mixer function is disabled the RCALM pin should be left open circuit. UTC L8602 Vcc RCALM RCAL1 CNB1 CNB2 CSUB RCAL2 C* C1 10nF C* C2 10nF JF2 VCC RCAL1 RCAL2 36k 36kCNB 47nF CSUB 47nF* Stripline Elements Gnd C*C3 10nF C*C4 10nF JFM VLO RCALM 68k UTC L8602 in 4 LNA and 2 active mixer mode The bias stages are split up into three groups, with the drain current of each group set by an external RCAL resistor. RCAL1 sets the LNA drain currents of stages 1 and 4, and R CAL2 sets the drain currents of LNA stages 2 and 5. R CALM sets the mixer drain currents of stages 3 and 6.

L8602 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 8 of 8 www.unisonic.com.tw Q W - R 1 2 3 - 0 2 3 . a UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. UTC reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.