L8229 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin description
- 3 Electrical Characteristics
- 3.1 Absolute maximum ratings
- 3.2 Operating ratings
- 3.3 General electrical characteristics
- 3.3.1 Output Drivers (OUTA or OUTB)
- 3.3.2 Control Logic pins
- 3.3.3 Analog Input Pins
- 3.3.4 General
- 4 L6219_HI and L6219_8 modes
- 5 L6219_HI and L6219_8 Electrical characteristics
- 5.1 DC specifications
- 5.2 AC/transient specifications
- 6 L6219_HI mode
- 6.1 Input Logic (I0 and I1)
- 6.2 Phase
- 6.3 Current Sensing
- 6.4 Single-pulse Generator
- 6.5 Output Stage
- 6.6 Vs, Vcc, Vref
- 7 L6219_8 mode
- 7.2 Mixed Decay
- 8 L8229_0 and L8229_1 modes
- 8.1 Serial interface specification
Features
■ Flexible Motor Driver configurations: – Dual Full Bridge for one bipolar Stepping motor. – Dual or single DC motor driver. ■ Programmable by two input pins to achieve one of the following functionalities: – Pin to pin compatible with ST L6219 or – Stepping motor direct control with 8 current levels or – Driver parameters control by means of Serial Port. ■ Mixed Decay. ■ Micro stepping function. ■ BCD5 technology (No Charge Pump required). ■ Supply Range from 8V to 38V. ■ IOUT up to 1.2A (1.5A peak). ■ RDSon= 0.85Ω (typ) for each switch. ■ Input logic level compatible with 3.3V or 5V control signals. ■ Package: PwSSO24.
Description
This IC is designed to be very flexible in driving Stepping or DC motors. By connecting to Vcc or to Gnd two program pins (pin 7 and 18) the user has the possibility to set up the device in different configurations. 1. The first configuration is an identical application of ST L6219 but with increased current. In this configuration L8229 provides a continuous current of the output stage up to 1.2A (1.5A peak). 2. The second configuration allows a functionality similar to previous one but with the possibility of choosing 8 different current levels to perform a more accurate stepping functionality. This is achieved by multiplexing the input pins dedicated to set the level of the current. Additionally the user can set the mixed mode decay for current recirculation. 3,4. The third and fourth configurations are intended to provide a very flexible programming for several parameters useful to drive different kind of Stepping and DC motors. This is achieved by means of a serial port interface that allows the user to configure the following parameters: a) Current levels (32 values for each bridge). b) Current direction. c) Type of decay for Stepping motors (Mix/Slow) or for DC motors (Fast/Slow). d) Vref input (Ext/Int). e) Vref divider (:5/:10). f) Blanking time (4 values). g) Oscillator freq divider (4 values). h) Off time (32 values). i) Fast decay time (16 values). j) Syncronous rectification. The functionalities of the two configurations are identical except that the internal bit address (first bit of SPI words) can be programmed to be 1 or 0: this enables two different L8229 to share a common serial bus. Order code PwSSO24 Part number Package Packing L8229 PwSSO24 Tube Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s) L8229 Contents
1 Block diagram
Figure 1. Block Diagram Note: The sensing resistors used for the stepping motor configurations must be not inductive.
2 Pin description
Figure 2. Pin Connection (Top view) relative to third and fourth configuration (L8229_0 and L8229_1). Table 1. Pin Description 1 OUT1A Motor Driver Bridge 1 Output A. 2 OUT2A Motor Driver Bridge 2 Output A. 3 SENSE2 Motor Driver Bridge 2 Sense Resistor. 4 COMPIN2 Current Comparator input for Bridge2. 5 OUT2B Motor Driver Bridge 2 Output B.
8 IO2 STB SCLK
I02: Current level control bit for Bridge 2. STB: Strobe input pin for current setting. SCLK: Clock input pin for serial protocol. 9I 1 2 I 1 2 S D I I12: Current level control bit for Bridge 2. SDI: Data input pin for serial protocol.
10 PHASE2 PHASE2 nCS PHASE2: Direction input control pin for Bridge 2. nCS: Chip Select input pin for serial protocol.
11 VREF2 VREFDEC VREF2
VREF2: Reference voltage input for Bridge 2. 12 RC2 RC2 FAULT RC2: Toff input pin for Bridge 2. FAULT: This pin is high when a generic fault is present. 13 VCC Logic and Low voltage analog Supply. 14 RC1 RC1 nRESET RC1: Toff input pin for Bridge 1. nRESET: Input pin for reset of serial port.
15 VREF1 VREFCOM VREF1
VREF1: Reference voltage input for Bridge 1. 16 PHASE1 PHASE1 OSC PHASE1: Direction input control pin for Bridge 1. OSC: Input for external oscillator used for timings.
17 I11 I11 PWM2
I11: Current level control bit for Bridge 1.
18 PROG2
(see following Programmable Modes table).
20 I01 I01 PWM1
I01: Current level control bit for Bridge 1. 21 OUT1B Motor Driver Bridge 1 Output B. 22 COMPIN1 Current Comparator input for Bridge1. 23 SENSE1 Motor Driver Bridge 1 Sense Resistor. 24 VS Supply voltage for output stages. Table 1. Pin Description (continued)
Table 2. Programmable modes
00 L6219 compatible
3 Electrical Characteristics
listed in their respective functionality descriptions. the lower thermal threshold temperature. not be driven when supplies are on.
3.1 Absolute maximum ratings
3.2 Operating ratings
Table 3. Absolute maximum ratings Ipeak Motor Driver Output Peak Current (see Note (1)).
- This peak current is intended as start up current for max 1 second with D.C. ≤10%
Table 4. Operating ratings (0°C ≤ Tj ≤ 125°C)
3.3 General electrical characteristics
3.3.1 Output Driver s (OUTA or OUTB)
Table 4. Operating ratings (0°C ≤ Tj ≤ 125°C) (continued) Table 5. Output Drivers (OUTA or OUTB)
3.3.2 Control Logic pins
3.3.3 Analog Input Pins
3.3.4 General
Table 6. Control Logic pins Table 7. Analog Input Pins Table 8. General
Obsolete Product(s) - Obsolete Product(s) L8229 L6219_HI and L6219_8 modes
4 L6219_HI and L6219_8 modes
When configured in one of these modes the device has a functionality similar to ST L6219 with some improvements. The output stage is made by LDMOS devices instead of the BJT present in ST L6219. This allows a reduced saturation drop and an higher current handling with similar power dissipation. Additionally the recirculation diodes are internally available as a part of the LDMOS structure. In case of: a) Undervoltage detection (UVD) or b) Thermal shutdown (TSD), the outputs will be in Hi-Z mode (all outputs off) respectively until the supplies voltage goes over the UV threshold plus hysteresis or the themperature decreases below TSD threshold minus hysteresis. In case of: c) Overcurrent detection (OCD) the outputs will be in Hi-Z mode (all outputs off) and will remain in this condition until the device is reset by turning off and on VCC supply voltage. Common electrical characteristics of both L6219_HI and L6219_8 modes are listed below, while specific characteristics are listed in their respective functionality descriptions.
5 L6219_HI and L6219_8 Electrical characteristics
5.1 DC specifications
5.2 AC/transient specifications
Table 9. DC specifications Table 10. AC/transient specifications
6 L6219_HI mode
In the L6219_HI mode, the device is pin and function compatible with the ST L6219 device. by connecting the exposed pad to a proper heat sink. current can also be completely switched off.
6.1 Input Logic (I0 and I1)
the logic inputs is left open, the circuit will treat it as a high level input.
6.2 Phase
from OutA through the motor winding to OutB.
6.3 Current Sensing
according to the current level chosen with signals I0 and I1. comparator input, the comparator output goes high, triggering the pulse generator. Table 11. Input Logic (I0 and I1)
suitable sense resistor to prevent current range over the maximum.
6.4 Single-pulse Generator
the time components Rt and Ct.
6.5 Output Stage
motor current particularly with low current levels.
6.6 Vs, Vcc, Vref
The circuit will stand any order of turn-on or turn-off of the supply voltages Vs and Vcc. Normal dV/dt values are then assumed. Preferably, Vref should be tracking Vcc during power-on and power-off if Vs is established. Figure 3. Ton and Toff
7 L6219_8 mode
inputs for decoding current levels settings for Bridge 2. equally spaced but are choosen to approximate a sinusoidal wave. start driving only upon the rising or falling edges of STB.
7.2 Mixed Decay
- Slow decay (current is recirculated throught the low side drivers) when VREFDEC > 0.94Vcc.
- A mix of Fast followed by Slow de cay when 0.33Vcc < VREFDEC < 0.94Vcc.
- Fast decay (current is recirculated from Sense to Vs) when VREFDEC < 0.33Vcc.
Table 12. Current levels
Table 13. AC/Transient Specification Table 14. Timing specifications Table 12. Current levels (continued)
Obsolete Product(s) - Obsolete Product(s) L8229 L8229_0 and L8229_1 modes
8 L8229_0 and L8229_1 modes
When in these modes, the device can be programmed via a serial interface. This allows a very precise microstepping functionality as well as the control of several parameters related to the motor functionality. In this configuration there is also the possibilty of driving two DC motors by means of two pulse width modulated (PWM) control signals. The parameters that can be set are the following: 1. Current levels (32 values for each bridge). 2. Current direction. 3. Type of decay for stepping motor (Mix/Slow). 4. Vref input (Ext/Int) 5. Vref divider (:5/:10). 6. Blanking time (4 values). 7. Oscillator freq di vider (4 values). 8. Off time (32 values). 9. Fast decay time (16 values). 10. Synchronous rectification (Active/Passive/LowSide/Off). 11. Choose of driving a Stepping or DC motor. 12. Possibility of paralleling bridges (in DC motor drive). 13. Slow or fast decay (in DC motor drive). 14. Possibility of setting outputs in brake mode. 15. Possibility of asserting Sleep mode to r educe current consumption and put outputs in HI-Z. When in L8229 modes, pin 12 (FAULT) is used to provide a "Generic Fault" signal that is intended as a warning for the user. In case of: a) Undervoltage detection (UVD): no action is taken on output bridges and the device will be working, leaving to the user the action of stopping the output bridges functionality. During UVD event, the Generic Fault signal is pulled high. b) Thermal shutdown (TSD): output bridges will be in Hi-Z mode (all outputs off) until the temperature decreases below TSD threshold minus hysteresis. During TSD event, the Generic Fault signal is pulled high. c) Over current detection (OCD): output bridges will be in Hi-Z mode. Depending on the motor (Stepping or DC according to W2 bit 14), the OCD status will be latched as follows: – for stepping motor driving the OCD st atus will be latched until SPI is reset by means of nRESET pin. – for DC motor driving th e OCD status will be latched until next positive PWM edge occurs. For both above cases, the Generic Fault signal is pulled high until the OCD status persists.
8.1 Serial interface specification
are for test mode purposes only. and serial data input (SDI). presented to their appropriate functions in a parallel mode. different from 16 bits), without the use of nCS. The outputs of the serial input port shall not "glitch" during any operation. Table 15. DC Specifications Table 16. AC/Transient Specifications
Figure 8. SPI Operations Table 17. SPI Timing specifications
8.2 SPI Bit definition
8.2.1 Word Description
8.2.2 W0 (OPERATIVE: Bit 2=0, Bit 1=0)
This word is mainly used to fix the current level and direction in the bridge. Table 18. Word Description
0 CHIP ADDRESS
present on the same board and a single nCS line is used). present on the same board and a single nCS line is used). Table 19. W0
0 CHIP ADDRESS 0
present on the same board and a single nCS line is used.
1 WORD ADDRESS 1 0 This is the LSB of th e two bits used to address the word
2 WORD ADDRESS 2 0 This is the MSB of the two bits used to address the word
3 DAC1 BIT 1 (LSB) 0 LSB for DAC intended to regulate the current of Bridge 1
4 DAC1 BIT 2 0 BIT2 for DAC intended to regulate the current of Bridge 1
5 DAC1 BIT 3 0 BIT3 for DAC intended to regulate the current of Bridge 1
6 DAC1 BIT 4 0 BIT4 for DAC intended to regulate the current of Bridge 1
7 DAC1 BIT 5 (MSB) 0 MSB for DAC intended to regulate the current of Bridge 1
8 PHASE 1 0 Controls the direction of current flow for Bridge1. A logic 0 level causes current flow from A (source) to B (sink).
9 DAC2 BIT1 (LSB) 0 LSB for DAC intended to regulate the current of Bridge 2
8.3 W1 (PARAMETERS: Bit 2=0, Bit 1=1)
This word is mainly used to set motor related parameters.
10 DAC2 BIT 2 0 BIT2 for DAC intended to regulate the current of Bridge 2
11 DAC2 BIT 3 0 BIT3 for DAC intended to regulate the current of Bridge 2
12 DAC2 BIT 4 0 BIT4 for DAC intended to regulate the current of Bridge 2
13 DAC2 BIT 5 (MSB) 0 MSB for DAC intended to regulate the current of Bridge 2
14 PHASE 2 0 Controls the direction of current flow Bridge 2. A logic HIGH level causes current flow from A (source) to B (sink).
15 PARALLEL OUTPUT 0 This bit must be set to 1 when otputs are paralled to drive a single DC
Table 19. W0 (continued) Table 20. W1 present on the same board and a single nCS line is used. 1 WORD ADDRESS 1 0 This is the LSB of t he two bits used to address the word. 2 WORD ADDRESS 2 0 This is the MSB of the two bits used to address the word. 3 NSLEEP 0 This bit is used to decide if the device should exit sleep mode. 4 OFF1 0 LSB for fixing the To ff time (see following Table 32). 5 OFF2 0 BIT 2 for fixing the Toff time (see following Table 32). 6 OFF3 0 BIT 3 for fixing the Toff time (see following Table 32). 7 OFF4 0 BIT 4 for fixing the Toff time (see following Table 32). 8 OFF5 0 MSB for fixing the Toff time (see following Table 32). 9 FASTDEC1 0 LSB for fixing the Fast Decay time (see following Table 31). 10 FASTDEC2 0 BIT 2 for fixing the Fast Decay time (see following Table 31). 11 FASTDEC3 0 BIT 3 for fixing the Fast Decay time (see following Table 31). 12 FASTDEC4 0 MSB for fixing the Fast Decay time (see following Table 31). 13 SYNCRECT1 0 LSB to decide the rectification mode (see following Table 35). 14 SYNCRECT2 0 MSB to decide the rectification mode (see following Table 35).
15 Brake 0 This bit is used to put outputs in brake mode
8.4 W2 (FUNCTIONAL: Bit 2=1, Bit 1=0)
Table 21. W2 present on the same board and a single nCS line is used. 1 WORD ADDRESS 1 0 This is the LSB of the two bits used to address the word. 2 WORD ADDRESS 2 0 This is the MSB of the two bits used to address the word.
5 REFERENCE INT/EXT 0 This bit is used to decide if the reference voltage will be internal (0) or
7 BLANK LSB 0 This is the LSB bit used to fix the Blanking time (see following
10 OSC MSB 0 This is the MSB bit used to fix the Oscillator values (see following
11 TEST 1 0 This bit is used for trim mode. 12 TEST 2 0 This bit is used for trim mode. 13 TEST 3 0 This bit is used for trim mode.
14 STEP/DC 0 This bit is used to set the drive of a Stepping Motor (0) or a DC Motor
15 SLOW/FAST (DC mot) 0 This bit is used to decide if Slow (0) or Fast (1) decay is applied to DC
Obsolete Product(s) - Obsolete Product(s) L8229 L8229_0 and L8229_1 modes 8.4.1 Reading back SPI. When W2 bit 11 to 13 are to 111, read back from SPI is enabled. This function is to check the actual data in W0 and W1; W2 can’t be read back. To read back the following procedure is requested: 1. Set PROG1=1, PROG2=0 2. Write W0 and W1 to SDI 3. Write W2 (with bits 11, 12, 13 set to 111) to SDI. This enables read back mode from SPI. 4. Write 0001 1111 1111 1111 to SDI (the first three bits mean that W0 is requested to be read out, the other bits have no sense just to fill the blank bits). This allows to check if the SDI output is W0 bit3~15. 5. Write W2 (with bits 11, 12, 13 set to 111) to SDI. This enables read back mode from SPI. 6. Write 0101 1111 1111 1111 to SDI (the first three bits mean that W1 is requested to be read out, the other bits have no sense just to fill the blank bits). This allows to check if the SDI output is W1 bit3~15. If the data to be read out are the same as the data write in, it means write function of SPI is right.
9 SPI programming
W2 bit 14. Default is stepping motor drive. The device can be awoken from the sleep mode by means of the bit 3 of W1. note that Brake mode overcomes Nsleep mode.
9.1 Current Control
power up, the default is the internal 2V. Table 22. Motor mode selected by W2
0 Stepping motor
1 DC motor
Table 23. Nsleep mode selected by W1
0 Sleep
Table 24. Brake mode selected by W1 Table 25. Vref mode selected by W2
(LSB) (13 to 9) as in following table. Table 26. Range mode selected by W2
0 Range = 10
1 Range = 5
Table 27. Current direction selected by W0 Table 28. Current levels selected by W0 for DAC
9.2 Timings Control
select the external oscillator frequency or it's dividing by either 2 or 4. The switching blanking time for masking transient can be selected by W2 bits 7 and 8. Table 28. Current levels selected by W0 for DAC (continued) Table 29. Oscillator frequency selected by W2
01 E x t
10 E x t / 2
11 E x t / 4
Table 30. Blanking time selected by W2
Fast decay timing is set by W1 bits 9 (LSB) to 12 (MSB). Setting Toff to be smaller than Tfast will result in fast decay only. Table 31. Fast decay time selected by W1 Table 32. Toff time selected by W1
Table 32. Toff time selected by W1 (continued)
9.3 Decay Modes and Synchronous Rectification
For DC motor drive, W2 bit 15 allows to choose slow or fast decay. recirculation, SYNC OFF recirculation, and LOW SIDE recirculation. happen because of FAST SYNC recirculation (that reverse the conduction of the bridge). rectification can't be used when in Slow Decay mode. Table 33. Stepping decay mode selected by W2
0 Mixed decay
1 Slow decay
Table 34. DC decay mode selected by W2 Table 35. Sync rectification selected by W1
00 A c t i v e (1)
- Only for Mixed Decay mode.
10 O f f
during Active Sync rectification. away from Rsense, as in SLOW recirculation. Figure 9. Active and Passive synchronous rectification during Mixed Decay.
Obsolete Product(s) - Obsolete Product(s) L8229 SPI programming The output states during these cases of recirculation could be summarized as below: (only OUTA to OUTB current flowing is described)
9.4 Mixed Decay
1) ACTIVE SYNC recirculation could be divided in following cases. 1a) No reverse current detected during Toff 1b) Reverse current detected during Fast Recirculation of Toff 1c) Reverse current detected during Slow Recirculation of Toff HA on HB off LA off LB on Current increasing in the load. All off Anticross state (fast recirculation through LA and HB body diodes). HA off HB on LA on LB off FAST SYNC recirculation through DMOS till end of fast decay time. HA off HB off LA on LB off Anticross state (fast recirculation through LA DMOS and HB body diode). HA off HB off LA on LB on SLOW SYNC recirculation till end of Toff. HA off HB off LA off LB on Anticross state (slow recirculation through LA body diode and LB DMOS). HA on HB off LA off LB on Current increasing in the load. HA on HB off LA off LB on Current increasing in the load. All off Anticross state (fast recirculation through LA and HB body diodes). HA off HB on LA on LB off FAST SYNC recirculation through DMOS till reverse current is detected. All off Hi-Z state till end of Toff. HA on HB off LA off LB on Current increasing in the load. HA on HB off LA off LB on Current increasing in the load. All off Anticross state (fast recirculation through LA and HB body diodes). HA off HB on LA on LB off FAST SYNC recirculation through DMOS till end of fast decay time. HA off HB off LA on LB off Anticross state (fast recirculation through LA DMOS and HB body diode). H A o f f H B o f f L A o n L B o n SL OW S Y N C r e c i r c u l a t i o n t i l l r eve r s e c u rr e n t i s d e t e c t e d . All off Hi-Z state till end of Toff. HA on HB off LA off LB on Current increasing in the load.
Obsolete Product(s) - Obsolete Product(s) SPI programming L8229 2) - PASSIVE SYNC recirculation could be divided in following cases: 2a) The reverse current (if present) does not exceed the regulated value (Note: this case is identical to ACTIVE SYNC case 1a) 2b) The reverse current exceeds the regulated value during FAST recirculation. (Note: if the current exceed the regulated value during SLOW recirculation, no action is taken and the behaviour will be that of case 2a) 3) - SYNC OFF recirculation has only one case: HA on HB off LA off LB on Current increasing in the load. All off Anticross state (fast recirculation through LA and HB body diodes). HA off HB on LA on LB off FAST SYNC recirculation through DMOS till end of fast decay time. HA off HB off LA on LB off Anticross state (fast recirculation through LA DMOS and HB body diode). HA off HB off LA on LB on SLOW SYNC recirculation till end of Toff. HA off HB off LA off LB on Anticross state (slow recirculation through LA body diode and LB DMOS). HA on HB off LA off LB on Current increasing in the load. HA on HB off LA off LB on Current increasing in the load. All off Anticross state (fast recirculation through LA and HB body diodes). HA off HB on LA on LB off FAST SYNC recirculation through DMOS till reverse current reaches the regulated value). All off Hi-Z state till end of Toff. HA on HB off LA off LB on Current increasing in the load. HA on HB off LA off LB on Current increasing in the load. All off Fast recirculation through LA and HB body diodes till end of fast decay time. HA off HB off LA off LB on Slow recirculation through LA body diode and LB DMOS till end of Toff. HA on HB off LA off LB on Current increasing in the load.
Obsolete Product(s) - Obsolete Product(s) L8229 SPI programming 4) LOW SIDE recirculation has only one case:
9.5 Slow Decay
When in Slow Decay, Active Synchronous rectification can't be used since current is not expected to be reversed because of BEMF . Therefore only Passive, Off or Low side recirculation cases can be selected. 1) ACTIVE SYNC recirculation is not allowed. 2) PASSIVE SYNC recirculation 3) SYNC OFF 4) LOW SIDE is identical to PASSIVE SYNC. HA on HB off LA off LB on Current increasing in the load. All off Fast recirculation through LA and HB body diodes) till end of fast decay time. HA off HB off LA on LB on SLOW SYNC recirculation till end of Toff. HA off HB off LA off LB on Anticross state (slow recirculation through the LA body diode and LB DMOS). HA on HB off LA off LB on Current increasing in the load. HA on HB off LA off LB on Current increasing in the load. HA off HB off LA off LB on Anticross state (slow recirculation through LA body diode and LB DMOS). HA off HB off LA on LB on SLOW SYNC recirculation till end of Toff. HA off HB off LA off LB on Anticross state (slow recirculation through the LA body diode and LB DMOS). HA on HB off LA off LB on Current increasing in the load. HA on HB off LA off LB on Current increasing in the load. HA off HB off LA off LB on Slow recirculation (through the LA body diode and LB DMOS) till end of Toff HA on HB off LA off LB on Current increasing in the load.
10 DC Motor Driver operation
description, the motor drive will be in voltage mode only. drive a single DC motor, the W0 bit 14 (PHASE2) will not be used as well as pin 17 (PWM2). The drives are powered by VS. the H bridge are allowed to conduct simultaneously. protection turnoffs due to the initial current spike resulting from circuit capacitance. When OCD happens, outputs are placed in Hi_Z untill next PWM positive edge occurs. lower thermal threshold temperature. Table 36. DC Motor Drivers - DC Specifications
- The current limitation is applied to the bottom H bridge LDMO S only, therefore over current protection applies to motor
current, but no short circuit protection exists against shorts from the DC motor outputs to ground or to VS. Table 37. DC Motor Drivers - AC/Transient Specifications Table 38. DC Motor Drivers Truth Table
Table 38. DC Motor Drivers Truth Table (continued)
conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 10. PowerSSO24 Mechanical Data & Package Dimensions (1) “D and E1” do not include mold flash or protusions. (2) No intrusion allowed inwards the leads.
Table 39. Document revision history 17-Feb-2005 1 Initial release. 10-Aug-2005 2 Many modify of texts and table. Corrected some errors/imprecisions in the whole document. 30-May-2006 4 Added note at the table 2. 12-Sep- 2006 5 Applied new graphic design template.