L8200

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UNISONIC TECHNOLOGIES CO., LTD L8200 Preliminary LINEAR INTEGRATED CIRCUIT www.unisonic.com.tw 1 of 6 Copyright © 2014 Unisonic Technologies Co., Ltd QW-R123-017.c CONFIDENTIAL, SUPPLIDE UNDE NDA SINGLE LNB-BIAS, CONTROL AND POWER MANAGEMENT SOLUTION  DESCRIPTION The UTC L8200 is a single chip power management and control solution for LNB’s. The highly integrate solution provides all the required FET and mixer bias, control detection and decoding, local oscillator switching and a stable power supply for the IF amplifier an additional support functions. Packaged in a small 16 pin QFN package or 20 pin HTSSOP package the UTC L8200 only requires 3 external components providing a very small compact solution. Being at the heart of the LNB monitoring the control, power management and env ironmental conditions the UTC L8200 is able to provide reliable solution eliminating effects such as false switching and over loading.  FEATURES * Single chip LNB bias, control and power management * Integrated regulated supply for LNB * Zero Gate FET switching * Voltage detection for polarization switching * 22kHz tone detector with signal rejection for band switching * Programmable mixer and FET bias  ORDERING INFORMATION Ordering Number Package Packing Lead Free Halogen Free L8200L-N20-R L8200G-N20-R HTSSOP-20 Tape Reel L8200L-Q16-3030-R L8200G-Q16-3030- R QFN-16(3×3) Tape Reel

L8200 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 2 of 6 www.unisonic.com.tw Q W - R 1 2 3 - 0 1 7 . c  MARKING INFORMATION PACKAGE MARKING HTSSOP-20 QFN-16(3×3)  PIN CONFIGURATION RcalA RcalM GND VINGM DM VOUT HB LB CSUB Top View 1 20 NC DM GM NC NC RcalA RcalM GND VIN VOUT HB LB CSUB NC GNDGND  PIN DESCRIPTION Pin No. PIN NAME DESCRIPTION QFN-16 HTSSOP-20 1 1 G1 To Gate of fet 1 2 2 D1 To Drain of fet 1 3 3 D2 To Drain of fet 2 4 5 G2 To Gate of fet 2 5 6 D3 To Drain of fet 3 6 7 G3 To Gate of fet 3 7 8 DM To Drain of mix fet 8 9 GM To Gate of mix fet 9 12 CSUB Connect an external cap to produce -2.5V 10 13 LB To Low band switch output 11 14 HB To High Low band switch output 12 15 V OUT 5V output terminal 13 16 V IN Power supply (include both voltage and tone signal) 14 17 GND Ground 15 18 RcalM Connect 22kohm to set Idm to 10mA 16 19 RcalA Connect 22kohm to set Id1, Id2, Id3 to 10mA 4, 10, 11, 20 NC NC

L8200 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 3 of 6 www.unisonic.com.tw Q W - R 1 2 3 - 0 1 7 . c  ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL RATINGS UNIT Supply Voltage V IN -0.6~25 continuous V Supply Current I IN 120 mA Power Dissipation HTSSOP-20 PD 1.3 W QFN-16(3×3) 2 W Operating Temperature Range T OPR -40~+85 °C Storage Temperature Range T STG -40~+150 °C Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.  ELECTRICAL CHARACTERISTICS Measured at TA=25°C, VIN=13V, RcalA=RcalM=22kΩ(setting lds to 10 mA) unless otherwise specified. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Supply Voltage Operating Range V IN 8 22 V Supply Current No Load Supply Current (Note 1) ICC Id1=Id2=Idm=0mA 2 3 mA QFN-16(3×3) 95 mA Max Bias Load Current (Note 2) Id1 or Id2+Id3+Idm 40 mA Max Osc Load Current (Note 2) LB or HB 50 mA Max Iout Load Current (Note 2) 50 mA Vout V OUT Vin=10.5V~21V, Iout=30mA 4.75 5 5.25 V Substrate Voltage V SUB (Internally generated), Isub=0mA -3.0 -2.5 -2.0 V Isub=-20uA -2.0 V Vpol Threshold V pol Applied via Vin pin 14.1 14.7 15.4 V Pol Switching Speed T pol Vin(low)=13V, Vin (High)=18V 1 ms Output Noise Drain Voltage Cgate-gnd=4.7nF, Cdrain-gnd=10nF 0.02 Vpk-pk Gate Voltage ICgate-gnd=4.7nF, Cdrain-gnd=10nF 0.005 Vpk-pk Tone Detector Tdetect Threshold V TONE Test Circuit 1 100 170 300 mV Rejection Freq (Note 3) Test Circuit 1, V(AC)in=1Vp/p sq.w. 1.0 7.5 kHz LO Output Stage LB Vout Low VLB II=0, Test Circuit 1, Tone enabled -0.01 0 0.01 V LB Vout High II=50mA, Test Circuit 1, Tone enabled 4.5 5.0 5.25 V HB Vout Low VHB II=0, Test Circuit 1, Tone enabled -0.01 0 0.01 V HB Vout High II=50mA, Test Circuit 1, Tone enabled 4.5 5.0 5.25 V

L8200 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 4 of 6 www.unisonic.com.tw Q W - R 1 2 3 - 0 1 7 . c  ELECTRICAL CHARACTERISTICS (Cont.) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Gate Characteristics G1 Output Voltage Off V GIO Id1=0, Vin=14V, ig1=0 -0.05 0 0.05 V Voltage Low V GIL Id1≤12mA, Vin=15.5V, Voltage High V GIH Id1 ≥8mA, Vin=15.5V, Ig1=0 0.4 0.65 1.0 V G2 Output Voltage Off V G2O Id2=0, Vin=15.5V, ig2=0 -0.05 0 0.05 V Voltage Low V G2L Id2≤12mA, Vin=14V, Voltage High V G2H Id2 ≥8mA, Vin=14V, Ig2=0 0.4 0.65 1.0 V G3 Output Voltage Low V G3L Id3/m ≤12mA, Ig3/m=-10uA -3.0 -2.5 -2.0 V Voltage High V G3H Id3/m ≥8mA,Ig3/m=0 0.4 0.5 1.0 V Drain Characteristics D1 Output Voltage High V D1 Id1=10mA, Vin=15. 5V 1.8 2.0 2.2 V Leakage Current I LEAK1 Vd1=0.5, Vin=14V 10 uA D2 Output Voltage High V D2 Id2=10mA, Vin=14V 1.8 2.0 2.2 V Leakage Current I LEAK2 Vd2=0.5, Vin=15.5V 10 uA D3 Output Voltage High V D3 Id3=10mA, Vin=15. 5V 1.8 2.0 2.2 V Dm Output Voltage High V DM Idm=10mA 0.5 0.6 0.7 V D1, 2, 3 and M Delta Vd vs VIN ∆VDV V IN=9~21V 0.5 %/V Delta Vd vs TJ ∆VDT T J=-40~+85°C 50 ppm FET Current Range Id1, Id2 & Id3 0 15 mA Mixer Current Range Idm 0 10 mA Drain Current I D Id1, Id2, Id3 & Idm, RcalA & RcalM=22kΩ 8 10 12 mA Delta Id vs Vcc ∆IDV Vcc=9~21V 0.5 %/V Delta Id vs TJ ∆IDT T J=-40~+85°C 0.05 %/°C Notes: 1. These parameters are related to Rcal values 2. The total combined load currents should not exceed the stated maximum load current. 3. The UTC L8200 series will also reject DiSEqC and other common switching tone bursts.

L8200 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 5 of 6 www.unisonic.com.tw Q W - R 1 2 3 - 0 1 7 . c  TYPICAL APPLICATION CIRCUIT UTC L8200 RcalA RcalM GND VINGM DM VOUT HB LB CSUB JF1 10nF C* C2 10nF * Stripline Elements 22kΩ 22kΩ 47nF To other FET stages Power supply for IF Amps RL1 RH1 RL2 QL CL1 RH2 9.75GHz Local Osc. 10.6GHz Local Osc. QH CH1 LNB power and tone signal Capacitors C1 and C2 ensure that residual power supply and substrate generator noise is not allowed to affect other external circuits which may be sensitive to RF inte rference. They also serve to suppress any potential RF feed through between stages via the UTC L8200. These capacitors are required for all stages used. Values of 10nF and 4.7nF respectively are recommended however this is design dependent and any value between 1nF and 100nF could be used. The capacitor CSUB is an integral part of the UTC L8200 ’s negative supply generator. The negative bias voltage is generated on-chip using an internal osci llator. The required value of capacitor CSUB is 47nF. This generator produces a low current supply of approximately -3V. Although this generator is intended purely to bias the external FETs, it can be used to power other external low current circuits via the CSUB pin. Resistor RCALA sets the drain current at which all external amplifier FETs are operated and RCALM sets the mixer bias current. If any bias control circuit is not required, its related drain and gate connections may be left open circuit without affecting the operation of the remaining bias circuits. The UTC L8200 have been designed to protect the external FETs form adverse operating conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit can not exceed the range -3.0V~1V under any conditions , including power up and power down transients. Should the negative bias generator be shorted or overloaded so that the drain current of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid damage to the FETs by excessive drain current. UTC L8200 incorporates over and under voltage protection so is the receiver or installation develops a fault the LNB will shut down and restart once operating conditions are back to normal.

L8200 Preliminary LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD 6 of 6 www.unisonic.com.tw Q W - R 1 2 3 - 0 1 7 . c  SINGLE UNIVERSAL BLOCK DIAGRAM The following block diagram below shows the main elements of a single universal LNB. A single chip solution provides all the FET and mixer bias, control signal detect for polarization and band selection and all the necessary power management functions required within a single universal LNB. UTC L8200 Vertical Horizontal Gain Stages GaAs/HEMT FET Active Mixer IF Gain Stage LB Osc HB Osc VOUT VIN Set-top Box Receiver Polarization and band switching on the UTC L8200 uses the standard 13~17V and 22kHz as defined by Astra. The exception is that the dev ices voltage detector has a much tighter tolerance than required to increase field reliability. The single V IN pin is used internally for three functions, LNB and IC power supply, voltage detection and tone detection. The IC’s is self powering via an internal re gulator which utilizes the 13~17 V control voltage from the satellite receiver. The regulated voltage is used to supply t he IC and is also outputted to the Vout pin to provide the power supply for the remaining element of the LNB such as the IF amplifiers. The 13~17V from the receiver is feed via a tight tolerance voltage detector with integrated filtering which remove s unwanted signals or interference. The results from the detectors output enables one of 2 bias circuits to turn one of either Fet1 or FET2 on. The internal tone detector allows the device to det ect the 22kHz tone which is superim posed on the LNB power line (13~17V signal), this is achieved with no external filtering co mponents. The tone detector rejects all unwanted signals including transients from other parts of the LNB system. The tone detector controls a drive circuits which powers and one of two oscillators, normally used to switch between lo w and high band in universal applications. The functional table below shows the operation of the FET and Mixer bias, oscillator output and the LNB power supply.  FUNCTION TABLE INPUTS OUTPUTS VIN (V) FIN (kHZ) FET1 FET2 FET3 MIXER LB(V) HB(V VOUT (V) <14.1 0 Disabled Active Active Active 5.0 0 5.0 >15.4 0 Active Disabled Active Active 5.0 5.0 <14.1 22 Disabled Active Active Active 0 5.0 5.0 >15.4 22 Active Disabled Active Active 0 5.0 5.0 UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.