L8115

UTCL8115 UTC | Alldatasheet

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UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 1 QW-R123-005,B FET BIAS CONTROLLER WITH POLARISATION SWITCH AND TONE DETECTION

DESCRIPTION

The UTC L8115 is designed to meet the bias requirements of GaAs and HEMT FETs commonly used in satellite receiver LNBs, PMR, cellular telephones etc. with a minimum of external components. With the addition of two capacitors and a resistor the devices provide drain voltage and current control for three external grounded source FETs, generating the regulated negative rail required for FET gate biasing whilst operating from a single supply. This negative bias, at -2.8 volts, can also be used to supply other external circuits. The UTC L8115 includes bias circuits to drive up to three external FETs. A control input to the device selects either one of two FETs as operational, the third FET is permanently active. This feature is normally used as an LNB polarization switch. Also specific to Universal LNB applications is the 22kHz tone detection and logic output feature which is used to enable high and low band frequency switching. Drain current setting of the UTC L8115 is user selectable over the range 0 to 15mA, this is achieved with addition of a single resistor. The UTC L8115 gives 2.2 volts drain whilst.

FEATURES

*Provides bias for GaAs and HEMT FETs. *Drives up to three FETs. *Dynamic FET protection. *Drain current set by external resistor. *Regulated negative rail generator requires only 2 external capacitors. *Choice in drain voltage *Wide supply voltage range *Polarisation switch for LNBs *22KHz tone detection for band switching. *Tone detector ignores unwanted signals *Support fr MIMIC, FET and Bipolar local oscillator devices

APPLICATIONS

*Satellite receiver LNBs *Private mobile radio(PMR) *Cellular telephones SSOP-16(150mil) SSOP-20(150mil)

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 2 QW-R123-005,B PIN CONFIGURATION SSOP-16(150mil) 1 16 GND D12 CNB1 CNB2 CSUB LB VCC LOV HB FIN VPOL RCAL SSOP-20(150mil) GND N/C C NB1 C NB2 C SUB LB V CC LOV H B FOUT CREC FIN VPOL R CAL ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS UNIT Supply Voltage Vcc -0.6 ~ 12 V Supply Current Icc 100 mA Input Voltage V IN 25 Continuous V Drain Current (per FET)(set by RCAL) I D 0 ~ 15 mA 500 mW Power Dissipation(Ta=25℃) SSOP-16(150mil) SSOP-20(150mil) PD 500 mW Operating Temperature Topr -40 ~ 80 ℃ Storage Temperature Tstg -50 ~ 85 ℃

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 3 QW-R123-005,B

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated, Ta=25℃, Vcc=5V, ID=10mA, RCAL=33kΩ) PARAMETER SYMBOL TEST CONDITONS MIN. TYP. MAX. UNIT Supply Voltage Vcc 5 10 V Supply Current Icc I D1= ID2 (or ID12)=ID3=0 ID1=0,ID2 (or ID12)= ID3=10mA, VPOL=14V ID2=0,ID1 (or ID12)= ID3=10mA, VPOL=15.5V ID1 and ID3=0, ILB=10mA ID1 and ID3=0, IHB=10mA 8.5 mA mA mA mA mA Substrate Voltage V SUB (Internally generated) I CSUB=0 I CSUB=-200μA -3.05 -2.8 -2.55 -2.4 V V Output Noise Drain Voltage Gate Voltage END ENG CG=4.7nF,CD=10nF CG=4.7nF,CD=10nF 0.02 0.005 Vpkpk Vpkpk Oscillator Frequency fo 180 330 800 kHz GATE CHARACTERISTICS PARAMETER SYMBOL TEST CONDITONS MIN. TYP. MAX. UNIT Output Current Range I GO -30 2000 A Output Voltage Gate 1 Off Low High V G1O VG1L VG1H ID1=0mA, VPOL=14V, IGO1=-10μA ID1=12mA, VPOL=15.5V, IGO1=-10μA ID1=8mA, VPOL=15.5V, IGO1=0μA -2.5 -2.5 0.4 -2.25 -2.25 0.75 -2.0 -2.0 1.0 V V V Output Voltage Gate 2 Off Low High V G2O VG2L VG2H ID2=0mA, VPOL=15.5V, IGO2=-10μA ID2=12mA, VPOL=14V, IGO2=-10μA ID2=8mA, VPOL=14V, IGO2=0μA -2.5 -2.5 0.4 -2.25 -2.25 0.75 -2.0 -2.0 1.0 V V V Output Voltage Gate 3 Low High V G3L VG3H ID3=12mA, IGO3=-10μA ID3=8mA, IGO3=0μA -3.0 0.4 -2.75 0.75 -2.0 1.0 V V DRAIN CHARACTERISTICS PARAMETER SYMBOL TEST CONDITONS MIN. TYP. MAX. UNIT Current I D 8 10 12 mA Current range I Drng Set by RCAL 0 15 mA Current Change With Vcc With Tj ΔIDV ΔIDT Vcc=5 ~ 10V Tj=-40 ~ +80℃ 0.5 0.05 %/V %/℃ Drain 1 Change: High V D1 I D1=10mA,VPOL=15.5V 2.0 2.2 2.4 V Drain 2 Change: High V D2 I D2=10mA,VPOL=14V 2.0 2.2 2.4 V Drain 3 Change: High V D3 I D3=10mA,VPOL=15.5V 2.0 2.2 2.4 V Voltage Change With Vcc With Tj ΔVDV ΔVDT Vcc=5 ~ 10V Tj=-40 ~ +80℃ 0.5 %/V ppm Leakage Current Drain 1 Drain 2 IL1 * IL2 * VD1=0.5V,VPOL=14V VD2=0.5V,VPOL=15.5V μA μA * FOR SSOP-20(150mil) package only.

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 4 QW-R123-005,B TONE DETECTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITONS MIN. TYP. MAX. UNIT Filter Amplifier Bias Voltage 5 VOUT IFIN=0 1.75 1.95 2.15 V Input Impedance Finz VFIN=100mV p/p 150 Ω Amplifier Gain AG V FIN=100mV p/p 30 V/mA V Threshold 5 FV T 100 170 350 mVp/p Output Stage Lov Volt.Range 6 VLov IL=50mA(LB or HB) -0.5 Vcc-1.8 V Lov Bias Current I LOV V LOV=0 0.02 0.15 1.0 μA VLOV=0, IL=0 RIb-Csub=1MΩ Enabled 6 -3.05 -2.80 -2.55 V LB Output Low VLBL VLOV=3V, IL=0mA RIb-Gnd=1MΩ Enabled 6 -0.01 0 0.1 V LB Output High VLBH VLOV=0, IL=10mA VLOV=3V ,IL=50mA Disabled 6 Disabled 6 -0.025 2.9 3.0 0.025 3.1 V VLOV=0 ,IL=0 Rhb-Csub=1MΩ Disabled 6 -3.05 -2.80 -2.55 V HB Output Low VHBL VLOV=3V, IL=0mA Rhb-Gnd=1MΩ Disabled 6 -0.01 0 0.1 V HB Output High VHBH VLOV=0, IL=10mA VLOV=3V, IL=50mA Enabled 6 Enabled 6 -0.025 2.9 3.0 0.025 3.1 V POLARITY SWITCH CHARACTERISTICS PARAMETER SYMBOL TEST CONDITONS MIN. TYP. MAX. UNIT Input Current I POL VPOL=25V (Applied via RPOL=2kΩ) 10 25 40 μA Threshold Voltage VTPOL VPOL=25V (Applied via RPOL=2kΩ) 14 14.75 15.5 V Switching Speed T SPOL VPOL=25V (Applied via RPOL=2kΩ) 100 ms NOTES: 1. The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors, CNB and CSUB, of 47nF are required for this purpose. 2. The characteristics are measured using an external reference resistor R CAL of value 33k wired from pins R CAL to ground. 3. Noise voltage is not measured in production. 4. Noise voltage measurement is made with FETs and gate and drain capacitors in place on all outputs.C G,4.7nF,are connected between gate output and ground,C D,10nF,are connected between drain outputs and ground. 5. These parameters are linearly related to Vcc. 6. These parameters are measured using Test Circuit 1

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 5 QW-R123-005,B TEST CIRCUIT 1 5V DC CNB 47nF CSUB 47nF 4.7nF Rcal Fin NC NC Lov Csub HB LB CF1 See Note 1 Note 1: V2 Characteristics Type: AC source Frequency: 22kHz Voltage: 350mVp/p Enabled 100mVp/p Disabled Note:Same circuit used for SSOP16(150mil) but with adjusted pinout. Gnd Cnb1 Cnb2 N/C Vpol Vcc UTC L8115 SSOP20(150mil) 33k TYPCIAL CHARACTERISTICS Drain Current (mA) Rcal (k) Vsub (V) External Vsub Load (mA) 0 20 40 60 10080 Vcc=5V 0.0 -1.0 -0.5 -1.5 -2.0 -2.5 -3.0 Vcc=5V 10V Note: Operation with loads>200μA is not guaranteed. JFET Drain Curretn vs Rcal Vsub vs External Load

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 6 QW-R123-005,B Drain Voltage (V) Drain Current (mA) LB/HB Offset voltage (mV) Load Current (mA) LB/HB Dropout Voltage vs Load Current LB/HB Dropout Voltage (V) Load Current (mA) 2.4 2 4 6 8 1210 2.3 2.2 2.1 14 16 Vcc=5V 10V 01 0 2 0 3 0 4 0 5 0 VCC=5V, VLOV=0V Ta=70 ℃ Ta=25 ℃ Ta=-40 ℃ 2.0 01 0 2 0 30 40 50 1.8 1.9 1.7 1.6 1.5 1.4 1.2 1.3 Vcc=5V Ta=70℃ Ta=25℃ Ta=-40℃ JFET Drain Voltage vs Drain Current LB/HB Offset Voltage vs Load Current FUNCTIONAL DIAGRAM Vcc VD set RCAL RCAL (Sets ID) GND CNB2 CNB CNB1 Negative supply Gen. CSUB CSUB DN GN QN 20μA ID Set ID Sense

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 7 QW-R123-005,B FUNCTIONAL DESCRIPTION The UTC L8115 provides all the bias requirements for external FETs, including the generation of the negative supply required for gate biasing, from the single s upply voltage.The diagram above shows a single stage from the UTC series. It contains 3 such stages. The negative rail generator is common to both devices. The drain voltage of the external FET Q N is set by the UTC L8115 to its normal operating voltage. This is determined by the on board VD Set reference, the UTC L8115 this is nominally 2.2 volts whilst. The drain current taken by the FET is monitored by the low value resistor I D Sense. The amplifier driving the gateof the FET adjusts the gate voltage of QN so that the drain current taken matches the current called for by an external resistor RCAL. Since the FET is a depletion mode transistor, it is often necessary to drive its gate negative with respect to groundto obtain the required drain current. To provide this capability powered from a single positive supply, the deviceincludes a low current negative supply generator. This generator uses an internal oscillator and two external capacitors, C NB and CSUB. The following schematic shows the function of the V POL input. Only one of the two external FETs numberd Q1 and Q2 are powered at any one time,their selection is controlled by the input V POL.This input is designed to be wired to the power input of the LNB via a high value(10k) resistor.With the input voltage of the LNB set at or below 14V,.FET Q2 will be enabled.With the input voltage at or above 15.5V,FET Q1 will be enabled.The disabled FET has its gate driven low and its drain terminal is switched open circuit. It is permissible to commect the drain pins D1 and D2 together if required by the application circuit;this is done internally in the SSOP-16(150mil) version.FET number Q3 is always active regardless of the voltage applied to V POL. Enable Drain Voltage & Current Controller 20μA VSUB Enable Drain Voltage & Current Controller 20μA VSUB Enable Drain Voltage & Current Controller 20μA VSUB 14.75V Reference VPOL Input For SSOP-20(150mil) Package

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 8 QW-R123-005,B Control Input Switch Function Input sense Polarisation Select ≤14 volts Vertical FET Q2 ≥15.5 volts Horizontal FET Q1 For many LNB applications, tone detection for band switching is required. The UTC L8115 includes all the circuitry necessary to detect the presence of a 22kHz tone modulated on the supply input to the LNB. The main elements of the detector are an op-amp, a rectifier/smoot her and a comparitor. The op-amp has a pre-set internal feedback resistor so that just a simple RC network wired to the input gives user defined gain and low frequency cut filter characteristics. The RC network components also serve two other purposes. The resistor provides overvoltage protection for the Vpol pin and the capacitor mi nimises tone interference of the Vpol threshold. The upper frequency roll-off of the op-amp has been set internally at above 100kHz to allow the amplifier to be used with other common tone switch frequencies. The rectifier/smoother/comparitor function is provided by a complex propriety circuit that allows the UTC L8115 to reliably detect wanted tones whilst ignoring low frequency square wave switch box signals, DiSEqC™ bursts and supply switching transients common when using DiSEqC-2™ ready set-top boxes. This is all achieved without the need for any further external components. The threshold of the comparitor is supply dependent, hence the gain of the preceding op-amp must be adjusted in line with supply voltage. See the table below for recommended values for 22kHz detection, given for a range of supplies. Lov Input LB Output HB Output Enable Enable OUTPUT DRIVERS LNB Input CF1 4.7n Ref Ref FILTER RECTIFIER VPOL Fin UTC L8115 COMPARATOR Table_1 Supply Voltage (Vcc) Filter Components 5V 6V 7V 8V 9V 10V Cf 4.7nF 4.7nF 4.7nF 10nF 10nF 10nF Note:Optimised for F(tone)=22kHz

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 9 QW-R123-005,B APPLICATIONS CIRCUIT The diagrams below show partial application circuits for the UTC series showing all external components required for appropriate biasing. The bias circuits are unconditionally stable over the full temperature range with the associated FETs and gate and drain capacitors in circuit. Capacitors C2 and C4 ensure that residual power supply and substrate generator noise is not allowed to affect other external circuits which may be sensitive to RF interference. They also serve to suppress any potential RF feedthrough between stages via the UTC device. These capacitors are required for all stages used. Values of 10nF and 4.7nF respectively are recommended however this is design dependent and any value between 1nF and 100nF could be used. The capacitors CNB and CSUB are an integral part of the UTCs negative supply generator. The negative bias voltage is generated on-chip using an internal oscillator. The required value of capacitors CNB and CSUB is 47nF. This generator produces a low current supply of approximately -3 volts. Although this generator is intended purely to bias the external FETs, it can be used to power other external circuits via the CSUB pin. Resistor RCAL sets the drain current at which all external FETs are operated. If any bias control circuit is not required, its related drain and gate connections may be left open circuit without affecting the operation of the remaining bias circuits. The UTC L8115 has been designed to protect the external FETs from adverse operating conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit can not exceed the range -3V to 1V under any conditions, including powerup and powerdown transients. All the bias stages include drain currents limits which work independently in each stage. Should the negative bias generator be shorted or overloaded so that the drain current of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid damage to the FETs by excessive drain current. * Stripline Elements * C1 * L2 * C3 C4 10nF *L1 10nF CNB 47nF CSUB 47nF 4.7nF LNB Downfeed Rcal Fin Lov Csub HB LB D12 C1G2 Gnd Cnb1 Cnb2 Vpol Vcc UTC L8115 SSOP16 (150mil) Vcc * L3 * C5C6 10nF SSOP16(150mil) Applications circuit 33k

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 10 QW-R123-005,B * Stripline Elements * C1 * L2 * C3 C4 10nF *L1 10nF CNB 47nF CSUB 47nF 33k 4.7nF LNB Downfeed Rcal Fin Lov Csub HB LB CF1G2 Gnd Cnb1 Vpol Vcc UTC L8115 SSOP20(150mil) Vcc Cnb2 N/C NC NC SSOP20(150mil) Applications circuit The following block diagram shows the main section of an LNB designed for use with the Astra series of satellites. The UTC L8115 is the core bias and control element of this circuit. The UTC provides the negative rail, FET bias control, polarisation switch control, tone detection and band switching with the minimum of external components. Compared to other discrete component solu tions the UTC circuit reduces component count and overall size required. Single Universal LNB Block Diagram UTC L8115 Regulator Vertical Antenna Gain Stage GaAs/HEMTFET Polarity Switch &Tone Detect Input Gain Stage GaAs/HEMTFET Mixer Gain Stage ASTRA Universal Band 10.70GHz-12.75 GHz Horizontal Antenna Gain Stage GaAs/HEMTFET Band Switch Output Local Osc 1

9.75 GHz - Low Band

10.6GHz - High Band IF down feed 950-2050 MHz - Low Band 1100 - 2150 MHz - High Band Tone detection and band switching is provided on the UTC L8115 devices. The following diagrams describes how this feature operates in an LNB and the external components required. The presence or absence of a 22kHz tone applied to pin FIN enables one of two outputs, LB and HB. A tone present enables HB and tone absent enables

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 11 QW-R123-005,B LB. The LB and HB outputs are designed to be compatible with both MMIC and discrete (bipolar or FET) local oscillator applications, selected by pin LOV. Referring to Figure 1 wiring pin LOV to ground will force LB and HB to switch between -2.6V (disabled) and 0V (enabled). Referring to Figures 2 and 3 wiring pin L OV to a positive voltage source (e.g. a potential divider across VCC and ground set to the required oscillator supply voltage, V OSC) will force the LB and HB outputs to provide the required oscillator supply, VOSC, when enabled and 0V when disabled. Tone Detection Function LOV F IN L B H B L B H B GND 22kHz Disabled Enabled -3 volts G ND - Enabled Disabled G ND -3 volts VOSC 22kHz Disabled Enabled Note 1 Vosc - Enabled Disabled Vosc Note 1 Note 1: 0 volts in typical LNB applications but ependent on extenal circuits. APPLICATIONS LOCAL OSCILLATOR CIRCUITS Vcc RCAL VPOL FIN NC NC Lov LB Csub HB GND CNB1 CNB2 N/C Vcc 33K CSUB 47nF CNB 47nF CLB 100n CHB 100nF Vcc 2.0k LNB Downfeed Figure 1 Local Osc. MMIC UTC L8115 CF1 4.7nF 300k 300k

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 12 QW-R123-005,B Vcc RCAL VPOL FIN NC NC Csub GND CNB1 CNB2 N/C Vcc 33K CSUB 47nF CNB 47nF

10 CHB

4.7nF 2.0K LNB Downfeed Figure 3 2 k CLB 100nQ1 10.6GHz Local Osc. Lov HB LB 9.75GHz Local Osc. Vcc RCAL VPOL FIN NC NC Csub GND CNB1 CNB2 N/C Vcc 33K CSUB 47nF CNB 47nF 4.7nF 2.0K LNB Downfeed Figure 2 CLB 100n 10.6GHz Local Osc. Lov HB LB 9.75GHz Local Osc. UTC L8115 UTC L8115

UTC L8115 LINEAR INTEGRATED CIRCUIT UTC UNISONIC TECHNOLOGIES CO., LTD. 13 QW-R123-005,B UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.