STL80N4LLF3 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuit
  • 4 Package mechanical data
  • 5 Revision history

N-channel 40V - 0.0042Ω - 80A - PowerFLAT™ (6x5) STripFET™ Power MOSFET for DC-DC conversion General features ■ Improved die-to-footprint ratio ■ Very low profile package (1mm Max) ■ Very low thermal resistance ■ Conduction losses reduced ■ Switching losses reduced

Description

This series of product utilizes the latest advanced design rules of ST’s proprietary STripFET™ Technology. The resulting Transistor is optimized for low on-Resistance and minimal gate charge. The chip-scaled PowerFLAT™ package allows a significant board space saving, still boosting the performance.

Applications

■ Switching application Internal schematic diagram Type V DSS RDS(on) ID STL80N4LLF3 40V <0.005 Ω 20A (1) 1. When mounted on FR-4 board of 1 inch² , 2oz Cu, t<10 sec PowerFLAT™( 6x5 ) Order codes Part number Marking Package Packaging STL80N4LLF3 L80N4LLF3 PowerFLAT™ (6x5) Tape & reel

1 Electrical ratings

Table 1. Absolute maximum ratings

  1. Guaranteed for test time < 15ms
  2. The value is rated according Rthj-c
  3. When mounted on FR-4 board of 1 inch² , 2oz Cu, t < 10 sec
  4. Pulse width limited by safe operating area

Table 2. Thermal resistance

  1. When mounted on FR-4 board of 1 inch² , 2oz Cu, t<10 sec

2 Electrical characteristics

Table 3. On/off states Table 4. Dynamic

Table 5. Switching times Table 6. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: Pulse duration = 300µs, duty cycle 1.5%

2.1 Electrical characterist ics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Normalized B VDSS vs temperature Figure 6. Static drain-source on resistance

3 Test circuit

Figure 12. Switching times test circuit for Figure 13. Gate charge test circuit Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test Figure 16. Unclamped inductive wavefo rm Figure 17. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

DIM. mm. inch A1 0.02 0.05 0.0007 0.0019 A3 0.20 0.007 D 5.00 0.196 D1 4.75 0.187 E 6.00 0.236 E1 5.75 0.226 e 1.27 0.050 PowerFLAT™ (6x5) MECHANICAL DATA

5 Revision history

Table 7. Revision history 13-May-2005 1 First release.