L7987L STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 41
Technical content
Datasheet sections
- 1 Application schematic and block diagram
- 2 Pin settings
- 2.1 Pin connection
- 2.2 Pin description
- 2.3 Maximum ratings
- 2.4 Thermal data
- 2.5 ESD protection
- 3 Electrical characteristics
- 4 Functional description
- 4.1 Oscillator and synchronization
- 4.2 Soft-start
- 4.3 Error amplifier and light-load management
- 4.4 Low VIN operation
- 4.5 Overcurrent protection
- 4.6 Overtemperature protection
- 5 Application information
- 5.1 Input capacitor selection
- 5.2 Output capacitor selection
- 5.3 Inductor selection
- 5.4 Compensation network
- 5.4.1 Type II compensation networ k
- 5.4.2 Type III compensation network
- 5.5 Thermal considerations
- 5.6 Layout considerations
- 6 Demonstration board
Features
2 A DC output current 4.5 V to 61 V operating input voltage RDS,ON = 300 mΩ typ. Adjustable fSW (250 kHz - 1.5 MHz) Low IQ-SHD (11 µA typ. from VIN) Low IQ (1 mA typ. - VIN 24 V - VOUT 3.3 V) Output voltage adjustable from 0.8 V to VIN Synchronization Adjustable soft-start time Adjustable current limitation Advanced bootstrap capacitor management for LDO operation VBIAS improves efficiency at light load PGOOD open collector output Output voltage sequencing Digital frequency foldback in short-circuit Peak current foldback in short-circuit Auto-recovery thermal shutdown
Applications
Designed for 24 V bus Fail safe tolerant systems Programmable logic controllers (PLCs)
Description
The L7987L device is a step-down monolithic switching regulator able to deliver up to 2 A DC. The output voltage adjustability ranges from 0.8 V to almost VIN. The embedded switchover feature on the VBIAS pin maximizes the efficiency at light load. The adjustable current limitation, designed to select the inductor RMS current accordingly with the nominal output current, and the high switching frequency capability make the size of the application compact. Pulse-by-pulse current sensing with digital frequency foldback implements an effective constant current protection over the different application conditions. The peak current foldback decreases the stress of the power components in heavy short-circuit condition. The PGOOD open collector output can also implement output voltage sequencing during the power-up phase. Multiple devices can be synchronized sharing the SYNCH pin to prevent beating noise in low noise applications like sensors with A/D conversion. HTSSOP16 (RTH = 40 °C/W)
1 Application schematic and block diagram
Figure 1. Application schematic Figure 2. Block diagram
2 Pin settings
2.1 Pin connection
Figure 3. Pin connection (top view)
2.2 Pin description
Table 1. Pin description
1 VBIAS
if supplied by the output voltage or by an auxiliary rail.
2 VIN DC input voltage
3 VIN DC input voltage
5 EN Active high enable pin. Connect to the VCC pin if not used.
7 SYNCH Master / slave synchronization
8 COMP Output of the error amplifier. The designed compensation network is connected at this pin. 9 FB Inverting input of the error amplifier. 10 FSW A pull-down resistor to G ND selects the switching frequency. 11 ILIM A pull-down resistor to GND selects the peak current limitation.
12 PGOOD The PGOOD open collector output is driven low when the output voltage, sensed on the FB
13 LX Switching node
14 LX Switching node
16 GND Signal GND
- E.P. Exposed pad must be connected to signal GND.
2.3 Maximum ratings
2.4 Thermal data
2.5 ESD protection
Table 2. Absolute maximum ratings Table 3. Thermal data Table 4. ESD protection
3 Electrical characteristics
Table 5. Electrical characteristics Switch internal supply from VCC to VBIAS. Switch internal supply from VCC to VBIAS.
Table 5. Electrical characteristics (continued)
- Specifications referred to T J from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by
design, characterization and statistical correlation.
- Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
- Not tested in production.
4 Functional description
external resistor. The input voltage feed-forward is implemented. The soft-start circuitry to limit inrush current during the start-up phase. The voltage mode error amplifier. management purposes, is also present. circuitry (UVLO) that checks the input and internal voltages. output voltage is above 87% of the target value.
4.1 Oscillator and synchronization
between the FSW pin and ground. Figure 4. Oscillator and synchronization
Figure 5. Switching frequency programmability sawtooth ramp, according to the input voltage change (Figure 6 a). to keep the PWM modulator gain constant versus the switching frequency. pin) only slightly lower than the external clock frequency.
L7987L Functional description This pre-adjusting of the slave IC switching frequency keeps the truncation of the ramp sawtooth negligible. In case two or more (up to five) L7987L SYNCH pins are tied together, the L7987L IC with higher programmed switching frequency is typically the master device; however, the SYNCH circuit is also able to synchronize with a slightly lower external frequency, so the frequency pre-adjustment with the same resistor on the FSW pin, as suggested above, is required for a proper operation.
Figure 6. Feed-forward
4.2 Soft-start
avoids inrush current surge and makes the output voltage increase monotonically. internal 0.8 V ± 1% reference to regulate the output voltage. Figure 7. Soft-start During the soft-start period the current limit is set to the nominal value. given TSSDISCH = 530 s and RSSDISCH = 380 typical values.
reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible.
4.3 Error amplifier an d light-load management
operational amplifier, therefore, with high DC gain and low output impedance. The uncompensated error amplifier characteristics are summarized in Table 6. has two poles due to the LC filter and one zero due to the ESR of the output capacitor. inductor charge current is slightly impacted by VIN and inductance level. recharge current can flow from VIN through CBOOT, LX and the LS MOS. Table 6. Error amplifier characteristics
L7987L Functional description
4.4 Low VIN operation
In normal operation (i.e.: VOUT programmed lower than input voltage) when the HS MOS is turned off, a minimum off time (TOFFMIN) interval is performed. In case the input voltage falls close or below the programmed output voltage (low dropout, LDO) the L7987L control loop is able to keep the boot capacitor properly charged by limiting the HS MOS on time to T ONMAX. When this limit is reached the HS MOS is turned-off and a pull-down resistor between LX and GND is turned on until one of the following conditions is met: A negative current limit (300 mA typ.) is reached A timeout (1 s typ.) is reached. So doing the L7987L device is able to work in low dropout operation, due to the advanced boot capacitor management.
4.5 Overcurrent protection
The L7987L device implements an overcurrent protection by sensing the current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing circuitry is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 120 ns. If the overcurrent limit is reached, the power MOSFET is turned off implementing pulse-by- pulse overcurrent protection. In the overcurrent condition, the device can skip turn-on pulses in order to keep the inductor current constant and equal to the current limit, assuming only a slight drift due to input and output voltage variation. If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the power MOSFET is turned off and one pulse is skipped. If, at the following switching on, when the “masking time” ends, the current is still higher than the overcurrent threshold, the device skips two pulses. This mechanism is repeated and the device can skip up to seven pulses (refer to Figure 8). If at the end of the “masking time” the current is lower than the overcurrent threshold, the number of skipped cycles is decreased by one unit. As a consequence, the overcurrent/short-circuit protection acts by switching off the power MOSFET and reducing the switching frequency down to one eighth of the default switching frequency, in order to keep constant the output current close to the current limit.
Figure 8. OCP and frequency scaling additional feature helps to reduce the IC stress in case of output short-circuit. threshold is restored. This foldback protection is disabled during the soft-start. output short-circuit the maximum switching frequency can be computed by Equation 4.
value shown in Table 2 on page 7. Figure 9. Current limit and programming resistor
4.6 Overtemperature protection
the integrated power MOSFET. (typ.) the device turns off the power MOSFET and shuts down.
Application information L7987L
5 Application information
5.1 Input capacitor selection
The input capacitor must be rated for the maximum input operating voltage and the maximum RMS input current. Since the step-down converters input current is a sequence of pulses from 0 A to IOUT, the input capacitor must absorb the equivalent RMS current which can be up to the load current divided by two (worst case, with duty cycle of 50%). For this reason, the quality of these capacitors must be very high to minimize the power dissipation generated by the internal ESR, thereby improving system reliability and efficiency. The RMS input current (flowing through the input capacitor) is roughly estimated by: Equation 7 Actual DC/DC conversion duty cycle, D = VOUT/VIN, is influenced by a few parameters: Equation 8 where VF is the freewheeling diode forward voltage and VSW the voltage drop across the internal high-side MOSFET. Considering the range DMIN to DMAX it is possible to determine the maximum ICIN,RMS flowing through the input capacitor. The input capacitor value must be dimensioned to safely handle the input RMS current and to limit the VIN and VCC ramp-up slew-rate to 0.5 V/s maximum, in order to avoid the device active ESD protections turn-on. Different capacitors can be considered: Electrolytic capacitors These are the most commonly used due to their low cost and wide range of operative voltage. The only drawback is that, considering ripple current rating requirements, they are physically larger than other capacitors. Ceramic capacitors If available for the required value and voltage rating, these capacitors usually have a higher RMS current rating for a given physical dimension (due to the very low ESR). The drawback is their high cost. Tantalum capacitors Small, good quality tantalum capacitors with very low ESR are becoming more available. However, they can occasionally burn if subjected to very high current, for example when they are connected to the power supply. DMAX VOUT VF+ DMIN VOUT VF+
The amount of the input voltage ripple can be roughly overestimated by Equation 9. Equation 9 In case of MLCC ceramic input capacitors, the equivalent series resistance (RES,IN) is negligible. In addition to the above considerations, a ceramic capacitor with an appropriate voltage rating and with a value 1 F or higher should always be placed across VIN and power ground and across VCC and the IC GND pins, as close as possible to the L7987L device. This solution is necessary for spike filtering purposes.
5.2 Output capacitor selection
The output capacitor is very important in order to satisfy the output voltage ripple requirement. Using a small inductor value is useful to reduce the size of the choke but increases the current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required. Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. If the zero goes to very high frequency, typical drawback in case of ceramic output capacitor application, a type III compensation network must be designed. The current in the output capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge and discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be estimated starting from the current ripple obtained by the inductor selection. Assuming I L the inductor current ripple, the output voltage ripple is roughly overestimated by Equation 10. Equation 10 Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR value. The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. The output capacitor is also the key component that provides the current to the load during a load transient which exceeds the system bandwidth. So, if the high slew rate load transient is required by the application, the output capacitor must be designed in order to sustain the load transient or absorbs the energy stored in the inductor until the converter reacts. In fact, even if the controller detects immediately the load variation and sets the duty cycle at 100% or 0%, the output current slope is limited by the inductor value, the input and output voltage. VIN PP VOUT PP IL RES OUT IL
Application information L7987L The output voltage has a drop or overshoot that depends on the ESR and capacitive charge/discharge, as roughly estimated in Equation 11: Equation 11 where VL is the voltage applied to the inductor during the load appliance or load release. Equation 12 MLCC capacitors have typically low ESR to minimize the ripple but also have low capacitance that does not minimize the voltage deviation during dynamic load variations. Electrolytic capacitors, on the other hand, have a large capacitance which minimizes voltage deviation during load transients whereas they do not show the same ESR values as the MLCCs, resulting then in higher ripple voltages. A mix between an electrolytic and MLCC capacitor can be used to minimize ripple as well as reducing voltage deviation in dynamic mode. The high bandwidth error amplifier of the L7987L and external compensation feature let design a wide range of output filter configurations (including all MLCC solutions) and perform fast transient response.
5.3 Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value, in order to have the expected current ripple, must be selected. The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current. In the continuous conduction mode (CCM), the required inductance value can be calculated by Equation 13: Equation 13 In order to guarantee a maximum current ripple in every condition, Equation 13 must be evaluated in case of maximum input voltage, assuming V OUT fixed. Increasing the value of the inductance help to reduce the current ripple but, at the same time, strongly impacts the converter response time to a dynamic load change. The response time is the time required by the inductor to change its current from the initial to the final value. Until the inductor has finished its charging (or discharging) time, the output current is supplied (or recovered) by the output capacitors. Further, if the compensation network is properly designed, during a load variation the device is able to properly change the duty cycle so improving the control loop transient response. When this condition is reached the response time is only limited by the time required to change the inductor current, basically by V IN, VOUT and L. Minimizing the response time, at the end, can help to decrease the output filter total cost and to reduce the application area. VOUT LT– IOUT RES OUT IOUT L IOUT VL DMAX VIN VOUT– VOUT L VOUT 1 VOUT VIN
5.4 Compensation network
E/A is considered as ideal, that is, its bandwidth is much larger than the system one. Figure 10. Switching regulator control loop simplified model gain changes and how to keep it constant in spite of the external synchronization).
Application information L7987L The transfer function of the power section (i.e.: the L-CO filters and the output load) is the ratio of the parallel of CO and RO and the sum of L and the parallel of CO and RO, including L and CO parasitics: Equation 15 given L, RDC, CO, RES and RO the parameters shown in Figure 10. The power section transfer function can be rewritten as follows: Equation 16 Equation 17 Equation 18 with the assumption that the inductor parasitic resistance, RDC, is negligible compared to RO. The closed loop gain is then given by: Equation 19 GLOOP(s) = GLC(s) • GPWO(s) • GCOMP(s) As noted in Section 5.2 on page 21, two different kinds of network can compensate the loop, depending on the value of fzESR, lower or higher than the regulator required bandwidth. In Section 5.4.1 and Section 5.4.2 the guidelines to select the type II and type III compensation network are illustrated. ODCOESODCESODCOOESOO ESOO DC O ESO O ESO LC RRRRCRRCRRCLsRRLCs RsCR RsLsCRR sCRR sG GLC s GLCO 1 s 1 s 2 GLCO RO fzESR fLC 2 LCO RO RES+ 2 LCO RO RES+ RO Q LCO RO RDC+ RO RES+ LCO RO RO RES+
5.4.1 Type II co mpensation network
allows to stabilize the loop. Figure 11. Type II compensation network
parasitic capacitance of the board, the RF required value is computed by Equation 22. The resultant control loop and other transfer functions gain are shown in Figure 12. Figure 12. Type II compensation - bode plot
5.4.2 Type III compensation network
based on MLCC ceramic capacitors, a type III compensation network must be designed. Figure 13. Type III compensation network
Application information L7987L The following suggestions can be followed for a quite common compensation strategy, assuming that CP << CF and RS << RU. Starting from Equation 19 on page 24, in case of type III compensation network and MLCC ceramic output capacitors the control loop gain module at s = 2 • FBW allows to fix the RF/RU ratio: Equation 26 After choosing the regulator bandwidth (typically FBW < 0.2 • FSW ) and a value for RU, usually between 1 k and 50 k, in order to achieve CF and CP not comparable with parasitic capacitance of the board, the RF required value is computed by Equation 26. Select CF in order to place FZ1 below FLC (typically 0.1 • FLC) Select CP in order to place FP1 at 0.5 • FSW Equation 27 Select CS in order to place FZ2 at FLC Select RS in order to place FP2 at 0.5 • FSW Equation 28 U F BW LC FF BWIIILOOP R R f f kfsG CF CP CS RS
The resultant control loop and other transfer functions gain are shown in Figure 14. Figure 14. Type III compensation - bode plot
5.5 Thermal considerations
and the current flowing into it during turn ON and turn OFF phases.
Application information L7987L TTR is the equivalent switching time. For this device the typical value for the equivalent switching time is 20 ns. Quiescent current losses, calculated as Equation 31 PQ = VIN • IQOPVIN + VBIAS • IQOPVBIAS where IQOPVIN and IQOPVBIAS are the L7987L quiescent current in case of separate bias supply. If the switchover feature is not used, the IC quiescent current is the only one from VIN, IQUIESC, as summarized in Table 5 on page 8. The junction temperature TJ can be calculated as: Equation 32 TJ = TA + Rth,JA • PTOT where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA, measured on the demonstration board described in Section 5.6, is about 40 °C/W for the HTSSOP16 package.
5.6 Layout considerations
The PCB layout of the switching DC/DC regulators is very important to minimize the noise injected in high impedance nodes and interference generated by the high switching current loops. Two separated ground areas must be considered: the signal ground and the power ground. In a step-down converter the input loop (including the input capacitor, the power MOSFET and the freewheeling diode) is the most critical one. This is due to the fact that high value pulsed currents are flowing through it. In order to minimize the EMI, this loop must be as short as possible. The input loop, including also the output capacitor, must be referred to the power ground. All the other components are referred to the signal ground. The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interference can be minimized by placing the routing of the feedback node as far as possible from the high current paths. To reduce the pick-up noise, the resistor divider must be placed very close to the device. To filter the high frequency noise, a small bypass capacitor (1 F or higher) must be added as close as possible to the input voltage pin of the device for both VIN and VCC pins. Thanks to the exposed pad of the device, the ground plane helps to reduce the junction to ambient thermal resistance; so a wide ground plane enhances the thermal performance of the converter, allowing high power conversion. The exposed pad must be connected to the signal GND pin. The connection to the ground plane must be achieved by taking care of the above mentioned input loop, in order to avoid high current flowing through the signal GND. Refer to Section 6 for the L7987L layout example.
6 Demonstration board
Figure 15. L7987L demonstration board schematic Table 7. L7987L demonstration board component list
Figure 16. L7987L demonstration board layout (top and bottom) Table 7. L7987L demonstration board component list (continued)
7 Application ideas
7.1 Positive buck-boost
the maximum expected load is 0.5 A. Figure 23. L7987L - positive buck-boost schematic example additional diode, D2, must be rated for the same maximum voltage. (C10, R15 and D5) and to speed up Q1 turn-off time (D4).
SW is the average current in the embedded power MOSFET during the ON time. page 29 must also be evaluated. Figure 24. Buck-boost PCB layout (top and bottom)
achieve a good phase margin.
7.2 Negative buck-boost
Figure 25. L7987L - negative (or inverting) buck-boost schematic example
Figure 26. Negative (or inverting) buck-boost PCB layout (top and bottom) other considerations summarized in Section 7.1 are also applied to the inverting buck-boost. Table 5: Electrical characteristics on page 8. to 49 V, if also the freewheeling diode has the same reverse voltage rating. considerations summarized in Section 7.1 are also applied to this topology.
Package information L7987L
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
8.1 HTSSOP16 package information
Figure 27. HTSSOP16 package outline Table 8. HTSSOP16 package mechanical data
9 Ordering information
Table 9. Order codes Table 10. Document revision history 15-May-2014 1 Initial release. page 1 (replaced “3 A” by “2 A”). wide input voltage ... systems”). Updated Figure 12 on page 26 (replaced by new figure). Updated Table 7 on page 31 (updated L1 component). Demonstration board on page 31. Added Section 7: Application ideas on page 34. Minor modifications throughout document.