L7292 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 60
Technical content
Datasheet sections
- 1 Package
- 2 Pin description
- 3 Typical application
- 4 Absolute maximum ratings
- 5 Electrical characteristi cs
- 5.1 Recommended operating conditions
- 5.2 Bias DC characteristics
- 5.3 Interface
- 5.3.1 I 2C electrical specification
- 5.3.2 MODA, MODB
- 5.4 EEPROM
- 5.5 Voltage monitor and POR generator
- 6 Voltage regulators
- 6.1 BUCK1 switching regulator
- 6.2 BUCK2 switching regulator
- 6.3 BUCK3 switching regulator
- 6.4 BUCK4 switching regulator
- 6.5 BUCK5 switching regulator
- 6.6 Thermal shutdown
- 7 General description
- 8.1 Description
- 8.2 Signal description
- 8.2.1 Serial clock (SCL)
- 8.2.2 Serial data (SDA)
Datasheet sections
- 10 EEPROM
- 11 Buck regulator descript ion
- 11.1 MOD selection - pin MODA, MODB
- 11.2 VOUT selection
- 11.3 Regulator sequence programmability
- 11.4 Soft-start
- 11.5 PWM mode
- 11.6 PFM mode
- 11.7 Forced PWM
- 11.8 Current limiting
- 11.9 Short-circuit protection
- 11.10 Deep sleep mode
- 11.11 Forced pull-down
- 11.12 Voltage monitor
- 11.13 Thermal protection
- 11.14 Fault summary
- 12 Package information
Features
Key specification – Vin range from 2.7 V to 5.5 V Interface – Two-wire I 2C serial interface supports 3.4-Mbit protocol (high speed mode) – 8-bit register bank – Random and Sequential Read modes – Automatic address incrementing Programmable buck regulators – Regulators with programmable DC set point and soft-start – Buck regulators include integrated PMOS and NMOS switching elements – Up to 90% efficiency – PWM and PFM modes – Two pins to select fo ur sets of DC voltages – ± 1% feedback voltage accuracy – All regulators with auto discharge function on reset. – Programmable bucks Support functions 128-bit EEPROM for: – Default Vout – Power up sequence – Reset IC delay time – Regulator enable Integrated voltage monitor with digital filters Thermal protection Package: VQFN 5 x 5 x 0.9 40L
Applications
SSD (Solid-State Drive), portable phone, etc.
Description
The L7292 is a power management device designed for consumer applications. Five bucks provide voltages for the µController and Flash memory with efficiency up to 90% in light-load condition. The device communicates with the µController via an I 2C serial interface operating at clock speeds up to 3.4 Mbit/s. The regulators operate at 1.3 MHz switching frequency and enter automatically in the PFM operation to maintain high efficiency over the entire load current range. The device can be forced into the PWM mode by writing a bit in the serial port register. Low quiescent current (e.g.: All SW reg. ON with no load Iq = 175 µA). The L7292 device has a DSM mode to reduce the quiescent current at the minimum value (1 x SW reg. ON with no load Iq = 60 µA). VQFN 5 x 5 x 0.9 40L Table 1. Device summary
1 Package
Figure 1. I2C ext. components
Figure 2. QFN 5 x 5 x 0.9 40L package (top view)
2 Pin description
Table 2. Pinout
Table 2. Pinout (continued)
3 Typical application
Figure 3. Typical application diagram
4 Absolute maximum ratings
long-term device reliability. Table 3. Absolute maximum ratings
5 Electrical characteristics
5.1 Recommended operating conditions
recommended conditions, unless otherwise indicated.
5.2 Bias DC characteristics
Table 4. Recommended operating conditions
- The “min.” value reported is referring to the typical value of undervoltage threshold distribution.
- Device mounted on the multilayer PCB with appropriate thermal optimization. If multiple ratings are listed
for the same parameter, all apply simultaneously. Table 5. Bias DC characteristics
5.3 Interface
5.3.1 I 2C electrical specification
Note: For others parameters refer to I 2C bus specifications.
5.3.2 MODA, MODB
5.4 EEPROM
Table 6. I2C electrical specification Table 7. MODA, MODB Table 8. EEPROM
5.5 Voltage monitor and POR generator
Table 9. Voltage monitor and POR generator
- Valid before POR signal enable.
6 Voltage regulators
6.1 BUCK1 switching regulator
Unless otherwise noted, typical values at TA = 25 °C, Vin = 5.0 V. The max. values are at Tj = 125 °C and the worst case process. Table 10. BUCK1 switching regulator
- Efficiency measured between the SUP14 PIN and BUCK1 POUT and while the BUCK4 is off. L = 1 H, DC resistance
6.2 BUCK2 switching regulator
Unless otherwise noted, typical values at TA = 25 °C, Vin = 5.0 V. The max. values are at Tj = 125 °C and the worst case process. Table 11. BUCK2 switching regulator
6.3 BUCK3 switching regulator
Unless otherwise noted, typical values at TA = 25 °C, Vin = 5.0 V. The max. values are at Tj = 125 °C and the worst case process. Table 12. BUCK3 switching regulator
6.4 BUCK4 switching regulator
Unless otherwise noted, typical values at TA = 25 °C, Vin = 5.0 V. The max. values are at Tj = 125 °C and the worst case process. Table 13. BUCK4 switching regulator Load transient time = 10 µs.
- Efficiency measured between the SUP14 PIN and BUCK4 POUT and while the BUCK1 is off. L= 1 µH, DC resistance max =
6.5 BUCK5 switching regulator
Unless otherwise noted, typical values at TA = 25 °C, Vin = 5.0 V. The max. values are at Tj = 125 °C and the worst case process. Table 14. BUCK5 switching regulator
6.6 Thermal shutdown
Table 15. Thermal shutdown
7 General description
The PMU is an integrated circuit designed to supply the µController and memory in applications supplied by a battery or 5 V. Each regulator is independent from the others and can be enabled or disabled by the I2C serial port. A 128-bit EEPROM is embedded in the device to store the default conditions used in each power up: The order in which the PSRs start during a power up sequence The programmable delay at the beginning and at the end of the power up sequence The programmable delay between each regulator start-up Excluding from the power up sequence any number of regulators The undervoltage mask and digital deglitch programmability for all regulators and for external and internal supplies Switching node slew rate programmability, disabling of synchronous rectification, PFM disabling for all switching regulators. All regulators employ synchronous rectification and have an automatic transition between PWM and PFM. A voltage monitor and thermal protection are present for a better control of system functionality.
Figure 4. Block diagram
8 I 2C interface
8.1 Description
a Stop condition after an ACK for Write and after a NoACK for Read.
8.2 Signal description
8.2.1 Serial clock (SCL)
a push-pull (rather than open drain) output.
8.2.2 Serial data (SDA)
output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from serial data (SDA) to VDD. Figure 5. I2C Start and Stop conditions
Figure 6. I2C protocol: bit order (MSB first), ACK bit, Start and Stop condition
8.3 I 2C device operation
controls the data transfer is known as the bus master, and the other as the slave device. clock for synchronization. The device is always a slave in all communications.
8.3.1 Start condition
Clock (SCL) for a Start condition, and will not respond unless one is given.
8.3.2 Stop condition
remains busy and another communication can start immediately.
8.3.3 Acknowledge bit (ACK)
acknowledge the receipt of the eight data bits.
8.3.4 Data input
when the Serial Clock (SCL) is driven low.
8.3.5 Register bank addressing
device type identifier which for the L7292 device is 0x7C. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. the device select code, it deselects itself from the bus.
8.3.6 Write operations
8.3.7 Byte Write
After the device selects the code and the address byte, the bus master sends one data byte.
8.3.8 Sequential Write
terminated by the bus master generating a Stop condition. Figure 7. Byte Write
Figure 8. Multi-write
8.3.9 Read operations
address counter is incremented by one, to point to the next register address.
8.3.10 Random Address Read
byte, and terminates the transfer with a Stop condition or a repeated Start condition.
8.3.11 Current Address Read
Start condition, without acknowledging the byte.
8.3.12 Sequential Read
with the internal address counter automatically incremented after each byte output. output data from the memory address 00h.
8.3.13 Acknowledge in Read mode
time, the device terminates the data transfer.
Figure 9. Current Address Read Figure 10. Random Address Read Figure 11. Sequential Current Address Read Figure 12. Sequential Random Address Read
4 CJU CJU 14
4 CJU CJU 4 CJU CJU 1=4
4 CJU CJU 4 CJU CJU CJU 1=4
8.4 High speed mode support
The device supports the I2C high speed mode to operate up to 3.4 Mbit/s. If the bus master wants to operate in the HS-mode a proper initial sequence in the fast-mode (max. 400 kbit/s) should be sent as described in the I 2C bus specification: 1. Start condition (S) 2. 8-bit master code (00001XXX) 3. Not acknowledge bit (A) After this sequence the bus switches into the high speed mode until first Stop condition.
9 Register map
9.1 General overview
Table 16. Register map overview
Table 17. Register map overview (continued)
- Every time the DSM bit is written or erased al l the other bits have to include the wanted status.
9.2 Detailed register description
Table 18. PSR1VL.VL voltage level
Table 19. PSR2VL.VL voltage level
Table 20. PSR3VL.VL - PSR4VL.VL - PSR5VL.VL - voltage level
9.2.4 PSRxLV.PSRxLVEN - voltage level selection enable 0: voltage level selection register disabled; voltage level is selected via MOD pins. 1: voltage level selection register enabled; output voltage changed according to the register selection. 9.2.5 PSRxLV.PSRxOCDIS - overcurrent disable 0: overcurrent for the regulator is enabled. 1: overcurrent for the regulator is disabled. 9.2.6 PSRxCFG.PFMDIS - PFM disable 0: PFM mode enabled. 1: PWM mode forced in the light-load mode. 9.2.7 YYYxCFG.ORDER - or der in power up sequence 0x0: first regulator to be turned on. 0x1: second regulator to be turned on. … 0x5 - 0x7: last regulator to be turned on. 9.2.8 PSRxCFG.RSLEW - driver slew rate 0x0: 500 V/s 0x1: 1000 V/s 0x2 1500 V/s 0x3: 2000 Vs 9.2.9 PSRxCFG.LSDIS - low side disable 0: low side enabled. 1: low side disabled. 9.2.10 YYYxCFG.UVM - mask undervoltage fault 0: undervoltage generates fault. 1: undervoltage does not generate fault. 9.2.11 SEQCFG.DLY2 - Delay 2 Delay between two sequence steps. 0x0: 0 ms / no delay 0x1: 0.5 ms 0x2: 1.0 ms 0x3: 2.0 ms
9.2.12 SEQCFG.DLY1CFG - Delay 1 configuration Delay before/after power up sequence configuration. 0x0: no delay. 0x1: delay before POR rising edge. 0x2: delay before starting sequence. 0x3: delay before starting sequence and before POR rising edge. 9.2.13 SEQCFG.DLY1 - Delay 1 Delay before de-assert POR (if enabled) and before starting sequence (if enabled). If SEQCFG Bit 7 = 0 0x0: 10 ms 0x1: 12 ms 0x2: 14 ms 0x3: 16 ms 0x4: 18 ms 0x5: 20 ms 0x6: 22 ms 0x7: 24 ms If SEQCFG Bit 7 = 1 Delay1 = 8 ms 9.2.14 PSCFG.EUVM - external undervoltage mask Mask external supply undervoltage fault. 0: undervoltage generates fault. 1: undervoltage does not generate fault. 9.2.15 PSCFG.IUVM - inte rnal undervoltage mask Mask internal supply undervoltage fault. 0: undervoltage generates fault. 1: undervoltage does not generate fault. 9.2.16 PSCFG.DEGL - deglitch Digital deglitch filter time duration for regulator output voltage monitor 0x0: 0 s 0x1: 1 s 0x2: 2 s 0x3: 5 s
9.2.17 REGCTRL.DSM - deep sleep mode 0: deep sleep mode disabled. 1: deep sleep mode enabled. 9.2.18 REGCTRL.LDO pull-down 0: pull-down but not in DSM. 1: always pull-down. 9.2.19 REGCTRL.YYYxDI S - PSRx/LDO disable 0: regulator is turned on. 1: regulator is turned off. 9.2.20 SETCTRL.BUSY - busy EEPROM busy, new operation not allowed. 0: new operation can be commanded. 1: no new operation can be commanded; all registers are locked, writing operation will not have effect. 9.2.21 SETCTRL.SDI - setting data integrity Setting data integrity status. 0: OK, data integrity check passed. 1: fault, data integrity check not passed. 9.2.22 SETCTRL.CMD - command Operation to be executed on setting data registers: address 0x00-0x0E. 0x0: no operation. 0x1: save as default. 0x2: restore default. 0x3: restore factory default. 9.2.23 STATUS.YYYxFL - fault Temperature, PSRx and LDO fault status. 0: no fault. 1: fault detected.
10 EEPROM
128 bits of the user accessible EEPROM are provided in the device. The EEPROM can be managed using the SETCTRL (“Setting Control”) register. The registers 0x00 through 0x0E (15 registers of 8 bits) are user-accessible and can be saved in the EEPROM to retain data at power-down. The EEPROM is managed as a whole block, meaning that all bits from registers 0x00 to 0x0E are loaded and saved at once in a single operation when accessing the EEPROM. The SETCTRL (setting control) register is used to operate on the EEPROM. To commence a write operation of the whole 0x00 - 0x0E block, the operations needed are as follows: Value 0x1 must be written via a serial interface to the SETCTRL.CMD bits (reg. 0x0F [1:0]). The SETCTRL.BUSY bit (reg. 0x0F [3]) will stay high for the duration of the EEPROM writing process, and can be optionally polled to assess the write status. The SETCTRL.CMD (reg. 0x0F [2]) can be optionally used to check if the operation was successful (bit low). To commence a read operation of the whole 0x00 - 0x0E block, the operations needed are as follows: Value 0x2 must be written via a serial interface to the SETCTRL.CMD bits (reg. 0x0F [1:0]). The SETCTRL.BUSY bit (reg. 0x0F [3]) will stay high for the duration of the EEPROM reading process, and can be optionally polled to assess the read status. The SETCTRL.CMD (reg. 0x0F [2]) can be optionally used to check if the operation was successful (bit low). To load the hard-coded default settings for registers 0x00 to 0x0E, value 0x3 must be written via a serial interface to the SETCTRL.CMD bits (reg. 0x0F[1:0]).
11 Buck regulator description
Figure 13. Block diagram light-loads to reduce the switching power losses and improve efficiency.
11.1 MOD selection - pin MODA, MODB
regulators changes according to Table 22. Table 21. Models selection Table 22. Regulators output voltage
Figure 14. Block diagram wanted power up sequence enabled.
11.2 VOUT selection
the MODA and MODB functionality.
status when in the DSM mode.
11.3 Regulator sequ ence programmability
0x3: delay before starting sequence and before POR rising edge. Table 23. VOUT ranges
Buck regulator description L7292 SEQCFG.DLY1 - Delay 1 - delay before de-assert POR (if enabled) and before starting sequence (if enabled) If SEQCFG Bit 7 = 0 0x0: 10 ms 0x1: 12 ms 0x2: 14 ms 0x3: 16 ms 0x4: 18 ms 0x5: 20 ms 0x6: 22 ms 0x7: 24 ms If SEQCFG Bit 7 = 1 Delay1 = 8 ms At the power up two conditions have to be asserted before to enable the ON phase of switching regulators. 1. LDO INT voltage = 1.8 V 2. SUP voltage ≥ 2.8 V When these conditions are asserted the default conditions stored in the EEPROM are performed. During this phase the comparators related to each BUCKx and Vsupply track the output voltage with the threshold defined by the regulator adjustment bits. After the BUCKx, Vsupplyx, and LDO INT are good, a programmable reset delay timeout begins. After the programmed delay, the POR pin is pulled high through the internal pull-up resistor to VBUS enabling the entire functionalities. The timing detail is as follows (based on the default soft-start order and delays programmed in the EEPROM): when the last start-up of regulators has ended (BUCK2 is the last one in soft-start sequence, by default), it starts the count of two Delay 2, and then the POR delay count (Delay 1) begins. This means that with the default settings (Dly 1 = 8 ms, Dly 2 = 0.5 ms), the POR is released and starts to be pulled up through the internal resistor 9 ms after the end of the start-up routine of the last regulator.
Figure 15. Operating mode
11.4 Soft-start
output voltage in a controlled manner. enabled (Figure 16); if again this isn't enough, the “current limit / 2" is applied.
Figure 16. Soft-start example
11.5 PWM mode
voltage and Vout in order to minimize the DC error on Vout. noise. In addition a slew rate programmability of the switching output is implemented.
L7292 Buck regulator description
11.6 PFM mode
To maintain high efficiency in light-load condition the device enters automatically the PFM mode for a load current of around IDCM/2 or lower. This happens when the inductor current becomes discontinuous. During the PFM operation, the converter fixes the output voltage to the nominal DC value plus ½ Vout ripple that is affected by the output capacitor, the current ripple in the inductor and the load current. In this phase the high-side PMOS current is limited at IDCM and the pulses frequency is proportional to the load current. When the PMOS current reaches IDCM the PMOS is switched OFF while the NMOS is forced ON. This is valid until a zero current is detected, then the regulator output is set in high impedance until Vout crosses the nominal value.
11.7 Forced PWM
When enabled, the buck regulator always operates in the PWM mode regardless of the output current. In the light-load the efficiency will be worse than in the PFM mode due to the inductor current becoming negative. This function enables the ability to have a constant frequency in light-load condition and also reduces the output voltage ripple.
11.8 Current limiting
According to the max. load current, an ILIMIT is embedded in each regulator to protect the device and any external components from overload conditions. When the high-side PMOS current reaches the ILIMIT, the regulator output is forced in high impedance for around 1 s, allowing the inductor current to decrease to a safe level before allowing another on-time to happen.
11.9 Short-circuit protection
In case the high-side PMOS current reaches the current limit and Vout falls below the short- circuit voltage threshold, the regulator is switched off permanently, until another full power- up of the whole device is performed.
11.10 Deep sleep mode
This feature is enabled when the device has to provide the minimum functionality of the system, to reduce the quiescent current and to be ready to restart the operative conditions when needed. The device can be placed in the “Deep Sleep Mode” (DSM) by writing bit 7 REGCTRL = 1 in this mode. Regulator 3 is enabled - no load current, in the PFM mode. Regulators 1 - 2 - 4 - 5 are OFF.
regulators ON with no load, while the in right column the DSM condition. phase with a different regulators setting. The DSM functionality is not enabled if POR is low.
11.11 Forced pull-down
pulled down through a discharge MOSFET switch, in order to discharge the output voltage.
11.12 Voltage monitor
circuit protection” is enabled.
11.13 Thermal protection
power up sequence following the default conditions. Table 24. Quiescent current
11.14 Fault summary
Figure 17. Operative mode Table 25. Protections for 1 s, then it continues regulating. Enabled with UVth = 85% of VOUT.
Table 26. Fault summary undervoltage PSR1 - 2 - 3 - 4 - 5 FL No Enabled at power up before POR rising. temperature falls below the lower threshold.
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 18. VQFN 5 x 5 x 0.9 40L package outline
Table 27. VQFN 5 x 5 x 0.9 40L package mechanical data
- VQFN-Sr stands for “Very Thin Quad Flat Non-leaded - Single Row”. Low profile: The total profile height
- The terminal A1 corner must be identified on the top surface through a inked or laser mark dot.
corner to identify the terminal A1. Exact shape of each corner is optional.
- Terminal A1 corner index area.
- The tolerance of the position that controls the locati on of the pattern of pads with respect to datum A and B.
must lie within this tolerance zone.
- The tolerance of the position that controls the location of the pads within the matrix with respect to each
of each pad must lie simultaneously in both tolerance zones.
13 PCB design rules guideline
13.1 Basic principles
time, the magnitude of the inductor current ramps up as it flows through the loop 1. system is used where a second switching element takes over the function of the diode. Figure 19. Current loops
13.2 Layout rules
devices, and inner layer 1 as a ground return plane. Figure 20. Layer stack
PCB design rules guideline L7292
13.2.1 Supplies
An incoming supply per switcher should be adequately buffered using an input capacitor. Refer to the device specification for suggested values. This capacitor needs to be placed as close as possible to the VIN pin to minimize the loop area.
13.2.2 Switch node
The switch node is the pin feeding the inductor. Keep the switch node as short as possible to avoid power losses. Do not make it wider than necessary to avoid capacitive loading of the switch node.
13.2.3 Feedback node
The feedback node is a high impedance input and thus sensitive to noise and current injection through the capacitive and magnetic coupling. Keep the feedback lines away from large switching surfaces or magnetic fields. Remember that magnetic fields are not stopped by copper! Feedback components should be connected to a clean return pathway and never share return paths with the main switching elements.
13.2.4 Output capacitors
Multiple output capacitors are preferred over a single one. Each capacitor should have its own return via.
13.3 PCB layout recommendation
Figure 21. All layers (top view) Figure 22. All layers (through view)
PCB design rules guideline L7292
13.4 General rules
Do not share vias. Every component connecting to the power or the reference plane needs its own via. For large currents multiple vias are to be preferred. Vias shall be placed as close as possible to the component pin. Feedback nodes are sensitive. Keep them away from magnetic fields and nodes that may capacitive couple energy into them.
13.5 Thermal aspects
The device package uses the center pad as a thermal conduit. This pad should be connected to an adequate spread of copper. When following the suggested layer stack the internal ground plane may be sufficient. If lots of other heat generating components are close by it may be necessary to create an exposed copper area on the backside of the board. The pad should be connected using multiple vias.
14 Evaluation tool
daughter board. The system allows the device full performance evaluation as well as debug. Figure 27. Serial port exerciser Figure 28. L7292 daughter board
15 Order codes
Table 28. Order codes Table 29. Document revision history 05-Nov-2015 1 Initial release.