L7203

L7203 STMICROELECTRONICS | Alldatasheet

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SMOOTH DRIVE  SYSTEM 1.8A DRIVE PEAK CAPABILITY SLEW RATE CONTROL INDUCTIVE SENSE START-UP ROUTINE THERMAL SHUTDOWN SUITABLE FOR 5V AND 12V APPLICATION ONLY ONE HALL SENSOR IS REQUIRED

DESCRIPTION

The L7203 SPINDLE MOTOR IC includes a three phase brushless spindle motor controller and the power stage in switching mode. The device is de- signed for both 5V and 12V OPTICAL DRIVE ap- plication requiring up to 1.8A peak of current. The device is realized in BCD5, a 0.7 µm Mixed technology. The spindle motor position detection is carried out by means of a single comparator with hyster- esis. In the start-up phase the "inductive sense start up method" is used to detect the rotor posi- tion, determining the direction of starting rotation. This procedure is implemented by a logic circuit on chip. The device applies three sinusoidal voltages to the motor coils. This is obtained through the application of the April 2001 LOW VOLTAGE DETECTO R PRS SRC AGND DGND BLOCK DIAGRAM ORDERING NUMBERS: L7203 (SO20) L7203S (SSO24) L7203 SMOOTH DRIVE SPINDLE MOTOR FOR OPTICAL DRIVE APPLICATION WITH POWER INTEGRATED SO20 SSO24

SMOOTH DRIVING concept. It is based on the idea of driving the motor wind- ing through 3 sinusoidal voltages dephased of 120 degrees. The motor is controlled in voltage mode, so no current control compensation net- work is required. Each profile is digitally described by 36 bytes stored in a ROM memory. These sinusoidal signals are modulated by multi- plying each sample by a value stored in the KVAL register. Using this kind of profiles it is possible to obtain great advantages such as torque ripple and acoustic noise reduction and lower EMI. An easier track following is ensured, since vibration are reduced. The clock signal on the chip can be synchronized to the external application clock signal. An internal circuit can limit the current. The threshold is fixed with a internal 0.2 V reference. The device generates: - a current generator to define output voltage slew rate - a 3.3 V reference to bias hall sensor. - the HFG open drain output signal for speed regulation. The device includes : - a circuit for thermal shutdown with hysteresis. - a low voltage detector In the STANDBY state the main functions of the device are turned off, in order to minimize the power consumption. The STANDBY state of the device is imposed by: - Thermal shutdown - stand by signal from µP PIN CONNECTIONS DESCRIPTION (continued) PRS N.C. N.C. VM U N.C. V W RF H BIAS ISR VCC DGND AGND SRC HFG FSYS STB1 N.C. PHS D01IN1174 RF1 PWMIN 11 14 1312H+ H- STB PRS VM U V RF W RF1 H+ PHS HBIAS ISR AGND VCC DGND SRC HFG FSYS1 H- PWMIN D98IN928A SO20 SSO24 L7203

VM Supply voltage for power stages +12/5V P12 VCC Supply for 5V core P5 DGND Logic ground G AGND Analog ground G DIGITAL PIN PWMIN PWM input signal to calculate kval IC5 Fsys System frequency IC5 PHS Phase Shift Pin IC5 PRS Prescaler Pin IC5 STB Start and Stop signal ZD5 HFG Open Drain F-Generator signal from Spindle Motor OD5 HALL SENSOR BIAS 3.3V reference to bias Hall sensor OA5 H+, H- Hall sensor differential input IA5 INDUCTIVE SENSE REFERENCE ISR Inductive sense reference IA5 MOTOR CONTROL OUTV Winding output U OA12 OUTV Winding output V OA12 OUTW Winding output W OA12 RF Current sense resistor (force) OA12 RF1 Current sense resistor (sense) IA5 SLEW RATE CONTROL SRC Slew Rate Control OA5 INPUT DEFINITION IC5 Input CMOS, 3.3-5V capability with hysteresis ZD5 Bidirectional, open drain, 3.3-5V capability OD5 Output, open drain, 3.3-5V capability IA5 Input, Analog, 5V OA5 Output, Analog, 5V OA12 Output, Analog, 12V P12 Power 12V / 5V P5 Power 5V G Ground L7203

DC ELECTRICAL CHARACTERISTICS ( VCC = 5V; VM = 12V; Tamb = 25°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VCC Supply 5V operating range 4.25 5.75 V VM Supply 12V operating range (note 1) 10.2 13.8 V VM Supply 5V operating range 4.25 5.75 V IVcc VCC Supply Current V CC = 5.75; fsys = 20MHz STB = 0 (bias pin open) STB =1 1.3 mA mA VVM VM Supply Current V M = 13.8 STB = 0 STB =1 mA mA PWMIN, PHS, PRS, Fsys ViL Input Low Voltage 1 V ViH Input High Voltage 2.2 V ViHYS Input Hysteresis 100 mV Iz Leakage Current V CC = 5.75 -10 +10 µA STB ViL Input Low Voltage 1 V ViH Input High Voltage 2.2 V VOL Open Drain Output IOL = 2mA V CC = 4.25V 0.4 V ViHYS Input Hysteresis 100 mV Iz Leakage Current V CC = 5.75, Therm off -10 +10 µA HFG VOL Open Drain Output IOL = 2mA V CC = 5V 0.4 V Iz Leakage Current V CC = 5.75, HFG hiz -10 +10 µA THERMAL DATA Symbol Parameter Value Unit R th j-pins Thermal Resistance Junction to Pins Max. 16 °C/W R th j-amb Thermal Resistance Junction to Ambient Max. 90 °C/W ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Tamb Ambient Temperature -20 to 80 °C Top Operating Temperature 0 to 150 °C Tsmin Minimum Thermal Circuit Threshold 140 °C VM -0.3 to 15 Vdc VCC -0.3 to 7 Vdc U, V, W, (low side drive =off) -0.3 to 17 Vdc PWMIN, PHS, FSYS, TEST, STB, HFG, BIAS, H+, H-, RF1, RF, ISR, PORPin -0.3 to VCC +0.3 Vdc PD1 Power dissipation at sustained operation with a package Rthj-amb at 90°C ESD Susceptibility 2000 Vac TSTG Storage Temperature -55 to 150 °C IOLHFG HFG open drain current 10 mA IPeak Motor Peak Current 1.8 A L7203

Controller drive STB pin by open drain. When Thermal Shutdown is excited, the device force this pin LOW. Controller will manage STB to do a re-start. When STB is LOW all the drivers are shut off. Hall Sensor Bias A regulator on chip supply a 3.3V+-10% refer- ence on pin Bias. This regulator can supply an output current up-to 15 mA. Symbol Parameter Test Condition Min. Typ. Max. Unit BIAS VBIAS BIAS Output Voltage V CC = 5V; 5mA < I < 15mA 3.25 3.75 V IBmax Max Output Current 15 mA H+, H- VH± H+ H- Input Voltage Range 0 2.5 V IH± Input Leakage Current V in = 0, +VCC -10 +10 µA VOFFISR Comparator Offset -15 +15 mV VHy Comparator Hysteresys 4 15 mV MOTOR POWER STAGE R DSON High and Low side FET on Resistance Tj = 125; VM = 4.25V I = 1.2A 2 Ω IU/V/W Spindle Output Leakage Current VM = 15V 100 µA CURRENT LIMITER VLim Internal Reference Voltage for current limitation 220 240 260 mV VOFFLim Comparator Offset -15 +15 mV THERMAL PROTECTION TS Shutdown temperature 130 170 °C UNDERVOLTAGE Vccth (fall) Undervoltage threshold (fall) 2.9 - - V Vccth (rise) Undervoltage threshold (rise) - - 3.4 V Vccth (hys) Undervoltage threshold (hys) - 0.1 - V SYSTEM FREQUENCY fsys System frequency PRS = 0 PRS = 1 MHz MHz SLEW RATE CONTROL VSRC SRC Output Voltage 1.25 V ISRC Output Current 500 µA R SRC External Resistor on pin SRC 10 K Ω ISR VISR Input Range 0 2 V Note 1: An SMBJIZAVCL-TR is recommended to clamp VM in case of high impedance on power supply line. DC ELECTRICAL CHARACTERISTICS (continued) R PULL UP OVER TEMP STB D98IN880 Figure 1. L7203

sequence: UW, VW, VU, WU, WV, UV. reference current ISR in each phase. tor divider between the pin BIAS and GND. so the rotor position is univocally determinated. For the Motor Connection please refer to the Fig. 4. pared with an internal 0.2V reference. logic) the signal to the power windings. the HOUT signal as in fig. 5. processor on the output open drain pin HFG. of the samples of the input signals.

255 CLOCK

Figure 4. Motor Connections.

the PWMIN signal and the internal signals, the PWMIN signal rate must be calculated by the ex- ternal microcontroller using the same frequency signal provided to the chip through the pin fsys. Digital Multiplier This unit contains a multiplier executing the multi- plication of each sample provided by the memory by the value stored in kval register. The output value is a 10-bit word, plus the sign bit. PWM Converter The PWM converter receives from the digital mul- tiplier three 10 bit digital number and converts it into three PWM signals. A counter counts up (from 0 to 255) and down (from 255 to 0) at the Fsys rate in continuos mode. Three 8-bit input registers are written with the 8 most significant bit of the word to be con- verted and compared to the counter value. The comparator output is: COMPARATOR

8 MSB

OUTPUT PWM: LSB WHERE: A HALF FSYS PERIOD A FSYS PERIOD Figure 11. COUNTER OUTPUT COMPARATOR 255 D98IN885A

510 Tsys

Figure 10. L7203

• 0, if the input value is smaller than the counter output - 1, if the input value is equal or greater than the counter output The comparator output is "adjusted" with a com- binational logic with the 2 low significant bit of the word to be converted in order to reach a 10 bit precision. The comparator output duty cycle is extended with a half fsys period for every low bit step how is showed in the figure 11. Phase Shift Block This block regulates the phase of the driving sig- nal to control the dephasing between the Zero- Cross signal and the voltage sinusoidal output signal. It is possible to demonstrate that the maximum efficiency for the motor driving may be reached ensuring a particular value PH of dephase be- tween the Zero-Cross signal and the voltage out- put signal. The Phase Shift BLock, starting from the PHS in- put signal synchronize the wave output with the Zero-Cross signal to ensure the optimum dephase. The PHS signal expresses the phase shift through the duration of its value according to the following rule: Table 1. PHS on NPhase Phase Shift (degree) time µs (Tsys = 50ns) decimal bit 0.2 0.4 0.6 0.8 1.0 1.2 1.4 00000 000 00000 001 00000 010 00000 011 00000 100 00000 101 00000 110 00000 111 LATCH 1.25 2.50 3.75 5.00 6.25 7.50 8.75 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 00001 000 00001 001 00001 010 00001 011 00001 100 00001 101 00001 110 00001 111 11.25 12.50 13.75 15.00 16.25 17.50 18.75 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 000010 000 000010 001 000010 010 000010 011 000010 100 000010 101 000010 110 000010 111 21.25 22.50 23.75 25.00 26.25 27.50 28.75 16.0 16.2 16.4 16.6 16.8 17.0 17.2 17.4 001010 000 001010 001 001010 010 001010 011 001010 100 001010 101 001010 110 001010 111 100 101.25 102.50 103.75 105.00 106.25 107.50 108.75 L7203

A eB D E L K H A1 C SO20MEC h x 45˚ SO20 DIM. mm inch A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 K 0˚ (min.)8˚ (max.) OUTLINE AND MECHANICAL DATA L7203

DIM. mm inch A 2.00 0.079 A1 0.05 0.002 B (2) 0.22 0.38 0.009 0.015 C 0.09 0.25 0.003 0.01 e 0.65 0.025 L1 1.25 0.05 k 0˚ (min), 4˚ (typ), 8˚ (max) ddd 0.1 0.004 (1) “D and E1” dimensions do not include mold flash or protu- sions, but do include mold mismatch and are mesaured at datum plane “H”. Mold flash or protusions shall not exceed 0.20mm in total (both side). (2) “B” dimension does not include dambar protusion/intrusion. SSO24 0053237 Be A2 A 11 2 1324 D L C E K SSO24ME SEATING PLANE C ddd C 0.25mm GAGE PLANE DATUM PLANE H Shrink Small Outline Package L7203

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com L7203