L6995 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 25
Technical content
■ CONSTANT ON TIME TOPOLOGY ALLOWS OPERATION WITH LOWER DUTY THAN PWM TOPOLOGY ■ VERY FAST LOAD TRANSIENTS ■ 5V Vcc SUPPLY ■ 1.5V TO 28V INPUT VOLTAGE RANGE ■ 0.9V ±1% VREF ■ MINIMUM OUTPUT VOLTAGE AS LOW AS 0.9V ■ SELECTABLE SINKING MODE ■ LOSSLESS CURRENT LIMIT ■ REMOTE SENSING ■ OVP,UVP LATCHED PROTECTIONS ■ 600µA TYP QUIESCENT CURRENT ■ POWER GOOD AND OVP SIGNALS ■ PULSE SKIPPING AT LIGHT LOADS
APPLICATIONS
■ I/O BUS FOR CPU CORE SUPPLY ■ NOTEBOOK COMPUTERS ■ NETWORKING DC-DC ■ DISTRIBUTED POWER
DESCRIPTION
The device is a step-down controller specifically de- signed to provide extremely high efficiency conver- sion, with losses current sensing tecnique. The "constant on-time" topology assures fast load transient response. The embedded "voltage feed-for- ward" provides nearly constant switching frequency operation. An integrator can be introduced in the control loop to reduce the static output voltage error. The available remote sensing improve the static and dynamic regulation recovering the wires voltage drop. Pulse skipping technique reduces power con- sumption at light load. Drivers current capability al- lows output current in excess of 20A. TSSOP20 ORDERING NUMBERS: L6995D L6995DTR STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL INPUT-OUTPUT CONVERSION This is preliminary information on a new product now in development. Details are subject to change without notice. MINIMUM COMPONENT COUNT APPLICATION SSC CBOOT OUTC SHDN 0.9V Vo L6995 28V Rin2 Rin1 CIN RILIM VDR INT VFB SS OSC BOOT HGATE PHASE LGATE PGND GND NOSKIP ILIM VSENSE VREF VREFC L BOOTD VCC HS LS DS
PIN CONNECTION (Top View) Symbol Parameter Value Unit VCC VCC to GND -0.3 to 6 V VDR VDR to GND -0.3 to 6 V HGATE and BOOT, to PHASE -0.3 to 6 V HGATE and BOOT, to PGND -0.3 to 36 V VPHASE PHASE -0.3-to 30 V LGATE to PGND -0.3 to V DR +0.3 V ILIM, VFB, VSENSE, NOSKIP , SHDN, PGOOD, OVP , VREF , INT , GND SENSE to GND -0.3 to VCC +0.3 V Ptot Power dissipation at Tamb = 25°C 1 W Tstg Storage temperature range -40 to 150 °C Symbol Parameter Value Unit R th j-amb Thermal Resistance Junction to Ambient 125 °C/W Tj Junction operating temperature range 0 to 125 °C PIN FUNCTION N° Name Description 1 NOSKIP Connect to V CC to force continuous conduction mode and sink mode.
2 GNDSE
3 INT Integrator output. Short this pin to VFB pin and connect it via a capacitor to VOUT to insert the integrator in the control loop. If the integrator is not used, short this pin to VREF .
4 VSENS
E This pin must be connected to the remote output voltage to detect overvoltage and undervoltage conditions and to provide integrator feedback input. 5V CC Supply voltage for IC core. Connect to 5V bus.
6 GND Signal ground
7 VREF 0.9 V voltage reference. Connect max. a 10nF ceramic capacitor between this pin and ground. This pin is capable to source or sink up to 250uA GNDSENSE INT OVP SHDN ILIM OSC VCC NOSKIP PGOOD LGATE PGND VDR PHASE HGATE BOOT1 10SS GND VREF VFB TSSOP20 INT VSENSE
8 VFB PWM comparator feedback input. Short this pin to INT pin when using the integrator function, or to VSENSE pin without integrator.
9 OSC Connect this pin to the input voltage through a voltage divider in order to provide the feed-
forward function. It cannot be left floating. 10 SS Soft start pin. A 5 µA constant current charges an external capacitor which value sets the soft- start time. 11 ILIM An external resistor connected between this pin and GND sets the current limit threshold. 12 SHDN Shutdown. When shorted to GND the device stops working; when high, it enables the normal operation. It cannot be left floating. 13 OVP Open drain output. When in OVP condition, the internal transistor goes off. Connect this pin to VCC through a resistor. 14 PGOOD Open drain output. The internal transistor is on during soft-start or in case of output voltage faults. Connect this pin to VCC through a resistor. 15 PGND Low Side driver ground. 16 LGATE Low Side driver output. 17 V DR Low Side driver supply. 18 PHASE Return path of the High Side driver. 19 HGATE High side MOSFETS driver output. 20 BOOT Bootstrap capacitor pin. High Side driver is supplied through this pin.
ELECTRICAL CHARACTERISTICS
(VCC = VDR = 5V; Tamb = 0°C to 85°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY SECTION Vin Input voltage range Vout=Vref Fsw=110Khz Iout=1A 1.5 28 V VCC , VDR 4.5 5.5 V VCC Turn-onvoltage 4.2 4.4 V Turn-off voltage 4.1 4.3 V Iqcc (VDR ) Driver quiescent current VFB > VREF 20 µA Iqcc (Vcc) Quiescent current VFB > VREF 600 µA SHUTDOWN SECTION SHDN Device On 1.2 V Device Off 0.6 V ISH (VDR ) Driver quiescent current in shutdown SHDN to GND 5 µA ISH (VCC ) Shut down current SHDN to GND 15 µA SOFT START SECTION ISS Soft Start current 4 6 µA SS Clamp Voltage 4 V ON TIME Ton On time duration VREF=VSENSE OSC=250mV 850 950 1050 ns PIN FUNCTION (continued) N° Name Description
VREF=VSENSE OSC=500mV 380 430 480 ns VREF=VSENSE OSC=1V 220 250 280 ns VREF=VSENSE OSC=2V 120 150 180 ns OFF TIME TOFFMIN Minimum off time 580 ns KOSC /TOFFMIN OSC=250mV 0.4 0.45 VOLTAGE REFERENCE VREF Voltage Accuracy 0 µA < IREF < 100µA 0.891 0.9 0.909 V PWM COMPARATOR Input voltage offset -2 +2 mV IFB Input Bias Current 0.1 µA CURRENT LIMIT AND ZERO CURRENT COMPARATOR ILIM input bias current I LIM to GND = 120KΩ 5 µA KC Current Limit factor R ILIM=120 KΩ 0.85 1 1.15 µA PHASE- GND Zero Crossing Comparator offset -2 2 mV GATE DRIVERS High side rise time V DR =5V; C=7nF HGATE - PHASE from 2 to 4.5V 50 70 ns High side fall time V DR =5V; C=7nF HGATE - PHASE from 2 to 4.5V 50 70 ns Low side rise time V DR =5V; C=14nF LGATE from 2 to 4.5V 50 70 ns Low side fall time V DR =5V; C=14nF LGATE from 2 to 4.5V 50 70 ns PGOOD UVP/OVP PROTECTIONS OVP Over voltage trip with respect to V REF 112 115 118 % UVP Under voltage trip 66 69 72 % PGOOD Upper threshold (VSENSE/VREF) VSENSE rising 107 110 113 % PGOOD Lower threshold (VSENSE/VREF) VSENSE falling 86 89 92 % VPGOOD ISOURCE =2mA 0.14 0.2 V INTEGRATOR INT Over Voltage Clamp V SENSE = VCC 1.04 1.07 1.1 V INT Under Voltage Clamp V SENSE = GND 0.82 0.84 0.86 V VSENSE - VREF Integrator Input Offset Voltage -5 5 mV IVSENSE Input Bias Current 0.1 µA ELECTRICAL CHARACTERISTICS (continued) (VCC = VDR = 5V; Tamb = 0°C to 85°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit
Figure 1. Functional & Block Diagram
1.15 VREF
0.89 VREF
1.10 VREF
0.69 VREF
1 DEVICE DESCRIPTION
1.1 Constant On Time PWM topology
Figure 2. Loop block schematic diagram
quency after a load transient as well as to mask PWM comparator output against noise and spikes. value). The voltage on the OSC pin must range between 50mV and 2V to ensure the system linearity.
1.2 Closing the loop
logic than a flip-flop to manage the transition in correct way. For more details refers to the Figure 1. error. Further the system regulates the output voltage valley value not the average, as in the Figure 3 is shown. Figure 3. Valley regulation to-peak amplitude is less than 150mV in steady state.
Where Δ VOUT is the output ripple and Δ VINT is the ripple wanted at the INT pin (100mV typ). Figure 4. Integrator loop block diagram steady-state operation. Some of these are internal as dead times, which depend on high side MOSFET driver. drops on supply and ground rails, low side and high side RDSON and inductor parasitic resistance. current decreases), the device stops to switch (high side MOSFET remains off).
1.3 Transition from PWM to PFM/PSK
1.4 Softstart
always present (see figure 5). Figure 5. Soft -Start Diagram has to be lower than the uvp time.
be supposed linear function of the time.
1.5 Current limit
inhibits the one-shot start. IN VOUT and switching frequency. Figure 6. Current limit schematic
1.6 Protection and fault
Sensing VSENSE pin voltage performs output protection. The nature of the fault (that is, latched OV or latched UV) is given by the PGOOD and OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ) of the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched: low side MOSFET is turned on, high side MOSFET is turned off and PGOOD goes low. In case the system detects an overvoltage the OVP pin goes high. To recover the functionality the device must be shut down and restarted thought the SHDN pin, or the supply has to be removed, and restart with the correct sequence. These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET short (OV fault).
1.7 Drivers
The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching tran- sition. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side MOSFET to be on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET is turned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the volt- age on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage reaches 500mV. This is important since the driver can work properly with a large range of external power MOS- FETS. The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the MOSFET gate charge and the switching frequency. So the power dissipation of the device is function of the ex- ternal power MOSFET gate charge and switching frequency. Eq 14 The maximum gate charge values for the low side and high side are given from: Eq 15 Eq 16 Where f SW0 = 500Khz. The equations above are valid for TJ = 150°C. If the system temperature is lower the QG can be higher. For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation; in this case the maximum value is QMAXLS = 125nC. The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect.
2 APPLICATION INFORMATION
2.1 20A Demo board description The demoboard shows the device operation in general purpose applications. The evaluation board allows using only one supply because the on board linear regulator LM317LD; the linear regulator supplies the device through the J1. Output current in excess of 20A can be reached dependently on the MOSFET type. The SW1 is used to start the device (when the supplies are already present) and to select the PFM/PWM mode. P driver V cc Q gTOT FSW⋅⋅= Q MAXHS fSW0 fSW Q MAXLS fSW0 fSW
Figure 7. Demoboard Schematic Diagram
2.2 Jumper Connection
Table 1. Jumper connection with integrator
- This component is not necessary, depends from the output ESR capacitor. See the integrator section.
Table 2. Jumper connection without integrator
2.3 NOTE
section is powered by the linear regulator); if the regulator is used close the J1, other wise it has to keep open. Be careful measuring the efficiency with the linear regulator asserted. around 1Mhz, but anyway higher than switching frequency (five times).
2.4 DEMOBOARD LAYOUT
Figure 8. PCB layout: bottom side Figure 9. PCB Layout: Top side Figure 10. Internal ground plane Figure 11. Power & signal plane
Table 3. PCB Layout guidelines Table 4. Component list with the adjacent circuitry. Side and Low side MOSFETS, Shottky diode as close as possible). 2) Controller placed as close as possible to the power MOSFET. Don’t penalty the efficiency. Keep power traces and load connections short and wide. close as possible to the Low Side MOSFETS. etc) as close as possible to the IC. 2) The feedback traces must be parallel and as close as possible. 3) Make the controller ground connection like the figure 19.
Notes: 1. N.M.=Not Mounted 2. The demoboard with this component list is set to give: VOUT = 1.25V, FSW = 270kHz with an input voltage around VIN = 20V with the integrator feature, and with 20A continuos output current. 3. All capacitors are intended ceramic type otherwise specified. Part name Value Dimension Notes C21 47pF 0603 C22 220nF 0805 C23 0603 N.M. C24 1nF 0603 C25 1uF Tantalum DIODES D1 BAT54 25V OUTPUT CAPACITORS C10-C11-C12 3X330uF EEFUE0D331R P ANASONIC Output capacitor C8, C9 N.M. INPUT CAPACITORS C13, C14, C16, C17, C15 C18 10uF C34Y5U1E106Z TOKIN Input capacitor 10uF C3225Y5V1E106Z TDK Part name Value Dimension Notes 10uF ECJ4XF1E106Z P ANASONIC 10uF TMK325F106ZH TAIYO YUDEN INDUCTOR L1 0.6µH ETQP6F0R6BFA P ANASONIC 0.6µH A959ASR60N TOKO 0.6µH DXM1306-R60-T COEV 0.6µH CEP12D38H0R6 SUMIDA POWER MOS Q1,Q2 STS11NF3LL STMicroelectronics Q3 N.M. STSJ25NF3LL STMicroelectronics Q3 N.M. Q5,Q6 STS25NH3LL STMicroelectronics Q4 N.M. DIODES D2 STPS3L40U STMicroelectronics 25V INTEGRATED CIRCUIT U1 LM317LD Linear regulator U2 L6995 Switcher
3 STEP BY STEP DESIGN
VIN = 20V VOUT = 1.25V IOUT = 20A FSW = 270kHz In this design it is considered a low profile demoboard, so a great attention is given to the components height. 3.1 Input capacitor. A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC com- ponent of this current is quite high and dissipates a considerable amount of power on the ESR capacitor: Eq 17 The IRMS current is given by: Eq 18 Neglecting the last term, the equation reduces to: Eq 19 which maximum value corresponds to δ = 1/2. ICINRMS , has a maximum equal to δ = 1/2 (@ VIN = 2×VOUT, that is, 50% duty cycle). The input capacitor, therefore, should be selected with an RMS rated current higher than ICINRMS . Electrolytic capacitors are the most used because are the cheapest ones and are available with a wide range of RMS current ratings. The only drawback is that, considering a requested ripple current rating, they are physically larger than other capacitors. Very good tantalum capacitors are coming available, with very low ESR and small size. The only problem is that they occasionally can burn out if subjected to very high current during the charge. So, it is better avoid this type of capacitors for the input filter of the device. In fact, they can be subjected to high surge current when connected to the power supply. If available for the requested value and voltage rating, the ceramic capacitors have usually a higher RMS current rating for a given physical size (due to the very low ESR). From the equation 18 it is found: Icin rms = 4.8A Considering 10µF capacitors ceramic, that have ICINRMS =1.5A, 6 pzs. are needed.
3.2 Inductor
In order to determine the inductor value is necessary considering the maximum output current to decide the in- ductor current saturation. Once the inductor current saturation it is found automatically is found the inductor val- ue. In our design it is considered a very low profile inductor. L = 0.6µH The saturation current for this choke is around 25A
3.3 Output capacitor
The output capacitor is chosen by the output voltage static and dynamic accuracy. The static accuracy is related to the output voltage ripple value, while the dynamic accuracy is related to the output current load step. If the static precision is around ± 2% for the 1.25V output, the output accuracy is ±25mV. To determine the ESR value from the output precision is necessary before calculate the ripple current: P CIN ESR CIN Iout2 Vin Vin Vout–()⋅ Icinrms Iout2δ 1 δ–() δ Icinrms Iout δ 1 δ–()=
Considering a switching frequency around 270kHz from the equation above the ripple current is around 7A. So the maximum ESR should be: Eq 21 The dynamic specifications are sometimes more relaxed than the static requirements so the ESR value around 7m Ω should be enough. The current ripple flows through the output capacitor, so the output capacitors should be calculated also to sus- tain this ripple: the RMS current value is given from Eq22. Eq 22 But this is usually a negligible constrain when choosing output capacitor. To allow the device control loop to work properly output capacitor zero should be at the least ten times smaller than switching frequency. The output capacitor value (COUT ) and the output capacitor ESR (ESROUT ) should be large enough and small enough, to keep the output voltage ripple within the specification and to give to the de- vice a minimum signal to noise ratio.
3.4 Power MOSFETS and Schottky Diodes
Since a 5V bus powers the gate drivers of the device, the use of logic-level MOSFETS is highly recommended, especially for high current applications. The breakdown voltage VBR DSS must be greater than VINMAX with a certain margin, so the selection will address 20V or 30V devices. The RDS ON can be selected once the allowable power dissipation has been established. By selecting identical Power MOSFET for the main switch and the synchronous rectifier, the total power they dissipate does not de- pend on the duty cycle. Thus, if P ON is this power loss (few percent of the rated output power), the required RDS ON (@ 25 °C) can be derived from: Eq 23 α is the temperature coefficient of RDSON (typically, α = 510-3 °C-1 for these low-voltage classes) and Δ T the admitted temperature rise. It is worth noticing, however, that generally the lower RDSON , the higher is the gate charge QG , which leads to a higher gate drive consumption. In fact, each switching cycle, a charge QG moves from the input source to ground, resulting in an equivalent drive current: Eq 24 The SCHOTTY diode placed in parallel to the synchronous rectifier must have a reverse voltage VRRM greater than VINMAX . For application with low Duty Cycle, where the input voltage is high (around 20V) it is very impor- tant to select the high side MOSFET with low gate charge, to reduce the switching losses as STS11NF3LL. For the low side section should be selected a low RDS ON as STS25NH3LL.
3.5 Output voltage setting
To select the output divider network there isn't a specific criteria, but a low divider network value (around 100Ω ) reduces the efficiency at low current; instead a high value divider network (500KΩ ) increase the noise effects. A network divider values from 1K to 50K is right. From the Eq4: IΔ Vin Vo– ESR V rippleΔ IΔ 2----- Icoutrms RDS ON P ON Iout2 1 α TΔ⋅+()⋅ Iq Qg F SW⋅=
R10 = 1KΩ R9 = 390Ω The device output voltage is adjustable by connecting a voltage divider from output to VSENSE pin. Minimum output voltage is VOUT = VREF = 0.9V. Once output divider and frequency divider have been designed as to ob- tain the required output voltage and switching frequency, the following equation gives the smallest input voltage, which allows L6995 to regulate (which corresponds to T OFF = TOFF, MIN): Eq 25 where the KOSC /TOFFMIN ratio worst-case is given in electrical characteristic table (pag. 4).
3.6 Voltage Feed Forward
Choosing the switching frequency around 270KHz from the Eq1. It can be selected the input divider. For exam- ple: R3=560K Ω R4=28K Ω In order to compensate the comparator delay R4 resistor should be increased around 20%. R4=33K Ω
3.7 Current limit resistor
From the Eq13 can be set the valley current limit, knowing the low side RDSON . To set the exact current limit it must be considered the temperature effect. So two STS25NH3LL have 2.75mΩ @ 25°C, at 100°C can be con- sidered 3.85mΩ . R8 = 47KΩ
3.8 Integrator capacitor
Let it be FU = 15kHz. Since VREF = 0.9V, from Eq4, it follows αOUT = 0.72 and, from Eq5 it follows CINT1 = 330pF. Because the ripple is lower than 150mV the system doesn't need the second integrator capacitor.
3.9 Soft start capacitor
Considering the soft start equations can be found: C SS = 200pF These equations are valid whitout load. When an active load is present the equantions result more complex; further some active loads have unexpected effect, as higher current than the expected one during the start up, that can change the start up time. In this case the capacitor value can be selected on the application; anyway the Eq11 gives an idea about the C SS value. δ 1 αOSC αOUT K OSC TOFFMIN
3.9.1 Efficiency
Figure 12. Efficiency vs output current Figure 13. Schematic Diagram
3.11 DEMOBOARD LAYOUT
Figure 14. Top side components placement Figure 15. Bottom side Jumpers distribution Figure 16. Top side layout Figure 17. Bottom side layout Table 5. Component list
- The demoboard with this component list is set to give: VOUT = 1.8V, FSW = 250kHz with an input voltage around VIN = 20V and
with the integrator feature.
- The diode efficiency impact is very low; it is not a necessary component.
- All capacitors are intended ceramic type otherwise specified.
Figure 18. Efficiency vs output current
4 TYPICAL OPERATING CHARACTERISTICS
The measurements refer to the part list in table 4. Vin = 20V Vout = 1.25V Fsw = 270kHz Tamb = 25°C. Figure 19. Soft Start with no load. Figure 20. Soft Start with 20A load. Figure 21. Normal functionality in PSK mode. Figure 22. Normal functionality in PWM mode.
DIM. mm inch A 1.20 0.047 A1 0.050 0.150 0.002 0.006 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 e 0.650 0.026 L1 1.000 0.039 k 0˚ (min.) 8˚ (max.) aaa 0.100 0.004 Note: 1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. TSSOP20 0087225 (Jedec MO-153-AC) Thin Shrink Small Outline Package
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com L6995