L6986I

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L6986I_V01 STMICROELECTRONICS | Alldatasheet

Document overview

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PDF pages: 60

Technical content

Datasheet sections

1 Application schematic
2 Pin connection
2.1 Maximum ratings
3 Electrical characteristics
4 Functional description
4.1 Primary side
4.1.1 Power supply and voltage reference
4.1.2 Switchover feature
4.1.3 Voltage monitor
4.1.4 Error amplifier
4.2 Transformer
4.3 Secondary side
4.4 Iso-buck operation principle
4.5 Soft-start and inhibit
4.6 Minimum On-Time
4.7 Output voltage line regulation
4.8 Output voltage load regulation
4.9 Overcurrent protection
4.10 Overvoltage protection
4.11 Thermal shutdown
5 Closing the loop
5.1 GCO(s)control to output transfer function
5.2 Error amplifier compensation network
5.3 Voltage divider
5.4 Total loop gain
5.5 Compensation network design
6 Application notes
6.1 Output voltage adjustment
6.2 Switching frequency

Features

Designed for iso-buck topology
4 V to 38 V operating input voltage
Primary output voltage regulation / no optocoupler required
1.9 A typical sink peak primary current capability
Peak current mode architecture in forced PWM operation
300 ns blanking time
8 µA I Q-SHTDWN
Adjustable f SW and synchronization
Embedded primary output voltage supervisor
Adjustable soft-start time
Internal primary current limiting
Overvoltage protection
R DS(on) HS = 180 mΩ, RDS(on) LS = 150 mΩ
Thermal shutdown

Applications

Isolated power supply for SiC MOSFET and IGBT drivers
Isolated power supply for isolated interfaces (RS232, I2C, SPI, etc.)
EV chargers
Motor drivers
Automation
UPS
Solar converters
Welding

Description

The L6986I is a device specifically designed for the isolated buck topology. Due to the P-Channel MOSFET as high-side power switch the device features 100% duty cycle operation. The primary output voltage can be accurately adjusted, whereas the isolated secondary output is derived by using a given transformer ratio. No optocoupler is required. The primary sink capability up to 1.9 A (even during soft- start) allows a proper energy transfer to the secondary side as well as enables a tracked soft-start of the secondary output. The control loop is based on a peak current mode architecture and the device operates in forced PWM. The 300 ns blanking time filters oscillations, generated by the transformer leakage inductance, making the solution more robust. Pulse by pulse current sensing on both power elements implements an effective constant current protection in the primary side. Due to the primary reverse current limit, the secondary output is protected against short circuit events. A primary output voltage supervisor, which notifies primary output voltage regulation through the RST open collector output, overvoltage protection, adjustable switching frequency, synchronization and a programmable soft-start are also available. Maturity status link L6986I

38 V, 5 W synchronous iso-buck converter for isolated applications

DS13647 - Rev 2 - September 2021 For further information contact your local STMicroelectronics sales office.

1 Application schematic

Figure 1. Application schematic

2 Pin connection

Figure 2. Pin connection (top view) Table 1. Pin description

1 RST

primary output voltage is over the active delay threshold. pin supplies the embedded analog circuitry.

3 SS / INH

to implement the soft-start.

5 FSW

minimize the IC consumption.

6 MLF Connect this pin to ground either directly or through a pull-down resistor if the

RST threshold should be adjusted (see Table 7).

8 DELAY

threshold. If this pin is left floating, RST is like a Power Good.

9 FB Primary output voltage sensing

10 SGND Signal GND

11 PGND Power GND

12 PGND Power GND

13 LX Switching node

14 LX Switching node

15 VIN DC input voltage

16 VBIAS Typically connected to the regulated primary output voltage, if it does not

exceed 6 V. Otherwise connect it to GND.

2.1 Maximum ratings

Stressing the device above the rating listed in the table below may cause permanent damage to the device. Table 2. Absolute maximum ratings Table 3. Thermal data Table 4. ESD protection

3 Electrical characteristics

Table 5. Electrical characteristics (TJ = 25 °C, VIN = 12 V unless otherwise specified).

Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max Unit VSS START Start of internal error amplifier ramp 0.995 1.1 1.150 V SSGAIN SS/INH to internal error amplifier gain 3 Error amplifier VFB Voltage feedback 0.841 0.85 0.859 V IFB FB biasing current 50 500 µA AV Error amplifier gain (1) 100 dB ICOMP EA output current capability ± 6 ±12 ±25 µA Inner current loop gCS Current sense transconductance (VCOMP to inductor current gain) (1) Ipk = 1 A 2.5 A/V VPP*gCS Slope compensation (2) 0.45 0.75 1.1 A Overvoltage protection VOVP Overvoltage trip (VOVP/VREF) 1.15 1.2 1.25 VOVP HYST Overvoltage hysteresis 0.5 2 5 % Synchronization (fanout: 6 slave devices typ.) fSYNCH Synchronization frequency FSW = VCC 275 1000 kHz FSW = GND 475 2200 VSYN TH SYNCH input threshold SYNCH rising 0.70 1.2 V ISYN SYNCH pull-down current VSYN = 1.2 V 0.7 mA VSYN OUT High level output 5 mA sinking load 1.40 V Low level output 0.7 mA sourcing load 0.6 Reset VTHR Selected RST threshold MLF pinstrapping before SS 2 % VTHR HYST RST hysteresis (1) 0.4 V VRST RST open collector output VIN > VIN HAND VFB < VTH4 mA sinking load 0.8 2 < VIN < VINH 4 mA sinking load 2 % Delay VTHD RST open collector released as soon as VDELAY > VTHD VFB > VTHR 1.19 1.234 1.258 V ID CH CDELAY charging current VFB > VTHR 1 2 3 µA Thermal shutdown TSHDWN Thermal shutdown temperature (1) 165 THYS Thermal shutdown hysteresis (1) 30 1. Not tested in production. 2. Measured at f SW = 250 kHz. L6986I

Table 6. fSW selection (TJ = 25 °C, VIN = 12 V unless otherwise specified).

Synchronization as slave between 275 kHz and 1000 kHz.
Not tested in production.
Synchronization as slave between 475 kHz and 1000 kHz

Figure 3. Circuit RVCC, RGND Table 7. RST threshold selection (TJ = 25 °C, VIN = 12 V unless otherwise specified).

please use the pre-defined resistor values.
do not exceed the indicated resistor value.

4 Functional description

Primary side, the regulation loop of the peak current mode architecture regulates the primary voltage (blue area in the picture below)
A two-windings transformer (in grey)
The secondary side, which generates the isolated output voltage (in green) given the selected transformer ratio

Figure 4. Iso-buck general schematic

4.1 Primary side

the primary side, defining so the duty-cycle and regulating the primary output voltage. synchronous MOSFET, hence transferring energy to the secondary coil during the off-time.

Figure 5. Internal block diagram

Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the device features low- dropout operation
A fully integrated sawtooth oscillator with adjustable frequency
A transconductance error amplifier
An internal feedback divider G DIV INT
The high-side current sense amplifier to sense the inductor current
A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements
The soft-start blocks to ramp the error amplifier reference voltage and so decreases the inrush current at power-up. The SS/INH pin inhibits the device when driven low
The switchover capability of the internal regulator to supply a portion of the quiescent current when the V BIAS pin is connected to an external output voltage
The synchronization circuitry to manage master / slave operation and the synchronization to an external clock
The current limitation circuit to implement the constant current protection, sensing pulse by pulse high-side / low-side switch current. In case of heavy short-circuit the current protection is fold back to decrease the stress of the external components
A circuit to implement the thermal protection function
The OVP circuitry to discharge the output capacitor in case of overvoltage event
MLF normally connected to GND through a resistor to set the threshold of the RST comparator
FSW pin strapping sets the switching frequency
The RST open collector output

4.1.1 Power supply and voltage reference

high and the device is enabled (SS/INH pin over the inhibits threshold). very low supply voltage noise sensitivity.

4.1.2 Switchover feature

output voltage). This helps to decrease the equivalent quiescent current seen at VIN.

4.1.3 Voltage monitor

regulator starts operating. There is also a hysteresis on the VCC (UVLO).

4.1.4 Error amplifier

inverting input (FB) is connected to the external divider or directly to the output voltage. Table 8. Uncompensated error amplifier characteristics The error amplifier output is compared with the inductor current sense information to perform PWM control. Figure 6. Internal circuit

4.2 Transformer

energy transfer to the secondary side, hence generating the secondary isolated output voltage.

4.3 Secondary side

and the rectifying element (Schottky diode).

4.4 Iso-buck operation principle

The picture below describes the operation principle of the iso-buck converter. winding. The load connected to the secondary output is supplied by Cout2. When the low side MOSFET is turned on, the voltage applied at the transformer windings inverts its polarity. winding to Cout and the load. Under this condition the energy transfer from primary to secondary side occurs. Figure 7. Iso-buck basic operating principle

Figure 8. Iso-buck primary and secondary current waveforms

4.5 Soft-start and inhibit

threshold. The current increases to 4 µA typ. as soon as the SS/INH voltage is higher than the VINH threshold. set the inhibit operation clamping the SS/INH voltage below VINH threshold. (SSGAIN) than the external ramp present at SS/INH pin.

Figure 9. Soft-start phase where TSS is the soft-start time, ISS CH the charging current and VFB the reference of the error amplifier.

Thermal shutdown event
UVLO event
The device is driven in INH mode The soft-start capacitor is discharged with a 0.6 mA typ. current capability for 1 ms time max. For complete and proper capacitor discharge in case of fault conditions, a maximum CSS = 67 nF value is suggested. In case the soft-start should be externally driven by a voltage step, the circuitry in figure below can be used. L6986I Soft-start and inhibit DS13647 - Rev 2 page 13/60

Figure 10. Enable the device with external voltage step More details about the component selection can be found in Section 6.5 Design of the external components. with the primary output voltage, as shown in figure below. Figure 11. Tracked soft-start at secondary side

4.6 Minimum On-Time

on-time (masking time, from which the parameter TON MIN derives). Figure 13. Simulation with appropriate masking time (330 ns)).

4.7 Output voltage line regulation

Figure 15. Schematic used for line and load regulation tests range up to 24 V for L6986I with VOUT prim = 5.3 V. Figure 16. Primary line regulation affected by the transformer and in particular by its leakage inductance. slightly increase the isolated output voltage, as shown in figure below.

4.8 Output voltage load regulation

over the entire output current range for the L6986I with VOUT = 5.3 V. Figure 19. Load regulation of the not isolated output parameters leads to a better load regulation. Figure 20. Effect of the transformer leakage inductance on the isolated output load regulation dependency of the isolated output voltage on the input voltage.

Figure 21. Input voltage effect on the load regulation of the isolated voltage

4.9 Overcurrent protection

secondary side of the iso-buck converter. current (see Table 5) in overcurrent condition. called “peak” the low-side sensing “valley”. from the analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event. be ineffective at extremely low duty cycles, the valley current protection at extremely high duty cycles. current limits assures the effectiveness of the overcurrent protection even in extreme duty cycle conditions. circuit event (switching frequency set to 500 kHz, actual switching frequency 250 kHz).

more negative), in accordance with equations (5) and (6)). ratio, D the duty cycle and ΔIL the current ripple in the primary winding. the reverse current limit (typ. 1.9 A), as shown in Figure 24. the equation (25)], hence allowing a higher current from the secondary output. Figure 24. Peak currents depending on the secondary output current (VIN = 12 V, VOUT_pri = 5.3, N = 6, fSW

Overcurrent or short circuit event at the secondary output, as described in the previous section.

4.10 Overvoltage protection

capacitor if the output voltage is 20% over the nominal value. overvoltage threshold even during the worst-case scenario in term of load transitions. not in line with the load request.

current during the overvoltage operation. pin (pin 9). For the selection of the capacitance value, equation (28) can be used. Figure 25. Overvoltage operation

4.11 Thermal shutdown

OFF continuously. When the thermal protection runs away a new soft-start cycle will take place.

5 Closing the loop

primary winding) as well as all the equations and calculations in the next sections. Figure 26. Block diagram of the loop

5.1 GCO(s)control to output transfer function

introduces a double pole at one half of the switching frequency.

Se can be calculated from the parameter VPP × gCS given in Table 5.

5.2 Error amplifier compensation network

Figure 27. Transconductance embedded error amplifier is useful to reduce the noise at the output of the error amplifier.

5.3 Voltage divider

Figure 28. Leading network example

5.4 Total loop gain

5.5 Compensation network design

VIN = 12 V, VOUT_pri = 5.3 V, ROUT_pri = 5.6 Ω (corresponding to almost 1 A load). respectively in Figure 29 and Figure 30. Figure 29. Bode plote (magnitude) Figure 30. Bode plot (phase)

The blue solid trace represents the transfer function including the sampling effect term (see equation (11)), the dotted blue trace neglects the contribution. Considering this example, bandwidth and phase margin are: BW ≈ 50 kHz Phase Margin → between 53° and 70° L6986I Compensation network design DS13647 - Rev 2 page 27/60

6 Application notes

6.1 Output voltage adjustment

where R1 and R2 are the resistors used in the output divider (see figure below). Figure 31. L6986I application circuit The integration of a P-channel MOSFET as high side switch theoretically allows duty cycle up to 100%. energy transfer to the secondary side takes place. side respectively and VFD1 is the forward voltage of the Schottky diode. of the current drawn from the primary output on the isolated voltage, as described by the eq. (9).

Figure 32. Isolated voltage variation due to the primary output current output exceeds the maximum deliverable charge limited by the peak current, the isolated output voltage drops. Figure 33. Secondary output maximum current

6.2 Switching frequency

Setting fSW = 250 kHz or fSW = 500 kHz does not require any external resistor. indicated in the electrical characteristics table), as described by the following equation. The switching frequency affects the selection of the primary inductance as well as the transformer construction.

6.3 Voltage supervisor

voltage and keeps the RST open collector output in low impedance as long as the VOUT is out of regulation (i.e. supply, the device can delay the RST assertion with a programmable time. Figure 34. Voltage supervisor operation released as soon as VDELAY = 1.234 V (see Figure 35). The CDELAY is dimensioned as follows. The maximum suggested capacitor value is 270 nF. soon as VDELAY = 1.234 V (see figure below). Figure 35. Voltage supervisor operation during OVP

6.4 Synchronization

when multiple switching regulators populate the same application board.

6.4.1 Embedded master - slave synchronization

synchronization signal to the others since the SYNCH pin is I/O able to deliver or recognize a frequency signal. frequency (see Table 6), so the same resistor connected at the FSW pin. common 180° phase shift with respect to the master. refer to the dedicate section. Figure 36. Input RMS current The figure below shows two not synchronized regulators with unconnected SYNCH pin.

Figure 37. Two regulators not synchronized Figure 38. Two regulators not synchronized

6.4.2 External synchronization signal

regulator set is phased to the reference and all the devices will work with 0° phase shift. recommended to synchronize with a frequency not higher than 1 MHz. signal. The slope compensation contribution is latched at power-up and so fixed during the device operation.

as shown in Figure 39 and Figure 40. Figure 39. L6986I synchronization driving capability selected line in Table 6 for at least 10 internal clock cycles. Table 9. Example of oscillator frequency selection Symbol RVCC (E24 series RGND (E24 series) fSW min. fSW typ. fSW max. point close to the selected oscillator frequency (FSW resistor). master may limit the driving frequency range within ± 5% of the selected frequency. (see IPK parameter in section 3) since the internal slope compensation signal may be saturated. successfully driving one pulse 250 kHz typ. (see Figure 40) in the SYNCH line.

6.5 Design of the external components

6.5.1 Input capacitor selection

capacitor are, together with its value, the maximum operating voltage and the RMS current capability. The input capacitor voltage rating must be higher than the maximum input operating voltage of the application. In the ideal case of efficiency η = 1, the RMS current reaches its maximum value when D = 0.5. Where ΔVHS and ΔVLS are the voltage drop across the high side and low side MOSFETs respectively. Figure 42. Input capacitor AC current

C IN ≥ C INmin = I OUT_pri +I OUT_sec ∙ N sec N pri 4 ∙ V PP ∙ f SW ∙ (35) Typically, CIN is dimensioned to keep the maximum peak to peak voltage across the input filter in the order of 5% of VINmax. L6986I Design of the external components DS13647 - Rev 2 page 36/60

6.5.2 Transformer selection

The transformer has two essential tasks:

Providing the isolation between primary and secondary side in accordance with the application requirements
Generating the necessary secondary output voltage from the regulated primary voltage with the most suitable turn ratio The transformer selection implies defining the following parameters:
Isolation voltage
Turn ratio
Primary inductance
Peak and RMS currents
Windings resistance
Leakage inductance
Parasitic capacitances Isolation voltage The isolation of the transformer in terms of voltage capability (1.5 kV, 4 kV, and so on) and type (functional basic, reinforced, etc.) is mainly driven by the application. Both parameters normally affect the size of the transformer as well as other electrical characteristics (e.g. winding resistance, leakage inductance, etc.). Turn Ratio Naming Npri and Nsec the number of turns of the primary and secondary windings respectively, the turn ratio is so defined: N = N pri N sec (36) Considering the equation (25), the turn ratio must be defined so that the voltage at the secondary output is the desired one over the whole secondary output current range: N ≥ V OUT_sec + R wind_sec ∙ I OUT_sec + V FD1 V OUT_pri + I OUT pri ∙ R DS on LS +R wind_pri (37) If no current is drawn from the primary output, the turn ratio should be only chosen to compensate the drops due to the secondary winding resistance and the Schottky diode. The effect of the leakage inductance on the secondary output voltage regulation (not included in the equation above) should be taken into account too. Figure 17 clearly shows how the secondary output voltage can drift due to the leakage inductance. Primary inductance The choice of the primary inductance does not differ so much from a standard buck. The magnetizing current, (see Figure 43) which combines the two winding currents, has the same shape of the buck inductor current and can be defined as: I L_mag = I pri +N ∙ I sec (38) L6986I Design of the external components DS13647 - Rev 2 page 37/60

Figure 43. Primary (blue) winding current, secondary (pink) winding current and magnetizing current the inductor value should be 19.4 µH (→ 18 µH or 22 µH the closest standardized value). RMS currents that the transformer should fulfill. The equation (44) emphasizes what mentioned about the recommended duty cycle. below). Furthermore, this affects the negative peak current at the primary side (see Figure 44).

Figure 48. Transformer parasitic capacitances

6.5.3 Schottky diode

Maximum forward current, mainly defined by the secondary output current demand (see equation (43));
Forward voltage drop, which affects the secondary output voltage regulation
Maximum peak reverse voltage. During the on phase of the primary side, when in the secondary side no current flows, the diode is reverse biased and must withstand this voltage: V D1_rev = N ∙ V INmax − V OUT_pri +V OUT_sec (44)
Junction capacitance, which should be as low as possible in order to reduce the ringing described in the previous section

6.5.4 Output capacitors selection

Determining the output voltage ripple
Supporting load transient
The loop stability, by setting one pole and one zero in the transfer function Considering the ouput voltage ripple requirement, the primary output capacitance should be selected according to the following equation: C OUT_pri = ΔI pri 8 ∙ f SW ∙ Δ V OUT_pri − ESR ∙ Δ I pri (45) Normally MLCC capacitor are the best choice for the output capacitor, therefore the ESR contribution is negligible and the equation (46) can be simplified. Secondary output capacitor The secondary output capacitor supplies the secondary output load current during the tON (when diode D1 is reverse biased) and its value defines the secondary output voltage ripple (ΔVOUT). C OUT_sec = I OUT_sec ∙ D ΔV OUT_sec ∙ f SW (46) L6986I Design of the external components DS13647 - Rev 2 page 41/60

7 Application example

Figure 49. Typical schematic with load applied to both the isolated and not isolated outputs

620 W82 p F

stable maximum deliverable current in an iso-buck topology must take into account the equations (5) and (6). outputs, with different input voltages. Figure 50. Maximum deliverable currents to the isolated and not isolated outputs

8 Application board

The reference evaluation board schematic is shown in the figure below. Figure 51. STEVAL-A6986IV1 evaluation board schematic

8 R12

Figure 52. STEVAL-L6986IV1 evaluation board schematic Figure 53. STEVAL-A6986IV2 evaluation board schematicC2 filter is not necessary or should be by-passed for any test, a 0 Ω resistor can be placed at R16. summarized in the following table.

Table 10. Type of the evaluation boards Table 11. BOM of the evaluation boards

Reference Part number Description Manufacturer R17 0 Ω R18 N.C. L3 XAL4030-472MEC 4.7 µH Coilcraft L4 MPZ2012S221A Ferrite bead TDK D1 STPS1150AY Schottky diode, 150 V, 1 A STM #1, #2 BZT52B4V3-HE3-08 Zener Diode 4.3 V Vishay Semiconductor #3 - N/A Q1 2STR1215 NPN power transistor STM #1 ZA9668-AE Transformer, N = 5.8, 3.3 kV isolation Coilcraft #2 2106.0007 Transformer, N = 5.6, 1.5 kV isolation Magnetica #3 ZB1175-AE Transformer, N = 1.53, 3.3 kV isolation Coilcraft U3 TL431AIL3T Adjustable voltage reference STM

8.1 Fine tuning of the evaluation boards

The evaluation boards can be customized to better match the user demands. 1. If a different dual isolated voltage is necessary (e.g. 15 V / - 6 V), the replacement of two components is enough to adapt the board: the Zener diode D3 (with a diode providing the most suitable Zener voltage) and the resistor divider (one of the two resistors) R12 - R13, in accordance with the equation: V I SO + = 2.49 V ⋅ R 12 + R 13 R 13 (47) Obviously, the total voltage VISO+ + |VISO-| must be compatible with the available voltage at the secondarywinding of the transformer. 2. STEVAL-A6986IV1 and STEVAL-L6986IV1 can be also turned into a single isolated voltage board by soldering a 0 Ω resistor in place of the capacitor C12. Any of the above-mentioned fine tunings could require an adjustment of the resistor R11. L6986I Fine tuning of the evaluation boards DS13647 - Rev 2 page 45/60

8.2 Load regulation of the evaluation boards

Figure 60. STEVAL-A6986IV1, VIN = 12 V, fSW = 500 kHz (VISO+) Figure 61. STEVAL-A6986IV1, VIN = 12 V, fSW = 500 kHz (VISO-) Figure 62. STEVAL-L6986IV1, VIN = 12 V, fSW = 500 kHz (VISO+)

9 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

9.1 HTSSOP16 package information

Figure 65. HTSSOP16 package outline

Package information

DS13647 - Rev 2 page 51/60

Table 12. HTSSOP16 mechanical data

Table 13. Ordering information

Ordering information

DS13647 - Rev 2 page 53/60

Revision history

Table 14. Document revision history 26-Mar-2021 1 First release. Updated Figure 13. Simulation with appropriate masking time (330 ns). Added R17 description in Table 11. BOM of the evaluation boards.

L6986I specifications and overview.

Summary

38 V, 5 W synchronous iso-buck converter for isolated applications 26-Mar-2021

Description

The L6986I is a device specifically designed for the isolated buck topology. Due to

Source title L6986I Datasheet(PDF) - STMicroelectronics

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Read L6986I online.

L6986I_V01 STMICROELECTRONICS | Alldatasheet

Document overview

Technical content

Datasheet sections

Features

Applications

Description

38 V, 5 W synchronous iso-buck converter for isolated applications

1 Application schematic

2 Pin connection

1 RST

3 SS / INH

5 FSW

6 MLF Connect this pin to ground either directly or through a pull-down resistor if the

8 DELAY

9 FB Primary output voltage sensing

10 SGND Signal GND

11 PGND Power GND

12 PGND Power GND

13 LX Switching node

14 LX Switching node

15 VIN DC input voltage

16 VBIAS Typically connected to the regulated primary output voltage, if it does not

2.1 Maximum ratings

3 Electrical characteristics

Electrical characteristics

4 Functional description

4.1 Primary side

4.1.1 Power supply and voltage reference

4.1.2 Switchover feature

4.1.3 Voltage monitor

4.1.4 Error amplifier

4.2 Transformer

4.3 Secondary side

4.4 Iso-buck operation principle

4.5 Soft-start and inhibit

4.6 Minimum On-Time

4.7 Output voltage line regulation

4.8 Output voltage load regulation

4.9 Overcurrent protection

4.10 Overvoltage protection

4.11 Thermal shutdown

5 Closing the loop

5.1 GCO(s)control to output transfer function

5.2 Error amplifier compensation network

5.3 Voltage divider

5.4 Total loop gain

5.5 Compensation network design

6 Application notes

6.1 Output voltage adjustment

6.2 Switching frequency

6.3 Voltage supervisor

6.4 Synchronization

6.4.1 Embedded master - slave synchronization

6.4.2 External synchronization signal

6.5 Design of the external components

6.5.1 Input capacitor selection

6.5.2 Transformer selection

6.5.3 Schottky diode

6.5.4 Output capacitors selection

7 Application example

620 W82 p F

8 Application board

8 R12

8.1 Fine tuning of the evaluation boards

8.2 Load regulation of the evaluation boards

9 Package information

9.1 HTSSOP16 package information

Package information

Ordering information

Revision history

Contents

L6986I specifications and overview.

More parts from the same family.